1 From 54eece496d38fb701d9719169d9270d8798191cc Mon Sep 17 00:00:00 2001
2 From: Martin Sperl <kernel@martin.sperl.org>
3 Date: Mon, 29 Feb 2016 11:39:20 +0000
4 Subject: [PATCH 258/304] clk: bcm2835: divider value has to be 1 or more
6 Current clamping of a normal divider allows a value < 1 to be valid.
8 A divider of < 1 would actually only be possible if we had a PLL...
10 So this patch clamps the divider to 1.
12 Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
15 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
16 Signed-off-by: Eric Anholt <eric@anholt.net>
17 Reviewed-by: Eric Anholt <eric@anholt.net>
18 (cherry picked from commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e)
20 drivers/clk/bcm/clk-bcm2835.c | 5 +++--
21 1 file changed, 3 insertions(+), 2 deletions(-)
23 --- a/drivers/clk/bcm/clk-bcm2835.c
24 +++ b/drivers/clk/bcm/clk-bcm2835.c
25 @@ -1202,8 +1202,9 @@ static u32 bcm2835_clock_choose_div(stru
26 div += unused_frac_mask + 1;
27 div &= ~unused_frac_mask;
29 - /* Clamp to the limits. */
30 - div = max(div, unused_frac_mask + 1);
31 + /* clamp to min divider of 1 */
32 + div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
33 + /* clamp to the highest possible fractional divider */
34 div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
35 CM_DIV_FRAC_BITS - data->frac_bits));