1 From 6efb6018b84fa3e5fefb69a097db05b6a0a6ba09 Mon Sep 17 00:00:00 2001
2 From: Martin Sperl <kernel@martin.sperl.org>
3 Date: Mon, 29 Feb 2016 12:51:42 +0000
4 Subject: [PATCH] clk: bcm2835: reorganize bcm2835_clock_array assignment
6 Reorganize bcm2835_clock_array so that there is no more
7 need for separate bcm2835_*_data structures to be defined.
8 Instead the required structures are generated inline via
11 To allow this to also work for pll alone it was required that
12 the parent_pll was changed from a pointer to bcm2835_pll_data
13 to the name of the pll instead.
15 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
16 Signed-off-by: Eric Anholt <eric@anholt.net>
17 Reviewed-by: Eric Anholt <eric@anholt.net>
18 (cherry picked from commit 3b15afefbef9b5952e3d68ad73d93f981b9faca8)
20 drivers/clk/bcm/clk-bcm2835.c | 852 +++++++++++++++++++-----------------------
21 1 file changed, 393 insertions(+), 459 deletions(-)
23 --- a/drivers/clk/bcm/clk-bcm2835.c
24 +++ b/drivers/clk/bcm/clk-bcm2835.c
25 @@ -418,115 +418,10 @@ static const struct bcm2835_pll_ana_bits
26 .fb_prediv_mask = BIT(11),
30 - * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
31 - * Port 2) transmitter clock.
33 - * It is in the PX LDO power domain, which is on when the AUDIO domain
36 -static const struct bcm2835_pll_data bcm2835_plla_data = {
38 - .cm_ctrl_reg = CM_PLLA,
39 - .a2w_ctrl_reg = A2W_PLLA_CTRL,
40 - .frac_reg = A2W_PLLA_FRAC,
41 - .ana_reg_base = A2W_PLLA_ANA0,
42 - .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
43 - .lock_mask = CM_LOCK_FLOCKA,
45 - .ana = &bcm2835_ana_default,
47 - .min_rate = 600000000u,
48 - .max_rate = 2400000000u,
49 - .max_fb_rate = BCM2835_MAX_FB_RATE,
52 -/* PLLB is used for the ARM's clock. */
53 -static const struct bcm2835_pll_data bcm2835_pllb_data = {
55 - .cm_ctrl_reg = CM_PLLB,
56 - .a2w_ctrl_reg = A2W_PLLB_CTRL,
57 - .frac_reg = A2W_PLLB_FRAC,
58 - .ana_reg_base = A2W_PLLB_ANA0,
59 - .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
60 - .lock_mask = CM_LOCK_FLOCKB,
62 - .ana = &bcm2835_ana_default,
64 - .min_rate = 600000000u,
65 - .max_rate = 3000000000u,
66 - .max_fb_rate = BCM2835_MAX_FB_RATE,
70 - * PLLC is the core PLL, used to drive the core VPU clock.
72 - * It is in the PX LDO power domain, which is on when the AUDIO domain
75 -static const struct bcm2835_pll_data bcm2835_pllc_data = {
77 - .cm_ctrl_reg = CM_PLLC,
78 - .a2w_ctrl_reg = A2W_PLLC_CTRL,
79 - .frac_reg = A2W_PLLC_FRAC,
80 - .ana_reg_base = A2W_PLLC_ANA0,
81 - .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
82 - .lock_mask = CM_LOCK_FLOCKC,
84 - .ana = &bcm2835_ana_default,
86 - .min_rate = 600000000u,
87 - .max_rate = 3000000000u,
88 - .max_fb_rate = BCM2835_MAX_FB_RATE,
92 - * PLLD is the display PLL, used to drive DSI display panels.
94 - * It is in the PX LDO power domain, which is on when the AUDIO domain
97 -static const struct bcm2835_pll_data bcm2835_plld_data = {
99 - .cm_ctrl_reg = CM_PLLD,
100 - .a2w_ctrl_reg = A2W_PLLD_CTRL,
101 - .frac_reg = A2W_PLLD_FRAC,
102 - .ana_reg_base = A2W_PLLD_ANA0,
103 - .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
104 - .lock_mask = CM_LOCK_FLOCKD,
106 - .ana = &bcm2835_ana_default,
108 - .min_rate = 600000000u,
109 - .max_rate = 2400000000u,
110 - .max_fb_rate = BCM2835_MAX_FB_RATE,
114 - * PLLH is used to supply the pixel clock or the AUX clock for the TV
117 - * It is in the HDMI power domain.
119 -static const struct bcm2835_pll_data bcm2835_pllh_data = {
121 - .cm_ctrl_reg = CM_PLLH,
122 - .a2w_ctrl_reg = A2W_PLLH_CTRL,
123 - .frac_reg = A2W_PLLH_FRAC,
124 - .ana_reg_base = A2W_PLLH_ANA0,
125 - .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
126 - .lock_mask = CM_LOCK_FLOCKH,
128 - .ana = &bcm2835_ana_pllh,
130 - .min_rate = 600000000u,
131 - .max_rate = 3000000000u,
132 - .max_fb_rate = BCM2835_MAX_FB_RATE,
135 struct bcm2835_pll_divider_data {
137 - const struct bcm2835_pll_data *source_pll;
138 + const char *source_pll;
143 @@ -535,124 +430,6 @@ struct bcm2835_pll_divider_data {
147 -static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
148 - .name = "plla_core",
149 - .source_pll = &bcm2835_plla_data,
151 - .a2w_reg = A2W_PLLA_CORE,
152 - .load_mask = CM_PLLA_LOADCORE,
153 - .hold_mask = CM_PLLA_HOLDCORE,
154 - .fixed_divider = 1,
157 -static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
158 - .name = "plla_per",
159 - .source_pll = &bcm2835_plla_data,
161 - .a2w_reg = A2W_PLLA_PER,
162 - .load_mask = CM_PLLA_LOADPER,
163 - .hold_mask = CM_PLLA_HOLDPER,
164 - .fixed_divider = 1,
167 -static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
168 - .name = "pllb_arm",
169 - .source_pll = &bcm2835_pllb_data,
171 - .a2w_reg = A2W_PLLB_ARM,
172 - .load_mask = CM_PLLB_LOADARM,
173 - .hold_mask = CM_PLLB_HOLDARM,
174 - .fixed_divider = 1,
177 -static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
178 - .name = "pllc_core0",
179 - .source_pll = &bcm2835_pllc_data,
181 - .a2w_reg = A2W_PLLC_CORE0,
182 - .load_mask = CM_PLLC_LOADCORE0,
183 - .hold_mask = CM_PLLC_HOLDCORE0,
184 - .fixed_divider = 1,
187 -static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
188 - .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
189 - .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
190 - .load_mask = CM_PLLC_LOADCORE1,
191 - .hold_mask = CM_PLLC_HOLDCORE1,
192 - .fixed_divider = 1,
195 -static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
196 - .name = "pllc_core2",
197 - .source_pll = &bcm2835_pllc_data,
199 - .a2w_reg = A2W_PLLC_CORE2,
200 - .load_mask = CM_PLLC_LOADCORE2,
201 - .hold_mask = CM_PLLC_HOLDCORE2,
202 - .fixed_divider = 1,
205 -static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
206 - .name = "pllc_per",
207 - .source_pll = &bcm2835_pllc_data,
209 - .a2w_reg = A2W_PLLC_PER,
210 - .load_mask = CM_PLLC_LOADPER,
211 - .hold_mask = CM_PLLC_HOLDPER,
212 - .fixed_divider = 1,
215 -static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
216 - .name = "plld_core",
217 - .source_pll = &bcm2835_plld_data,
219 - .a2w_reg = A2W_PLLD_CORE,
220 - .load_mask = CM_PLLD_LOADCORE,
221 - .hold_mask = CM_PLLD_HOLDCORE,
222 - .fixed_divider = 1,
225 -static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
226 - .name = "plld_per",
227 - .source_pll = &bcm2835_plld_data,
229 - .a2w_reg = A2W_PLLD_PER,
230 - .load_mask = CM_PLLD_LOADPER,
231 - .hold_mask = CM_PLLD_HOLDPER,
232 - .fixed_divider = 1,
235 -static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
236 - .name = "pllh_rcal",
237 - .source_pll = &bcm2835_pllh_data,
239 - .a2w_reg = A2W_PLLH_RCAL,
240 - .load_mask = CM_PLLH_LOADRCAL,
242 - .fixed_divider = 10,
245 -static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
246 - .name = "pllh_aux",
247 - .source_pll = &bcm2835_pllh_data,
249 - .a2w_reg = A2W_PLLH_AUX,
250 - .load_mask = CM_PLLH_LOADAUX,
252 - .fixed_divider = 10,
255 -static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
256 - .name = "pllh_pix",
257 - .source_pll = &bcm2835_pllh_data,
259 - .a2w_reg = A2W_PLLH_PIX,
260 - .load_mask = CM_PLLH_LOADPIX,
262 - .fixed_divider = 10,
265 struct bcm2835_clock_data {
268 @@ -671,188 +448,6 @@ struct bcm2835_clock_data {
272 -static const char *const bcm2835_clock_per_parents[] = {
283 -static const char *const bcm2835_clock_vpu_parents[] = {
296 -static const char *const bcm2835_clock_osc_parents[] = {
304 - * Used for a 1Mhz clock for the system clocksource, and also used by
305 - * the watchdog timer and the camera pulse generator.
307 -static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
309 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
310 - .parents = bcm2835_clock_osc_parents,
311 - .ctl_reg = CM_TIMERCTL,
312 - .div_reg = CM_TIMERDIV,
317 -/* One Time Programmable Memory clock. Maximum 10Mhz. */
318 -static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
320 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
321 - .parents = bcm2835_clock_osc_parents,
322 - .ctl_reg = CM_OTPCTL,
323 - .div_reg = CM_OTPDIV,
329 - * VPU clock. This doesn't have an enable bit, since it drives the
330 - * bus for everything else, and is special so it doesn't need to be
331 - * gated for rate changes. It is also known as "clk_audio" in various
332 - * hardware documentation.
334 -static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
336 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
337 - .parents = bcm2835_clock_vpu_parents,
338 - .ctl_reg = CM_VPUCTL,
339 - .div_reg = CM_VPUDIV,
342 - .is_vpu_clock = true,
345 -static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
347 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
348 - .parents = bcm2835_clock_vpu_parents,
349 - .ctl_reg = CM_V3DCTL,
350 - .div_reg = CM_V3DDIV,
355 -static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
357 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
358 - .parents = bcm2835_clock_vpu_parents,
359 - .ctl_reg = CM_ISPCTL,
360 - .div_reg = CM_ISPDIV,
365 -static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
367 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
368 - .parents = bcm2835_clock_vpu_parents,
369 - .ctl_reg = CM_H264CTL,
370 - .div_reg = CM_H264DIV,
375 -/* TV encoder clock. Only operating frequency is 108Mhz. */
376 -static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
378 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
379 - .parents = bcm2835_clock_per_parents,
380 - .ctl_reg = CM_VECCTL,
381 - .div_reg = CM_VECDIV,
386 -static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
388 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
389 - .parents = bcm2835_clock_per_parents,
390 - .ctl_reg = CM_UARTCTL,
391 - .div_reg = CM_UARTDIV,
396 -/* HDMI state machine */
397 -static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
399 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
400 - .parents = bcm2835_clock_per_parents,
401 - .ctl_reg = CM_HSMCTL,
402 - .div_reg = CM_HSMDIV,
408 - * Secondary SDRAM clock. Used for low-voltage modes when the PLL in
409 - * the SDRAM controller can't be used.
411 -static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
413 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
414 - .parents = bcm2835_clock_vpu_parents,
415 - .ctl_reg = CM_SDCCTL,
416 - .div_reg = CM_SDCDIV,
421 -/* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */
422 -static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
424 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
425 - .parents = bcm2835_clock_osc_parents,
426 - .ctl_reg = CM_TSENSCTL,
427 - .div_reg = CM_TSENSDIV,
432 -/* Arasan EMMC clock */
433 -static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
435 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
436 - .parents = bcm2835_clock_per_parents,
437 - .ctl_reg = CM_EMMCCTL,
438 - .div_reg = CM_EMMCDIV,
443 -static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
445 - .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
446 - .parents = bcm2835_clock_per_parents,
447 - .ctl_reg = CM_PWMCTL,
448 - .div_reg = CM_PWMDIV,
451 - .is_mash_clock = true,
454 struct bcm2835_gate_data {
457 @@ -860,18 +455,6 @@ struct bcm2835_gate_data {
462 - * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
463 - * you have the debug bit set in the power manager, which we
464 - * don't bother exposing) are individual gates off of the
465 - * non-stop vpu clock.
467 -static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
468 - .name = "peri_image",
470 - .ctl_reg = CM_PERIICTL,
475 struct bcm2835_cprman *cprman;
476 @@ -1596,7 +1179,7 @@ bcm2835_register_pll_divider(struct bcm2
478 memset(&init, 0, sizeof(init));
480 - init.parent_names = &data->source_pll->name;
481 + init.parent_names = &data->source_pll;
482 init.num_parents = 1;
483 init.name = divider_name;
484 init.ops = &bcm2835_pll_divider_clk_ops;
485 @@ -1695,50 +1278,401 @@ struct bcm2835_clk_desc {
489 -#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
491 -#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
492 -#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
493 -#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
494 -#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
495 +/* assignment helper macros for different clock types */
496 +#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
497 + .data = __VA_ARGS__ }
498 +#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
499 + &(struct bcm2835_pll_data) \
501 +#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
502 + &(struct bcm2835_pll_divider_data) \
504 +#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
505 + &(struct bcm2835_clock_data) \
507 +#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
508 + &(struct bcm2835_gate_data) \
511 +/* parent mux arrays plus helper macros */
513 +/* main oscillator parent mux */
514 +static const char *const bcm2835_clock_osc_parents[] = {
521 +#define REGISTER_OSC_CLK(...) REGISTER_CLK( \
522 + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
523 + .parents = bcm2835_clock_osc_parents, \
526 +/* main peripherial parent mux */
527 +static const char *const bcm2835_clock_per_parents[] = {
538 +#define REGISTER_PER_CLK(...) REGISTER_CLK( \
539 + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
540 + .parents = bcm2835_clock_per_parents, \
543 +/* main vpu parent mux */
544 +static const char *const bcm2835_clock_vpu_parents[] = {
557 +#define REGISTER_VPU_CLK(...) REGISTER_CLK( \
558 + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
559 + .parents = bcm2835_clock_vpu_parents, \
563 + * the real definition of all the pll, pll_dividers and clocks
564 + * these make use of the above REGISTER_* macros
566 static const struct bcm2835_clk_desc clk_desc_array[] = {
568 - [BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
569 - [BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
570 - [BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
571 - [BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
572 - [BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
573 - /* the PLL dividers */
574 - [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
575 - [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
576 - [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
577 - [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
578 - [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
579 - [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
580 - [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
581 - [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
582 - [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
583 - [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
584 - [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
585 + /* the PLL + PLL dividers */
588 + * PLLA is the auxiliary PLL, used to drive the CCP2
589 + * (Compact Camera Port 2) transmitter clock.
591 + * It is in the PX LDO power domain, which is on when the
592 + * AUDIO domain is on.
594 + [BCM2835_PLLA] = REGISTER_PLL(
596 + .cm_ctrl_reg = CM_PLLA,
597 + .a2w_ctrl_reg = A2W_PLLA_CTRL,
598 + .frac_reg = A2W_PLLA_FRAC,
599 + .ana_reg_base = A2W_PLLA_ANA0,
600 + .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
601 + .lock_mask = CM_LOCK_FLOCKA,
603 + .ana = &bcm2835_ana_default,
605 + .min_rate = 600000000u,
606 + .max_rate = 2400000000u,
607 + .max_fb_rate = BCM2835_MAX_FB_RATE),
608 + [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
609 + .name = "plla_core",
610 + .source_pll = "plla",
612 + .a2w_reg = A2W_PLLA_CORE,
613 + .load_mask = CM_PLLA_LOADCORE,
614 + .hold_mask = CM_PLLA_HOLDCORE,
615 + .fixed_divider = 1),
616 + [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
617 + .name = "plla_per",
618 + .source_pll = "plla",
620 + .a2w_reg = A2W_PLLA_PER,
621 + .load_mask = CM_PLLA_LOADPER,
622 + .hold_mask = CM_PLLA_HOLDPER,
623 + .fixed_divider = 1),
625 + /* PLLB is used for the ARM's clock. */
626 + [BCM2835_PLLB] = REGISTER_PLL(
628 + .cm_ctrl_reg = CM_PLLB,
629 + .a2w_ctrl_reg = A2W_PLLB_CTRL,
630 + .frac_reg = A2W_PLLB_FRAC,
631 + .ana_reg_base = A2W_PLLB_ANA0,
632 + .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
633 + .lock_mask = CM_LOCK_FLOCKB,
635 + .ana = &bcm2835_ana_default,
637 + .min_rate = 600000000u,
638 + .max_rate = 3000000000u,
639 + .max_fb_rate = BCM2835_MAX_FB_RATE),
640 + [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
641 + .name = "pllb_arm",
642 + .source_pll = "pllb",
644 + .a2w_reg = A2W_PLLB_ARM,
645 + .load_mask = CM_PLLB_LOADARM,
646 + .hold_mask = CM_PLLB_HOLDARM,
647 + .fixed_divider = 1),
650 + * PLLC is the core PLL, used to drive the core VPU clock.
652 + * It is in the PX LDO power domain, which is on when the
653 + * AUDIO domain is on.
655 + [BCM2835_PLLC] = REGISTER_PLL(
657 + .cm_ctrl_reg = CM_PLLC,
658 + .a2w_ctrl_reg = A2W_PLLC_CTRL,
659 + .frac_reg = A2W_PLLC_FRAC,
660 + .ana_reg_base = A2W_PLLC_ANA0,
661 + .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
662 + .lock_mask = CM_LOCK_FLOCKC,
664 + .ana = &bcm2835_ana_default,
666 + .min_rate = 600000000u,
667 + .max_rate = 3000000000u,
668 + .max_fb_rate = BCM2835_MAX_FB_RATE),
669 + [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
670 + .name = "pllc_core0",
671 + .source_pll = "pllc",
673 + .a2w_reg = A2W_PLLC_CORE0,
674 + .load_mask = CM_PLLC_LOADCORE0,
675 + .hold_mask = CM_PLLC_HOLDCORE0,
676 + .fixed_divider = 1),
677 + [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
678 + .name = "pllc_core1",
679 + .source_pll = "pllc",
681 + .a2w_reg = A2W_PLLC_CORE1,
682 + .load_mask = CM_PLLC_LOADCORE1,
683 + .hold_mask = CM_PLLC_HOLDCORE1,
684 + .fixed_divider = 1),
685 + [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
686 + .name = "pllc_core2",
687 + .source_pll = "pllc",
689 + .a2w_reg = A2W_PLLC_CORE2,
690 + .load_mask = CM_PLLC_LOADCORE2,
691 + .hold_mask = CM_PLLC_HOLDCORE2,
692 + .fixed_divider = 1),
693 + [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
694 + .name = "pllc_per",
695 + .source_pll = "pllc",
697 + .a2w_reg = A2W_PLLC_PER,
698 + .load_mask = CM_PLLC_LOADPER,
699 + .hold_mask = CM_PLLC_HOLDPER,
700 + .fixed_divider = 1),
703 + * PLLD is the display PLL, used to drive DSI display panels.
705 + * It is in the PX LDO power domain, which is on when the
706 + * AUDIO domain is on.
708 + [BCM2835_PLLD] = REGISTER_PLL(
710 + .cm_ctrl_reg = CM_PLLD,
711 + .a2w_ctrl_reg = A2W_PLLD_CTRL,
712 + .frac_reg = A2W_PLLD_FRAC,
713 + .ana_reg_base = A2W_PLLD_ANA0,
714 + .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
715 + .lock_mask = CM_LOCK_FLOCKD,
717 + .ana = &bcm2835_ana_default,
719 + .min_rate = 600000000u,
720 + .max_rate = 2400000000u,
721 + .max_fb_rate = BCM2835_MAX_FB_RATE),
722 + [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
723 + .name = "plld_core",
724 + .source_pll = "plld",
726 + .a2w_reg = A2W_PLLD_CORE,
727 + .load_mask = CM_PLLD_LOADCORE,
728 + .hold_mask = CM_PLLD_HOLDCORE,
729 + .fixed_divider = 1),
730 + [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
731 + .name = "plld_per",
732 + .source_pll = "plld",
734 + .a2w_reg = A2W_PLLD_PER,
735 + .load_mask = CM_PLLD_LOADPER,
736 + .hold_mask = CM_PLLD_HOLDPER,
737 + .fixed_divider = 1),
740 + * PLLH is used to supply the pixel clock or the AUX clock for the
743 + * It is in the HDMI power domain.
745 + [BCM2835_PLLH] = REGISTER_PLL(
747 + .cm_ctrl_reg = CM_PLLH,
748 + .a2w_ctrl_reg = A2W_PLLH_CTRL,
749 + .frac_reg = A2W_PLLH_FRAC,
750 + .ana_reg_base = A2W_PLLH_ANA0,
751 + .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
752 + .lock_mask = CM_LOCK_FLOCKH,
754 + .ana = &bcm2835_ana_pllh,
756 + .min_rate = 600000000u,
757 + .max_rate = 3000000000u,
758 + .max_fb_rate = BCM2835_MAX_FB_RATE),
759 + [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
760 + .name = "pllh_rcal",
761 + .source_pll = "pllh",
763 + .a2w_reg = A2W_PLLH_RCAL,
764 + .load_mask = CM_PLLH_LOADRCAL,
766 + .fixed_divider = 10),
767 + [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
768 + .name = "pllh_aux",
769 + .source_pll = "pllh",
771 + .a2w_reg = A2W_PLLH_AUX,
772 + .load_mask = CM_PLLH_LOADAUX,
774 + .fixed_divider = 10),
775 + [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
776 + .name = "pllh_pix",
777 + .source_pll = "pllh",
779 + .a2w_reg = A2W_PLLH_PIX,
780 + .load_mask = CM_PLLH_LOADPIX,
782 + .fixed_divider = 10),
785 - [BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
786 - [BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
787 - [BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
788 - [BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
789 - [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
790 - [BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
791 - [BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
792 - [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
793 - [BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
794 - [BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
795 - [BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
796 - [BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
797 - [BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
798 - [BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
800 + /* clocks with oscillator parent mux */
802 + /* One Time Programmable Memory clock. Maximum 10Mhz. */
803 + [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
805 + .ctl_reg = CM_OTPCTL,
806 + .div_reg = CM_OTPDIV,
810 + * Used for a 1Mhz clock for the system clocksource, and also used
811 + * bythe watchdog timer and the camera pulse generator.
813 + [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
815 + .ctl_reg = CM_TIMERCTL,
816 + .div_reg = CM_TIMERDIV,
820 + * Clock for the temperature sensor.
821 + * Generally run at 2Mhz, max 5Mhz.
823 + [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
825 + .ctl_reg = CM_TSENSCTL,
826 + .div_reg = CM_TSENSDIV,
830 + /* clocks with vpu parent mux */
831 + [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
833 + .ctl_reg = CM_H264CTL,
834 + .div_reg = CM_H264DIV,
837 + [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
839 + .ctl_reg = CM_ISPCTL,
840 + .div_reg = CM_ISPDIV,
844 + * Secondary SDRAM clock. Used for low-voltage modes when the PLL
845 + * in the SDRAM controller can't be used.
847 + [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
849 + .ctl_reg = CM_SDCCTL,
850 + .div_reg = CM_SDCDIV,
853 + [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
855 + .ctl_reg = CM_V3DCTL,
856 + .div_reg = CM_V3DDIV,
860 + * VPU clock. This doesn't have an enable bit, since it drives
861 + * the bus for everything else, and is special so it doesn't need
862 + * to be gated for rate changes. It is also known as "clk_audio"
863 + * in various hardware documentation.
865 + [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
867 + .ctl_reg = CM_VPUCTL,
868 + .div_reg = CM_VPUDIV,
871 + .is_vpu_clock = true),
873 + /* clocks with per parent mux */
875 + /* Arasan EMMC clock */
876 + [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
878 + .ctl_reg = CM_EMMCCTL,
879 + .div_reg = CM_EMMCDIV,
882 + /* HDMI state machine */
883 + [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
885 + .ctl_reg = CM_HSMCTL,
886 + .div_reg = CM_HSMDIV,
889 + [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
891 + .ctl_reg = CM_PWMCTL,
892 + .div_reg = CM_PWMDIV,
895 + .is_mash_clock = true),
896 + [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
898 + .ctl_reg = CM_UARTCTL,
899 + .div_reg = CM_UARTDIV,
902 + /* TV encoder clock. Only operating frequency is 108Mhz. */
903 + [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
905 + .ctl_reg = CM_VECCTL,
906 + .div_reg = CM_VECDIV,
913 + * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
914 + * you have the debug bit set in the power manager, which we
915 + * don't bother exposing) are individual gates off of the
916 + * non-stop vpu clock.
918 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
919 - &bcm2835_clock_peri_image_data),
920 + .name = "peri_image",
922 + .ctl_reg = CM_PERIICTL),
925 static int bcm2835_clk_probe(struct platform_device *pdev)