1 From 4af3eff3ca4b361018749b00b71426fa23cc58a4 Mon Sep 17 00:00:00 2001
2 From: Martin Sperl <kernel@martin.sperl.org>
3 Date: Mon, 29 Feb 2016 12:51:41 +0000
4 Subject: [PATCH 261/381] clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in
7 As the use of BCM2835_CLOCK_COUNT in
8 include/dt-bindings/clock/bcm2835.h is frowned upon as
9 it needs to get modified every time a new clock gets introduced
10 this patch changes the clk-bcm2835 driver to use a different
11 scheme for registration of clocks and pll, so that there
12 is no more need for BCM2835_CLOCK_COUNT to be defined.
14 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
15 Signed-off-by: Eric Anholt <eric@anholt.net>
16 Reviewed-by: Eric Anholt <eric@anholt.net>
17 (cherry picked from commit 56eb3a2ed9726961e1bcfa69d4a3f86d68f0eb52)
19 drivers/clk/bcm/clk-bcm2835.c | 167 ++++++++++++++++++++----------------
20 include/dt-bindings/clock/bcm2835.h | 2 -
21 2 files changed, 94 insertions(+), 75 deletions(-)
23 --- a/drivers/clk/bcm/clk-bcm2835.c
24 +++ b/drivers/clk/bcm/clk-bcm2835.c
25 @@ -301,7 +301,7 @@ struct bcm2835_cprman {
28 struct clk_onecell_data onecell;
29 - struct clk *clks[BCM2835_CLOCK_COUNT];
33 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
34 @@ -853,6 +853,25 @@ static const struct bcm2835_clock_data b
35 .is_mash_clock = true,
38 +struct bcm2835_gate_data {
46 + * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
47 + * you have the debug bit set in the power manager, which we
48 + * don't bother exposing) are individual gates off of the
49 + * non-stop vpu clock.
51 +static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
52 + .name = "peri_image",
54 + .ctl_reg = CM_PERIICTL,
59 struct bcm2835_cprman *cprman;
60 @@ -1658,14 +1677,81 @@ static struct clk *bcm2835_register_cloc
61 return devm_clk_register(cprman->dev, &clock->hw);
64 +static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
65 + const struct bcm2835_gate_data *data)
67 + return clk_register_gate(cprman->dev, data->name, data->parent,
68 + CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
69 + cprman->regs + data->ctl_reg,
70 + CM_GATE_BIT, 0, &cprman->regs_lock);
73 +typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
75 +struct bcm2835_clk_desc {
76 + bcm2835_clk_register clk_register;
80 +#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
82 +#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
83 +#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
84 +#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
85 +#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
87 +static const struct bcm2835_clk_desc clk_desc_array[] = {
89 + [BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
90 + [BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
91 + [BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
92 + [BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
93 + [BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
94 + /* the PLL dividers */
95 + [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
96 + [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
97 + [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
98 + [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
99 + [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
100 + [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
101 + [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
102 + [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
103 + [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
104 + [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
105 + [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
107 + [BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
108 + [BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
109 + [BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
110 + [BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
111 + [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
112 + [BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
113 + [BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
114 + [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
115 + [BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
116 + [BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
117 + [BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
118 + [BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
119 + [BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
120 + [BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
122 + [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
123 + &bcm2835_clock_peri_image_data),
126 static int bcm2835_clk_probe(struct platform_device *pdev)
128 struct device *dev = &pdev->dev;
130 struct bcm2835_cprman *cprman;
131 struct resource *res;
132 + const struct bcm2835_clk_desc *desc;
133 + const size_t asize = ARRAY_SIZE(clk_desc_array);
136 - cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
137 + cprman = devm_kzalloc(dev,
138 + sizeof(*cprman) + asize * sizeof(*clks),
143 @@ -1682,80 +1768,15 @@ static int bcm2835_clk_probe(struct plat
145 platform_set_drvdata(pdev, cprman);
147 - cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
148 + cprman->onecell.clk_num = asize;
149 cprman->onecell.clks = cprman->clks;
152 - clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
153 - clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
154 - clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
155 - clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
156 - clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
158 - clks[BCM2835_PLLA_CORE] =
159 - bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
160 - clks[BCM2835_PLLA_PER] =
161 - bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
162 - clks[BCM2835_PLLC_CORE0] =
163 - bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
164 - clks[BCM2835_PLLC_CORE1] =
165 - bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
166 - clks[BCM2835_PLLC_CORE2] =
167 - bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
168 - clks[BCM2835_PLLC_PER] =
169 - bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
170 - clks[BCM2835_PLLD_CORE] =
171 - bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
172 - clks[BCM2835_PLLD_PER] =
173 - bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
174 - clks[BCM2835_PLLH_RCAL] =
175 - bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
176 - clks[BCM2835_PLLH_AUX] =
177 - bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
178 - clks[BCM2835_PLLH_PIX] =
179 - bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
181 - clks[BCM2835_CLOCK_TIMER] =
182 - bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
183 - clks[BCM2835_CLOCK_OTP] =
184 - bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
185 - clks[BCM2835_CLOCK_TSENS] =
186 - bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
187 - clks[BCM2835_CLOCK_VPU] =
188 - bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
189 - clks[BCM2835_CLOCK_V3D] =
190 - bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
191 - clks[BCM2835_CLOCK_ISP] =
192 - bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
193 - clks[BCM2835_CLOCK_H264] =
194 - bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
195 - clks[BCM2835_CLOCK_V3D] =
196 - bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
197 - clks[BCM2835_CLOCK_SDRAM] =
198 - bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
199 - clks[BCM2835_CLOCK_UART] =
200 - bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
201 - clks[BCM2835_CLOCK_VEC] =
202 - bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
203 - clks[BCM2835_CLOCK_HSM] =
204 - bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
205 - clks[BCM2835_CLOCK_EMMC] =
206 - bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
209 - * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
210 - * you have the debug bit set in the power manager, which we
211 - * don't bother exposing) are individual gates off of the
212 - * non-stop vpu clock.
214 - clks[BCM2835_CLOCK_PERI_IMAGE] =
215 - clk_register_gate(dev, "peri_image", "vpu",
216 - CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
217 - cprman->regs + CM_PERIICTL, CM_GATE_BIT,
218 - 0, &cprman->regs_lock);
220 - clks[BCM2835_CLOCK_PWM] =
221 - bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
222 + for (i = 0; i < asize; i++) {
223 + desc = &clk_desc_array[i];
224 + if (desc->clk_register && desc->data)
225 + clks[i] = desc->clk_register(cprman, desc->data);
228 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
230 --- a/include/dt-bindings/clock/bcm2835.h
231 +++ b/include/dt-bindings/clock/bcm2835.h
233 #define BCM2835_CLOCK_EMMC 28
234 #define BCM2835_CLOCK_PERI_IMAGE 29
235 #define BCM2835_CLOCK_PWM 30
237 -#define BCM2835_CLOCK_COUNT 31