1 From 787e7372d221fad5da0ee1ee74d3c42d409fb22b Mon Sep 17 00:00:00 2001
2 From: Martin Sperl <kernel@martin.sperl.org>
3 Date: Mon, 29 Feb 2016 15:43:57 +0000
4 Subject: [PATCH 265/381] clk: bcm2835: add missing osc and per clocks
6 Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E,
7 and DSI1E. PULSE is not added because it has an extra divider.
9 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
10 Signed-off-by: Eric Anholt <eric@anholt.net>
11 Reviewed-by: Eric Anholt <eric@anholt.net>
12 (cherry picked from commit d3d6f15fd376e3dbba851724057b112558c70b79)
14 drivers/clk/bcm/clk-bcm2835.c | 90 +++++++++++++++++++++++++++++++++++++
15 include/dt-bindings/clock/bcm2835.h | 14 ++++++
16 2 files changed, 104 insertions(+)
18 --- a/drivers/clk/bcm/clk-bcm2835.c
19 +++ b/drivers/clk/bcm/clk-bcm2835.c
21 #define CM_SDCCTL 0x1a8
22 #define CM_SDCDIV 0x1ac
23 #define CM_ARMCTL 0x1b0
24 +#define CM_AVEOCTL 0x1b8
25 +#define CM_AVEODIV 0x1bc
26 #define CM_EMMCCTL 0x1c0
27 #define CM_EMMCDIV 0x1c4
29 @@ -1606,6 +1608,12 @@ static const struct bcm2835_clk_desc clk
30 .div_reg = CM_TSENSDIV,
33 + [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
35 + .ctl_reg = CM_TECCTL,
36 + .div_reg = CM_TECDIV,
40 /* clocks with vpu parent mux */
41 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
42 @@ -1620,6 +1628,7 @@ static const struct bcm2835_clk_desc clk
48 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
49 * in the SDRAM controller can't be used.
50 @@ -1651,6 +1660,36 @@ static const struct bcm2835_clk_desc clk
51 .is_vpu_clock = true),
53 /* clocks with per parent mux */
54 + [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
56 + .ctl_reg = CM_AVEOCTL,
57 + .div_reg = CM_AVEODIV,
60 + [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
62 + .ctl_reg = CM_CAM0CTL,
63 + .div_reg = CM_CAM0DIV,
66 + [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
68 + .ctl_reg = CM_CAM1CTL,
69 + .div_reg = CM_CAM1DIV,
72 + [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
74 + .ctl_reg = CM_DFTCTL,
75 + .div_reg = CM_DFTDIV,
78 + [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
80 + .ctl_reg = CM_DPICTL,
81 + .div_reg = CM_DPIDIV,
85 /* Arasan EMMC clock */
86 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
87 @@ -1659,6 +1698,29 @@ static const struct bcm2835_clk_desc clk
88 .div_reg = CM_EMMCDIV,
92 + /* General purpose (GPIO) clocks */
93 + [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
95 + .ctl_reg = CM_GP0CTL,
96 + .div_reg = CM_GP0DIV,
99 + .is_mash_clock = true),
100 + [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
102 + .ctl_reg = CM_GP1CTL,
103 + .div_reg = CM_GP1DIV,
106 + .is_mash_clock = true),
107 + [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
109 + .ctl_reg = CM_GP2CTL,
110 + .div_reg = CM_GP2DIV,
114 /* HDMI state machine */
115 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
117 @@ -1680,12 +1742,26 @@ static const struct bcm2835_clk_desc clk
120 .is_mash_clock = true),
121 + [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
123 + .ctl_reg = CM_SLIMCTL,
124 + .div_reg = CM_SLIMDIV,
127 + .is_mash_clock = true),
128 + [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
130 + .ctl_reg = CM_SMICTL,
131 + .div_reg = CM_SMIDIV,
134 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
136 .ctl_reg = CM_UARTCTL,
137 .div_reg = CM_UARTDIV,
141 /* TV encoder clock. Only operating frequency is 108Mhz. */
142 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
144 @@ -1694,6 +1770,20 @@ static const struct bcm2835_clk_desc clk
149 + [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
151 + .ctl_reg = CM_DSI0ECTL,
152 + .div_reg = CM_DSI0EDIV,
155 + [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
157 + .ctl_reg = CM_DSI1ECTL,
158 + .div_reg = CM_DSI1EDIV,
165 --- a/include/dt-bindings/clock/bcm2835.h
166 +++ b/include/dt-bindings/clock/bcm2835.h
168 #define BCM2835_PLLA_CCP2 33
169 #define BCM2835_PLLD_DSI0 34
170 #define BCM2835_PLLD_DSI1 35
172 +#define BCM2835_CLOCK_AVEO 36
173 +#define BCM2835_CLOCK_DFT 37
174 +#define BCM2835_CLOCK_GP0 38
175 +#define BCM2835_CLOCK_GP1 39
176 +#define BCM2835_CLOCK_GP2 40
177 +#define BCM2835_CLOCK_SLIM 41
178 +#define BCM2835_CLOCK_SMI 42
179 +#define BCM2835_CLOCK_TEC 43
180 +#define BCM2835_CLOCK_DPI 44
181 +#define BCM2835_CLOCK_CAM0 45
182 +#define BCM2835_CLOCK_CAM1 46
183 +#define BCM2835_CLOCK_DSI0E 47
184 +#define BCM2835_CLOCK_DSI1E 48