1 From a0d015caa8ddfd37ae8cbfc7aec1d614b5ad3b78 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Mon, 15 Feb 2016 17:31:41 -0800
4 Subject: [PATCH 292/304] drm/vc4: Fix setting of vertical timings in the CRTC.
6 It looks like when I went to add the interlaced bits, I just took the
7 existing PV_VERT* block and indented it, instead of copy and pasting
8 it first. Without this, changing resolution never worked.
10 Signed-off-by: Eric Anholt <eric@anholt.net>
11 (cherry picked from commit a7c5047d1ce178dd2b1fa577fc8909ad663d56d5)
13 drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++
14 1 file changed, 10 insertions(+)
16 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
17 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
18 @@ -217,6 +217,16 @@ static void vc4_crtc_mode_set_nofb(struc
20 VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
22 + CRTC_WRITE(PV_VERTA,
23 + VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
25 + VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
27 + CRTC_WRITE(PV_VERTB,
28 + VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
30 + VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
33 CRTC_WRITE(PV_VERTA_EVEN,
34 VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,