1 From 6af02628d1704bf16359696593246bbb78222363 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Sat, 2 Jul 2016 09:57:07 -0700
4 Subject: [PATCH] drm/vc4: Move validation's current/max ip into the validation
7 Reduces the argument count for some of the functions, and will be used
8 more with the upcoming looping support.
10 Signed-off-by: Eric Anholt <eric@anholt.net>
11 (cherry picked from commit d0566c2a2f2baacefe1eb75be8a001fdd6fe84a3)
13 drivers/gpu/drm/vc4/vc4_validate_shaders.c | 54 +++++++++++++++++-------------
14 1 file changed, 30 insertions(+), 24 deletions(-)
16 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
17 +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
19 #include "vc4_qpu_defines.h"
21 struct vc4_shader_validation_state {
22 + /* Current IP being validated. */
25 + /* IP at the end of the BO, do not read shader[max_ip] */
30 struct vc4_texture_sample_info tmu_setup[2];
31 int tmu_write_count[2];
33 @@ -129,11 +137,11 @@ record_texture_sample(struct vc4_validat
37 -check_tmu_write(uint64_t inst,
38 - struct vc4_validated_shader_info *validated_shader,
39 +check_tmu_write(struct vc4_validated_shader_info *validated_shader,
40 struct vc4_shader_validation_state *validation_state,
43 + uint64_t inst = validation_state->shader[validation_state->ip];
44 uint32_t waddr = (is_mul ?
45 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
46 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
47 @@ -228,11 +236,11 @@ check_tmu_write(uint64_t inst,
51 -check_reg_write(uint64_t inst,
52 - struct vc4_validated_shader_info *validated_shader,
53 +check_reg_write(struct vc4_validated_shader_info *validated_shader,
54 struct vc4_shader_validation_state *validation_state,
57 + uint64_t inst = validation_state->shader[validation_state->ip];
58 uint32_t waddr = (is_mul ?
59 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
60 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
61 @@ -261,7 +269,7 @@ check_reg_write(uint64_t inst,
65 - return check_tmu_write(inst, validated_shader, validation_state,
66 + return check_tmu_write(validated_shader, validation_state,
70 @@ -294,10 +302,10 @@ check_reg_write(uint64_t inst,
74 -track_live_clamps(uint64_t inst,
75 - struct vc4_validated_shader_info *validated_shader,
76 +track_live_clamps(struct vc4_validated_shader_info *validated_shader,
77 struct vc4_shader_validation_state *validation_state)
79 + uint64_t inst = validation_state->shader[validation_state->ip];
80 uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
81 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
82 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
83 @@ -369,10 +377,10 @@ track_live_clamps(uint64_t inst,
87 -check_instruction_writes(uint64_t inst,
88 - struct vc4_validated_shader_info *validated_shader,
89 +check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
90 struct vc4_shader_validation_state *validation_state)
92 + uint64_t inst = validation_state->shader[validation_state->ip];
93 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
94 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
96 @@ -382,12 +390,10 @@ check_instruction_writes(uint64_t inst,
100 - ok = (check_reg_write(inst, validated_shader, validation_state,
102 - check_reg_write(inst, validated_shader, validation_state,
104 + ok = (check_reg_write(validated_shader, validation_state, false) &&
105 + check_reg_write(validated_shader, validation_state, true));
107 - track_live_clamps(inst, validated_shader, validation_state);
108 + track_live_clamps(validated_shader, validation_state);
112 @@ -417,30 +423,30 @@ vc4_validate_shader(struct drm_gem_cma_o
114 bool found_shader_end = false;
115 int shader_end_ip = 0;
116 - uint32_t ip, max_ip;
119 struct vc4_validated_shader_info *validated_shader;
120 struct vc4_shader_validation_state validation_state;
123 memset(&validation_state, 0, sizeof(validation_state));
124 + validation_state.shader = shader_obj->vaddr;
125 + validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
127 for (i = 0; i < 8; i++)
128 validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
129 for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
130 validation_state.live_min_clamp_offsets[i] = ~0;
132 - shader = shader_obj->vaddr;
133 - max_ip = shader_obj->base.size / sizeof(uint64_t);
135 validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
136 if (!validated_shader)
139 - for (ip = 0; ip < max_ip; ip++) {
140 - uint64_t inst = shader[ip];
141 + for (ip = 0; ip < validation_state.max_ip; ip++) {
142 + uint64_t inst = validation_state.shader[ip];
143 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
145 + validation_state.ip = ip;
149 case QPU_SIG_WAIT_FOR_SCOREBOARD:
150 @@ -450,7 +456,7 @@ vc4_validate_shader(struct drm_gem_cma_o
151 case QPU_SIG_LOAD_TMU1:
152 case QPU_SIG_PROG_END:
153 case QPU_SIG_SMALL_IMM:
154 - if (!check_instruction_writes(inst, validated_shader,
155 + if (!check_instruction_writes(validated_shader,
156 &validation_state)) {
157 DRM_ERROR("Bad write at ip %d\n", ip);
159 @@ -467,7 +473,7 @@ vc4_validate_shader(struct drm_gem_cma_o
162 case QPU_SIG_LOAD_IMM:
163 - if (!check_instruction_writes(inst, validated_shader,
164 + if (!check_instruction_writes(validated_shader,
165 &validation_state)) {
166 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
168 @@ -487,7 +493,7 @@ vc4_validate_shader(struct drm_gem_cma_o
172 - if (ip == max_ip) {
173 + if (ip == validation_state.max_ip) {
174 DRM_ERROR("shader failed to terminate before "
175 "shader BO end at %zd\n",
176 shader_obj->base.size);