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bcm47xx: Implement the remaining PMU resource inits.
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-2.6.28 / 810-ssb-add-pmu-support.patch
1 Index: linux-2.6.28.2/drivers/ssb/Makefile
2 ===================================================================
3 --- linux-2.6.28.2.orig/drivers/ssb/Makefile 2009-02-01 13:09:04.000000000 +0100
4 +++ linux-2.6.28.2/drivers/ssb/Makefile 2009-02-01 13:09:31.000000000 +0100
5 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
6
7 # built-in drivers
8 ssb-y += driver_chipcommon.o
9 +ssb-y += driver_chipcommon_pmu.o
10 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
11 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
12 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
13 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
14 ===================================================================
15 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
16 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-01 21:16:15.000000000 +0100
17 @@ -0,0 +1,378 @@
18 +/*
19 + * Sonics Silicon Backplane
20 + * Broadcom ChipCommon Power Management Unit driver
21 + *
22 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
23 + * Copyright 2007, Broadcom Corporation
24 + *
25 + * Licensed under the GNU/GPL. See COPYING for details.
26 + */
27 +
28 +#include <linux/ssb/ssb.h>
29 +#include <linux/ssb/ssb_regs.h>
30 +#include <linux/ssb/ssb_driver_chipcommon.h>
31 +#include <linux/delay.h>
32 +
33 +#include "ssb_private.h"
34 +
35 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
36 +{
37 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
38 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
39 +}
40 +
41 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
42 + u32 offset, u32 value)
43 +{
44 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
45 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
46 +}
47 +
48 +struct pmu0_plltab_entry {
49 + u16 freq; /* Crystal frequency in kHz.*/
50 + u8 xf; /* Crystal frequency value for PMU control */
51 + u8 wb_int;
52 + u32 wb_frac;
53 +};
54 +
55 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
56 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
57 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
58 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
59 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
60 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
61 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
62 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
63 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
64 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
65 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
66 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
67 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
68 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
69 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
70 +};
71 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
72 +
73 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
74 +{
75 + const struct pmu0_plltab_entry *e;
76 + unsigned int i;
77 +
78 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
79 + e = &pmu0_plltab[i];
80 + if (e->freq == crystalfreq)
81 + return e;
82 + }
83 +
84 + return NULL;
85 +}
86 +
87 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
88 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
89 + u32 crystalfreq)
90 +{
91 + struct ssb_bus *bus = cc->dev->bus;
92 + const struct pmu0_plltab_entry *e = NULL;
93 + u32 pmuctl, tmp, pllctl;
94 + unsigned int i;
95 +
96 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
97 + /* The 5354 crystal freq is 25MHz */
98 + crystalfreq = 25000;
99 + }
100 + if (crystalfreq)
101 + e = pmu0_plltab_find_entry(crystalfreq);
102 + if (!e)
103 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
104 + BUG_ON(!e);
105 + crystalfreq = e->freq;
106 + cc->pmu.crystalfreq = e->freq;
107 +
108 + /* Check if the PLL already is programmed to this frequency. */
109 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
110 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
111 + /* We're already there... */
112 + return;
113 + }
114 +
115 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
116 + (crystalfreq / 1000), (crystalfreq % 1000));
117 +
118 + /* First turn the PLL off. */
119 + switch (bus->chip_id) {
120 + case 0x4328:
121 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
122 + ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
123 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
124 + ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
125 + break;
126 + case 0x5354:
127 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
128 + ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
129 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
130 + ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
131 + break;
132 + default:
133 + SSB_WARN_ON(1);
134 + }
135 + for (i = 1500; i; i--) {
136 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
137 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
138 + break;
139 + udelay(10);
140 + }
141 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
142 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
143 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
144 +
145 + /* Set PDIV in PLL control 0. */
146 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
147 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
148 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
149 + else
150 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
151 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
152 +
153 + /* Set WILD in PLL control 1. */
154 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
155 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
156 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
157 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
158 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
159 + if (e->wb_frac == 0)
160 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
161 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
162 +
163 + /* Set WILD in PLL control 2. */
164 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
165 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
166 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
167 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
168 +
169 + /* Set the crystalfrequency and the divisor. */
170 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
171 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
172 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
173 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
174 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
175 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
176 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
177 +}
178 +
179 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
180 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
181 + u32 crystalfreq)
182 +{
183 + WARN_ON(1);
184 + //TODO
185 +}
186 +
187 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
188 +{
189 + struct ssb_bus *bus = cc->dev->bus;
190 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
191 +
192 + if (bus->bustype == SSB_BUSTYPE_SSB) {
193 + /* TODO: The user may override the crystal frequency. */
194 + }
195 +
196 + switch (bus->chip_id) {
197 + case 0x4312:
198 + case 0x4325:
199 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
200 + break;
201 + case 0x4328:
202 + case 0x5354:
203 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
204 + break;
205 + default:
206 + ssb_printk(KERN_ERR PFX
207 + "ERROR: PLL init unknown for device %04X\n",
208 + bus->chip_id);
209 + }
210 +}
211 +
212 +struct pmu_res_updown_tab_entry {
213 + u8 resource; /* The resource number */
214 + u16 updown; /* The updown value */
215 +};
216 +
217 +enum pmu_res_depend_tab_task {
218 + PMU_RES_DEP_SET = 1,
219 + PMU_RES_DEP_ADD,
220 + PMU_RES_DEP_REMOVE,
221 +};
222 +
223 +struct pmu_res_depend_tab_entry {
224 + u8 resource; /* The resource number */
225 + u8 task; /* SET | ADD | REMOVE */
226 + u32 depend; /* The depend mask */
227 +};
228 +
229 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
230 + { .resource = SSB_PLLRES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
231 + { .resource = SSB_PLLRES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
232 + { .resource = SSB_PLLRES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
233 + { .resource = SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
234 + { .resource = SSB_PLLRES_4328_ILP_REQUEST, .updown = 0x0202, },
235 + { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
236 + { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
237 + { .resource = SSB_PLLRES_4328_ROM_SWITCH, .updown = 0x0101, },
238 + { .resource = SSB_PLLRES_4328_PA_REF_LDO, .updown = 0x0F01, },
239 + { .resource = SSB_PLLRES_4328_RADIO_LDO, .updown = 0x0F01, },
240 + { .resource = SSB_PLLRES_4328_AFE_LDO, .updown = 0x0F01, },
241 + { .resource = SSB_PLLRES_4328_PLL_LDO, .updown = 0x0F01, },
242 + { .resource = SSB_PLLRES_4328_BG_FILTBYP, .updown = 0x0101, },
243 + { .resource = SSB_PLLRES_4328_TX_FILTBYP, .updown = 0x0101, },
244 + { .resource = SSB_PLLRES_4328_RX_FILTBYP, .updown = 0x0101, },
245 + { .resource = SSB_PLLRES_4328_XTAL_PU, .updown = 0x0101, },
246 + { .resource = SSB_PLLRES_4328_XTAL_EN, .updown = 0xA001, },
247 + { .resource = SSB_PLLRES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
248 + { .resource = SSB_PLLRES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
249 + { .resource = SSB_PLLRES_4328_BB_PLL_PU, .updown = 0x0701, },
250 +};
251 +
252 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
253 + {
254 + /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
255 + .resource = SSB_PLLRES_4328_ILP_REQUEST,
256 + .task = PMU_RES_DEP_SET,
257 + .depend = ((1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
258 + (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM)),
259 + },
260 +};
261 +
262 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
263 + { .resource = SSB_PLLRES_4325_XTAL_PU, .updown = 0x1501, },
264 +};
265 +
266 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
267 + {
268 + /* Adjust HT-Available dependencies. */
269 + .resource = SSB_PLLRES_4325_HT_AVAIL,
270 + .task = PMU_RES_DEP_ADD,
271 + .depend = ((1 << SSB_PLLRES_4325_RX_PWRSW_PU) |
272 + (1 << SSB_PLLRES_4325_TX_PWRSW_PU) |
273 + (1 << SSB_PLLRES_4325_LOGEN_PWRSW_PU) |
274 + (1 << SSB_PLLRES_4325_AFE_PWRSW_PU)),
275 + },
276 +};
277 +
278 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
279 +{
280 + struct ssb_bus *bus = cc->dev->bus;
281 + u32 min_msk = 0, max_msk = 0;
282 + unsigned int i;
283 + const struct pmu_res_updown_tab_entry *updown_tab = NULL;
284 + unsigned int updown_tab_size;
285 + const struct pmu_res_depend_tab_entry *depend_tab = NULL;
286 + unsigned int depend_tab_size;
287 +
288 + switch (bus->chip_id) {
289 + case 0x4312:
290 + /* We keep the default settings:
291 + * min_msk = 0xCBB
292 + * max_msk = 0x7FFFF
293 + */
294 + break;
295 + case 0x4325:
296 + /* Power OTP down later. */
297 + min_msk = (1 << SSB_PLLRES_4325_CBUCK_BURST) |
298 + (1 << SSB_PLLRES_4325_LNLDO2_PU);
299 + if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
300 + SSB_CHIPCO_CHST_4325_PMUTOP_2B)
301 + min_msk |= (1 << SSB_PLLRES_4325_CLDO_CBUCK_BURST);
302 + /* The PLL may turn on, if it decides so. */
303 + max_msk = 0xFFFFF;
304 + updown_tab = pmu_res_updown_tab_4325a0;
305 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
306 + depend_tab = pmu_res_depend_tab_4325a0;
307 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
308 + break;
309 + case 0x4328:
310 + min_msk = (1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
311 + (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM) |
312 + (1 << SSB_PLLRES_4328_XTAL_EN);
313 + /* The PLL may turn on, if it decides so. */
314 + max_msk = 0xFFFFF;
315 + updown_tab = pmu_res_updown_tab_4328a0;
316 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
317 + depend_tab = pmu_res_depend_tab_4328a0;
318 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
319 + break;
320 + case 0x5354:
321 + /* The PLL may turn on, if it decides so. */
322 + max_msk = 0xFFFFF;
323 + break;
324 + default:
325 + ssb_printk(KERN_ERR PFX
326 + "ERROR: PMU resource config unknown for device %04X\n",
327 + bus->chip_id);
328 + }
329 +
330 + if (updown_tab) {
331 + for (i = 0; i < updown_tab_size; i++) {
332 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
333 + updown_tab[i].resource);
334 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
335 + updown_tab[i].updown);
336 + }
337 + }
338 + if (depend_tab) {
339 + for (i = 0; i < depend_tab_size; i++) {
340 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
341 + depend_tab[i].resource);
342 + switch (depend_tab[i].task) {
343 + case PMU_RES_DEP_SET:
344 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
345 + depend_tab[i].depend);
346 + break;
347 + case PMU_RES_DEP_ADD:
348 + chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
349 + depend_tab[i].depend);
350 + break;
351 + case PMU_RES_DEP_REMOVE:
352 + chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
353 + ~(depend_tab[i].depend));
354 + break;
355 + default:
356 + SSB_WARN_ON(1);
357 + }
358 + }
359 + }
360 +
361 + /* Set the resource masks. */
362 + if (min_msk)
363 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
364 + if (max_msk)
365 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
366 +}
367 +
368 +void ssb_pmu_init(struct ssb_chipcommon *cc)
369 +{
370 + struct ssb_bus *bus = cc->dev->bus;
371 + u32 pmucap;
372 +
373 +if (bus->chip_id != 0x5354) return; //FIXME currently only 5354 code implemented.
374 +
375 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
376 + return;
377 +
378 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
379 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
380 +
381 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
382 + cc->pmu.rev, pmucap);
383 +
384 + if (cc->pmu.rev >= 1) {
385 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
386 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
387 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
388 + } else {
389 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
390 + SSB_CHIPCO_PMU_CTL_NOILPONW);
391 + }
392 + }
393 + ssb_pmu_pll_init(cc);
394 + ssb_pmu_resources_init(cc);
395 +}
396 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
397 ===================================================================
398 --- linux-2.6.28.2.orig/drivers/ssb/driver_chipcommon.c 2009-02-01 13:07:03.000000000 +0100
399 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon.c 2009-02-01 13:47:17.000000000 +0100
400 @@ -26,19 +26,6 @@ enum ssb_clksrc {
401 };
402
403
404 -static inline u32 chipco_read32(struct ssb_chipcommon *cc,
405 - u16 offset)
406 -{
407 - return ssb_read32(cc->dev, offset);
408 -}
409 -
410 -static inline void chipco_write32(struct ssb_chipcommon *cc,
411 - u16 offset,
412 - u32 value)
413 -{
414 - ssb_write32(cc->dev, offset, value);
415 -}
416 -
417 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
418 u32 mask, u32 value)
419 {
420 @@ -246,6 +233,7 @@ void ssb_chipcommon_init(struct ssb_chip
421 {
422 if (!cc->dev)
423 return; /* We don't have a ChipCommon */
424 + ssb_pmu_init(cc);
425 chipco_powercontrol_init(cc);
426 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
427 calc_fast_powerup_delay(cc);
428 Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
429 ===================================================================
430 --- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 13:22:59.000000000 +0100
431 +++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 21:09:37.000000000 +0100
432 @@ -181,6 +181,16 @@
433 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
434 #define SSB_CHIPCO_FLASH_CFG 0x0128
435 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
436 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
437 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
438 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
439 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
440 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
441 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
442 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
443 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
444 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
445 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
446 #define SSB_CHIPCO_UART0_DATA 0x0300
447 #define SSB_CHIPCO_UART0_IMR 0x0304
448 #define SSB_CHIPCO_UART0_FCR 0x0308
449 @@ -197,6 +207,172 @@
450 #define SSB_CHIPCO_UART1_LSR 0x0414
451 #define SSB_CHIPCO_UART1_MSR 0x0418
452 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
453 +/* PMU registers (rev >= 20) */
454 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
455 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
456 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
457 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
458 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
459 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
460 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
461 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
462 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
463 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
464 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
465 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
466 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
467 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
468 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
469 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
470 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
471 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
472 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
473 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
474 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
475 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
476 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
477 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
478 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
479 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
480 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
481 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
482 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
483 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
484 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
485 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
486 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
487 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
488 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
489 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
490 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
491 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
492 +
493 +
494 +
495 +/** PMU PLL registers */
496 +
497 +/* PMU rev 0 PLL registers */
498 +#define SSB_PMU0_PLLCTL0 0
499 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
500 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
501 +#define SSB_PMU0_PLLCTL1 1
502 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
503 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
504 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
505 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
506 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
507 +#define SSB_PMU0_PLLCTL2 2
508 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
509 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
510 +
511 +/* PMU rev 1 PLL registers */
512 +#define SSB_PMU1_PLLCTL0 0
513 +#define SSB_PMU1_PLLCTL1 1
514 +#define SSB_PMU1_PLLCTL2 2
515 +#define SSB_PMU1_PLLCTL3 3
516 +#define SSB_PMU1_PLLCTL4 4
517 +#define SSB_PMU1_PLLCTL5 5
518 +
519 +/* BCM4312 PLL resource numbers. */
520 +#define SSB_PLLRES_4312_SWITCHER_BURST 0
521 +#define SSB_PLLRES_4312_SWITCHER_PWM 1
522 +#define SSB_PLLRES_4312_PA_REF_LDO 2
523 +#define SSB_PLLRES_4312_CORE_LDO_BURST 3
524 +#define SSB_PLLRES_4312_CORE_LDO_PWM 4
525 +#define SSB_PLLRES_4312_RADIO_LDO 5
526 +#define SSB_PLLRES_4312_ILP_REQUEST 6
527 +#define SSB_PLLRES_4312_BG_FILTBYP 7
528 +#define SSB_PLLRES_4312_TX_FILTBYP 8
529 +#define SSB_PLLRES_4312_RX_FILTBYP 9
530 +#define SSB_PLLRES_4312_XTAL_PU 10
531 +#define SSB_PLLRES_4312_ALP_AVAIL 11
532 +#define SSB_PLLRES_4312_BB_PLL_FILTBYP 12
533 +#define SSB_PLLRES_4312_RF_PLL_FILTBYP 13
534 +#define SSB_PLLRES_4312_HT_AVAIL 14
535 +
536 +/* BCM4325 PLL resource numbers. */
537 +#define SSB_PLLRES_4325_BUCK_BOOST_BURST 0
538 +#define SSB_PLLRES_4325_CBUCK_BURST 1
539 +#define SSB_PLLRES_4325_CBUCK_PWM 2
540 +#define SSB_PLLRES_4325_CLDO_CBUCK_BURST 3
541 +#define SSB_PLLRES_4325_CLDO_CBUCK_PWM 4
542 +#define SSB_PLLRES_4325_BUCK_BOOST_PWM 5
543 +#define SSB_PLLRES_4325_ILP_REQUEST 6
544 +#define SSB_PLLRES_4325_ABUCK_BURST 7
545 +#define SSB_PLLRES_4325_ABUCK_PWM 8
546 +#define SSB_PLLRES_4325_LNLDO1_PU 9
547 +#define SSB_PLLRES_4325_LNLDO2_PU 10
548 +#define SSB_PLLRES_4325_LNLDO3_PU 11
549 +#define SSB_PLLRES_4325_LNLDO4_PU 12
550 +#define SSB_PLLRES_4325_XTAL_PU 13
551 +#define SSB_PLLRES_4325_ALP_AVAIL 14
552 +#define SSB_PLLRES_4325_RX_PWRSW_PU 15
553 +#define SSB_PLLRES_4325_TX_PWRSW_PU 16
554 +#define SSB_PLLRES_4325_RFPLL_PWRSW_PU 17
555 +#define SSB_PLLRES_4325_LOGEN_PWRSW_PU 18
556 +#define SSB_PLLRES_4325_AFE_PWRSW_PU 19
557 +#define SSB_PLLRES_4325_BBPLL_PWRSW_PU 20
558 +#define SSB_PLLRES_4325_HT_AVAIL 21
559 +
560 +/* BCM4328 PLL resource numbers. */
561 +#define SSB_PLLRES_4328_EXT_SWITCHER_PWM 0
562 +#define SSB_PLLRES_4328_BB_SWITCHER_PWM 1
563 +#define SSB_PLLRES_4328_BB_SWITCHER_BURST 2
564 +#define SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST 3
565 +#define SSB_PLLRES_4328_ILP_REQUEST 4
566 +#define SSB_PLLRES_4328_RADIO_SWITCHER_PWM 5
567 +#define SSB_PLLRES_4328_RADIO_SWITCHER_BURST 6
568 +#define SSB_PLLRES_4328_ROM_SWITCH 7
569 +#define SSB_PLLRES_4328_PA_REF_LDO 8
570 +#define SSB_PLLRES_4328_RADIO_LDO 9
571 +#define SSB_PLLRES_4328_AFE_LDO 10
572 +#define SSB_PLLRES_4328_PLL_LDO 11
573 +#define SSB_PLLRES_4328_BG_FILTBYP 12
574 +#define SSB_PLLRES_4328_TX_FILTBYP 13
575 +#define SSB_PLLRES_4328_RX_FILTBYP 14
576 +#define SSB_PLLRES_4328_XTAL_PU 15
577 +#define SSB_PLLRES_4328_XTAL_EN 16
578 +#define SSB_PLLRES_4328_BB_PLL_FILTBYP 17
579 +#define SSB_PLLRES_4328_RF_PLL_FILTBYP 18
580 +#define SSB_PLLRES_4328_BB_PLL_PU 19
581 +
582 +/* BCM5354 PLL resource numbers. */
583 +#define SSB_PLLRES_5354_EXT_SWITCHER_PWM 0
584 +#define SSB_PLLRES_5354_BB_SWITCHER_PWM 1
585 +#define SSB_PLLRES_5354_BB_SWITCHER_BURST 2
586 +#define SSB_PLLRES_5354_BB_EXT_SWITCHER_BURST 3
587 +#define SSB_PLLRES_5354_ILP_REQUEST 4
588 +#define SSB_PLLRES_5354_RADIO_SWITCHER_PWM 5
589 +#define SSB_PLLRES_5354_RADIO_SWITCHER_BURST 6
590 +#define SSB_PLLRES_5354_ROM_SWITCH 7
591 +#define SSB_PLLRES_5354_PA_REF_LDO 8
592 +#define SSB_PLLRES_5354_RADIO_LDO 9
593 +#define SSB_PLLRES_5354_AFE_LDO 10
594 +#define SSB_PLLRES_5354_PLL_LDO 11
595 +#define SSB_PLLRES_5354_BG_FILTBYP 12
596 +#define SSB_PLLRES_5354_TX_FILTBYP 13
597 +#define SSB_PLLRES_5354_RX_FILTBYP 14
598 +#define SSB_PLLRES_5354_XTAL_PU 15
599 +#define SSB_PLLRES_5354_XTAL_EN 16
600 +#define SSB_PLLRES_5354_BB_PLL_FILTBYP 17
601 +#define SSB_PLLRES_5354_RF_PLL_FILTBYP 18
602 +#define SSB_PLLRES_5354_BB_PLL_PU 19
603 +
604 +
605 +
606 +/** Chip specific Chip-Status register contents. */
607 +#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
608 +#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
609 +#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
610 +#define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
611 +#define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
612 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
613 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
614 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
615 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3
616 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
617 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
618 +#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
619
620
621
622 @@ -353,11 +529,20 @@
623 struct ssb_device;
624 struct ssb_serial_port;
625
626 +/* Data for the PMU, if available.
627 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
628 + */
629 +struct ssb_chipcommon_pmu {
630 + u8 rev; /* PMU revision */
631 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
632 +};
633 +
634 struct ssb_chipcommon {
635 struct ssb_device *dev;
636 u32 capabilities;
637 /* Fast Powerup Delay constant */
638 u16 fast_pwrup_delay;
639 + struct ssb_chipcommon_pmu pmu;
640 };
641
642 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
643 @@ -365,6 +550,17 @@ static inline bool ssb_chipco_available(
644 return (cc->dev != NULL);
645 }
646
647 +/* Register access */
648 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
649 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
650 +
651 +#define chipco_mask32(cc, offset, mask) \
652 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
653 +#define chipco_set32(cc, offset, set) \
654 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
655 +#define chipco_maskset32(cc, offset, mask, set) \
656 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
657 +
658 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
659
660 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
661 @@ -406,4 +602,8 @@ extern int ssb_chipco_serial_init(struct
662 struct ssb_serial_port *ports);
663 #endif /* CONFIG_SSB_SERIAL */
664
665 +/* PMU support */
666 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
667 +
668 +
669 #endif /* LINUX_SSB_CHIPCO_H_ */
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