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bcm47xx: Implement the remaining parts of PMU init.
[openwrt/staging/wigyori.git] / target / linux / brcm47xx / patches-2.6.28 / 810-ssb-add-pmu-support.patch
1 Sent to mainline on 2009 Feb 03.
2
3 For further modifications, please use separate patch files. This simpifies
4 keeping track of what is upstream and what is not. Thanks.
5
6 --mb
7
8
9 Index: linux-2.6.28.2/drivers/ssb/Makefile
10 ===================================================================
11 --- linux-2.6.28.2.orig/drivers/ssb/Makefile 2009-02-01 13:09:04.000000000 +0100
12 +++ linux-2.6.28.2/drivers/ssb/Makefile 2009-02-01 13:09:31.000000000 +0100
13 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
14
15 # built-in drivers
16 ssb-y += driver_chipcommon.o
17 +ssb-y += driver_chipcommon_pmu.o
18 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
19 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
20 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
21 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
22 ===================================================================
23 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
24 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-03 19:07:23.000000000 +0100
25 @@ -0,0 +1,508 @@
26 +/*
27 + * Sonics Silicon Backplane
28 + * Broadcom ChipCommon Power Management Unit driver
29 + *
30 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
31 + * Copyright 2007, Broadcom Corporation
32 + *
33 + * Licensed under the GNU/GPL. See COPYING for details.
34 + */
35 +
36 +#include <linux/ssb/ssb.h>
37 +#include <linux/ssb/ssb_regs.h>
38 +#include <linux/ssb/ssb_driver_chipcommon.h>
39 +#include <linux/delay.h>
40 +
41 +#include "ssb_private.h"
42 +
43 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
44 +{
45 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
46 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
47 +}
48 +
49 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
50 + u32 offset, u32 value)
51 +{
52 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
53 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
54 +}
55 +
56 +struct pmu0_plltab_entry {
57 + u16 freq; /* Crystal frequency in kHz.*/
58 + u8 xf; /* Crystal frequency value for PMU control */
59 + u8 wb_int;
60 + u32 wb_frac;
61 +};
62 +
63 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
64 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
65 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
66 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
67 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
68 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
69 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
70 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
71 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
72 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
73 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
74 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
75 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
76 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
77 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
78 +};
79 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
80 +
81 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
82 +{
83 + const struct pmu0_plltab_entry *e;
84 + unsigned int i;
85 +
86 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
87 + e = &pmu0_plltab[i];
88 + if (e->freq == crystalfreq)
89 + return e;
90 + }
91 +
92 + return NULL;
93 +}
94 +
95 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
96 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
97 + u32 crystalfreq)
98 +{
99 + struct ssb_bus *bus = cc->dev->bus;
100 + const struct pmu0_plltab_entry *e = NULL;
101 + u32 pmuctl, tmp, pllctl;
102 + unsigned int i;
103 +
104 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
105 + /* The 5354 crystal freq is 25MHz */
106 + crystalfreq = 25000;
107 + }
108 + if (crystalfreq)
109 + e = pmu0_plltab_find_entry(crystalfreq);
110 + if (!e)
111 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
112 + BUG_ON(!e);
113 + crystalfreq = e->freq;
114 + cc->pmu.crystalfreq = e->freq;
115 +
116 + /* Check if the PLL already is programmed to this frequency. */
117 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
118 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
119 + /* We're already there... */
120 + return;
121 + }
122 +
123 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
124 + (crystalfreq / 1000), (crystalfreq % 1000));
125 +
126 + /* First turn the PLL off. */
127 + switch (bus->chip_id) {
128 + case 0x4328:
129 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
130 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
131 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
132 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
133 + break;
134 + case 0x5354:
135 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
136 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
137 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
138 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
139 + break;
140 + default:
141 + SSB_WARN_ON(1);
142 + }
143 + for (i = 1500; i; i--) {
144 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
145 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
146 + break;
147 + udelay(10);
148 + }
149 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
150 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
151 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
152 +
153 + /* Set PDIV in PLL control 0. */
154 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
155 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
156 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
157 + else
158 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
159 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
160 +
161 + /* Set WILD in PLL control 1. */
162 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
163 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
164 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
165 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
166 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
167 + if (e->wb_frac == 0)
168 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
169 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
170 +
171 + /* Set WILD in PLL control 2. */
172 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
173 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
174 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
175 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
176 +
177 + /* Set the crystalfrequency and the divisor. */
178 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
179 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
180 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
181 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
182 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
183 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
184 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
185 +}
186 +
187 +struct pmu1_plltab_entry {
188 + u16 freq; /* Crystal frequency in kHz.*/
189 + u8 xf; /* Crystal frequency value for PMU control */
190 + u8 ndiv_int;
191 + u32 ndiv_frac;
192 + u8 p1div;
193 + u8 p2div;
194 +};
195 +
196 +static const struct pmu1_plltab_entry pmu1_plltab[] = {
197 + { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
198 + { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
199 + { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
200 + { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
201 + { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
202 + { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
203 + { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
204 + { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
205 + { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
206 + { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
207 + { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
208 + { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
209 + { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
210 + { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
211 + { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
212 +};
213 +
214 +#define SSB_PMU1_DEFAULT_XTALFREQ 15360
215 +
216 +static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
217 +{
218 + const struct pmu1_plltab_entry *e;
219 + unsigned int i;
220 +
221 + for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
222 + e = &pmu1_plltab[i];
223 + if (e->freq == crystalfreq)
224 + return e;
225 + }
226 +
227 + return NULL;
228 +}
229 +
230 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
231 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
232 + u32 crystalfreq)
233 +{
234 + struct ssb_bus *bus = cc->dev->bus;
235 + const struct pmu1_plltab_entry *e = NULL;
236 + u32 buffer_strength = 0;
237 + u32 tmp, pllctl, pmuctl;
238 + unsigned int i;
239 +
240 + if (bus->chip_id == 0x4312) {
241 + /* We do not touch the BCM4312 PLL and assume
242 + * the default crystal settings work out-of-the-box. */
243 + cc->pmu.crystalfreq = 20000;
244 + return;
245 + }
246 +
247 + if (crystalfreq)
248 + e = pmu1_plltab_find_entry(crystalfreq);
249 + if (!e)
250 + e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
251 + BUG_ON(!e);
252 + crystalfreq = e->freq;
253 + cc->pmu.crystalfreq = e->freq;
254 +
255 + /* Check if the PLL already is programmed to this frequency. */
256 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
257 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
258 + /* We're already there... */
259 + return;
260 + }
261 +
262 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
263 + (crystalfreq / 1000), (crystalfreq % 1000));
264 +
265 + /* First turn the PLL off. */
266 + switch (bus->chip_id) {
267 + case 0x4325:
268 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
269 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
270 + (1 << SSB_PMURES_4325_HT_AVAIL)));
271 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
272 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
273 + (1 << SSB_PMURES_4325_HT_AVAIL)));
274 + /* Adjust the BBPLL to 2 on all channels later. */
275 + buffer_strength = 0x222222;
276 + break;
277 + default:
278 + SSB_WARN_ON(1);
279 + }
280 + for (i = 1500; i; i--) {
281 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
282 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
283 + break;
284 + udelay(10);
285 + }
286 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
287 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
288 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
289 +
290 + /* Set p1div and p2div. */
291 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
292 + pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
293 + pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
294 + pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
295 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
296 +
297 + /* Set ndiv int and ndiv mode */
298 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
299 + pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
300 + pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
301 + pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
302 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
303 +
304 + /* Set ndiv frac */
305 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
306 + pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
307 + pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
308 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
309 +
310 + /* Change the drive strength, if required. */
311 + if (buffer_strength) {
312 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
313 + pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
314 + pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
315 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
316 + }
317 +
318 + /* Tune the crystalfreq and the divisor. */
319 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
320 + pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
321 + pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
322 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
323 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
324 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
325 +}
326 +
327 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
328 +{
329 + struct ssb_bus *bus = cc->dev->bus;
330 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
331 +
332 + if (bus->bustype == SSB_BUSTYPE_SSB) {
333 + /* TODO: The user may override the crystal frequency. */
334 + }
335 +
336 + switch (bus->chip_id) {
337 + case 0x4312:
338 + case 0x4325:
339 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
340 + break;
341 + case 0x4328:
342 + case 0x5354:
343 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
344 + break;
345 + default:
346 + ssb_printk(KERN_ERR PFX
347 + "ERROR: PLL init unknown for device %04X\n",
348 + bus->chip_id);
349 + }
350 +}
351 +
352 +struct pmu_res_updown_tab_entry {
353 + u8 resource; /* The resource number */
354 + u16 updown; /* The updown value */
355 +};
356 +
357 +enum pmu_res_depend_tab_task {
358 + PMU_RES_DEP_SET = 1,
359 + PMU_RES_DEP_ADD,
360 + PMU_RES_DEP_REMOVE,
361 +};
362 +
363 +struct pmu_res_depend_tab_entry {
364 + u8 resource; /* The resource number */
365 + u8 task; /* SET | ADD | REMOVE */
366 + u32 depend; /* The depend mask */
367 +};
368 +
369 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
370 + { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
371 + { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
372 + { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
373 + { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
374 + { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, },
375 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
376 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
377 + { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, },
378 + { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, },
379 + { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, },
380 + { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, },
381 + { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, },
382 + { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, },
383 + { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, },
384 + { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, },
385 + { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, },
386 + { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, },
387 + { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
388 + { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
389 + { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, },
390 +};
391 +
392 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
393 + {
394 + /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
395 + .resource = SSB_PMURES_4328_ILP_REQUEST,
396 + .task = PMU_RES_DEP_SET,
397 + .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
398 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
399 + },
400 +};
401 +
402 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
403 + { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, },
404 +};
405 +
406 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
407 + {
408 + /* Adjust HT-Available dependencies. */
409 + .resource = SSB_PMURES_4325_HT_AVAIL,
410 + .task = PMU_RES_DEP_ADD,
411 + .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
412 + (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
413 + (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
414 + (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
415 + },
416 +};
417 +
418 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
419 +{
420 + struct ssb_bus *bus = cc->dev->bus;
421 + u32 min_msk = 0, max_msk = 0;
422 + unsigned int i;
423 + const struct pmu_res_updown_tab_entry *updown_tab = NULL;
424 + unsigned int updown_tab_size;
425 + const struct pmu_res_depend_tab_entry *depend_tab = NULL;
426 + unsigned int depend_tab_size;
427 +
428 + switch (bus->chip_id) {
429 + case 0x4312:
430 + /* We keep the default settings:
431 + * min_msk = 0xCBB
432 + * max_msk = 0x7FFFF
433 + */
434 + break;
435 + case 0x4325:
436 + /* Power OTP down later. */
437 + min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
438 + (1 << SSB_PMURES_4325_LNLDO2_PU);
439 + if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
440 + SSB_CHIPCO_CHST_4325_PMUTOP_2B)
441 + min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
442 + /* The PLL may turn on, if it decides so. */
443 + max_msk = 0xFFFFF;
444 + updown_tab = pmu_res_updown_tab_4325a0;
445 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
446 + depend_tab = pmu_res_depend_tab_4325a0;
447 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
448 + break;
449 + case 0x4328:
450 + min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
451 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
452 + (1 << SSB_PMURES_4328_XTAL_EN);
453 + /* The PLL may turn on, if it decides so. */
454 + max_msk = 0xFFFFF;
455 + updown_tab = pmu_res_updown_tab_4328a0;
456 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
457 + depend_tab = pmu_res_depend_tab_4328a0;
458 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
459 + break;
460 + case 0x5354:
461 + /* The PLL may turn on, if it decides so. */
462 + max_msk = 0xFFFFF;
463 + break;
464 + default:
465 + ssb_printk(KERN_ERR PFX
466 + "ERROR: PMU resource config unknown for device %04X\n",
467 + bus->chip_id);
468 + }
469 +
470 + if (updown_tab) {
471 + for (i = 0; i < updown_tab_size; i++) {
472 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
473 + updown_tab[i].resource);
474 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
475 + updown_tab[i].updown);
476 + }
477 + }
478 + if (depend_tab) {
479 + for (i = 0; i < depend_tab_size; i++) {
480 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
481 + depend_tab[i].resource);
482 + switch (depend_tab[i].task) {
483 + case PMU_RES_DEP_SET:
484 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
485 + depend_tab[i].depend);
486 + break;
487 + case PMU_RES_DEP_ADD:
488 + chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
489 + depend_tab[i].depend);
490 + break;
491 + case PMU_RES_DEP_REMOVE:
492 + chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
493 + ~(depend_tab[i].depend));
494 + break;
495 + default:
496 + SSB_WARN_ON(1);
497 + }
498 + }
499 + }
500 +
501 + /* Set the resource masks. */
502 + if (min_msk)
503 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
504 + if (max_msk)
505 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
506 +}
507 +
508 +void ssb_pmu_init(struct ssb_chipcommon *cc)
509 +{
510 + struct ssb_bus *bus = cc->dev->bus;
511 + u32 pmucap;
512 +
513 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
514 + return;
515 +
516 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
517 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
518 +
519 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
520 + cc->pmu.rev, pmucap);
521 +
522 + if (cc->pmu.rev >= 1) {
523 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
524 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
525 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
526 + } else {
527 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
528 + SSB_CHIPCO_PMU_CTL_NOILPONW);
529 + }
530 + }
531 + ssb_pmu_pll_init(cc);
532 + ssb_pmu_resources_init(cc);
533 +}
534 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
535 ===================================================================
536 --- linux-2.6.28.2.orig/drivers/ssb/driver_chipcommon.c 2009-02-01 13:07:03.000000000 +0100
537 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon.c 2009-02-01 13:47:17.000000000 +0100
538 @@ -26,19 +26,6 @@ enum ssb_clksrc {
539 };
540
541
542 -static inline u32 chipco_read32(struct ssb_chipcommon *cc,
543 - u16 offset)
544 -{
545 - return ssb_read32(cc->dev, offset);
546 -}
547 -
548 -static inline void chipco_write32(struct ssb_chipcommon *cc,
549 - u16 offset,
550 - u32 value)
551 -{
552 - ssb_write32(cc->dev, offset, value);
553 -}
554 -
555 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
556 u32 mask, u32 value)
557 {
558 @@ -246,6 +233,7 @@ void ssb_chipcommon_init(struct ssb_chip
559 {
560 if (!cc->dev)
561 return; /* We don't have a ChipCommon */
562 + ssb_pmu_init(cc);
563 chipco_powercontrol_init(cc);
564 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
565 calc_fast_powerup_delay(cc);
566 Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
567 ===================================================================
568 --- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 13:22:59.000000000 +0100
569 +++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-03 18:43:33.000000000 +0100
570 @@ -181,6 +181,16 @@
571 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
572 #define SSB_CHIPCO_FLASH_CFG 0x0128
573 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
574 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
575 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
576 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
577 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
578 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
579 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
580 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
581 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
582 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
583 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
584 #define SSB_CHIPCO_UART0_DATA 0x0300
585 #define SSB_CHIPCO_UART0_IMR 0x0304
586 #define SSB_CHIPCO_UART0_FCR 0x0308
587 @@ -197,6 +207,196 @@
588 #define SSB_CHIPCO_UART1_LSR 0x0414
589 #define SSB_CHIPCO_UART1_MSR 0x0418
590 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
591 +/* PMU registers (rev >= 20) */
592 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
593 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
594 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
595 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
596 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
597 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
598 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
599 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
600 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
601 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
602 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
603 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
604 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
605 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
606 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
607 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
608 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
609 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
610 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
611 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
612 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
613 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
614 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
615 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
616 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
617 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
618 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
619 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
620 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
621 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
622 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
623 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
624 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
625 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
626 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
627 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
628 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
629 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
630 +
631 +
632 +
633 +/** PMU PLL registers */
634 +
635 +/* PMU rev 0 PLL registers */
636 +#define SSB_PMU0_PLLCTL0 0
637 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
638 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
639 +#define SSB_PMU0_PLLCTL1 1
640 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
641 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
642 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
643 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
644 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
645 +#define SSB_PMU0_PLLCTL2 2
646 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
647 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
648 +
649 +/* PMU rev 1 PLL registers */
650 +#define SSB_PMU1_PLLCTL0 0
651 +#define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */
652 +#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20
653 +#define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */
654 +#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24
655 +#define SSB_PMU1_PLLCTL1 1
656 +#define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
657 +#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0
658 +#define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */
659 +#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8
660 +#define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */
661 +#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16
662 +#define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */
663 +#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24
664 +#define SSB_PMU1_PLLCTL2 2
665 +#define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */
666 +#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0
667 +#define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */
668 +#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8
669 +#define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
670 +#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17
671 +#define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */
672 +#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20
673 +#define SSB_PMU1_PLLCTL3 3
674 +#define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */
675 +#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0
676 +#define SSB_PMU1_PLLCTL4 4
677 +#define SSB_PMU1_PLLCTL5 5
678 +#define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
679 +#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8
680 +
681 +/* BCM4312 PLL resource numbers. */
682 +#define SSB_PMURES_4312_SWITCHER_BURST 0
683 +#define SSB_PMURES_4312_SWITCHER_PWM 1
684 +#define SSB_PMURES_4312_PA_REF_LDO 2
685 +#define SSB_PMURES_4312_CORE_LDO_BURST 3
686 +#define SSB_PMURES_4312_CORE_LDO_PWM 4
687 +#define SSB_PMURES_4312_RADIO_LDO 5
688 +#define SSB_PMURES_4312_ILP_REQUEST 6
689 +#define SSB_PMURES_4312_BG_FILTBYP 7
690 +#define SSB_PMURES_4312_TX_FILTBYP 8
691 +#define SSB_PMURES_4312_RX_FILTBYP 9
692 +#define SSB_PMURES_4312_XTAL_PU 10
693 +#define SSB_PMURES_4312_ALP_AVAIL 11
694 +#define SSB_PMURES_4312_BB_PLL_FILTBYP 12
695 +#define SSB_PMURES_4312_RF_PLL_FILTBYP 13
696 +#define SSB_PMURES_4312_HT_AVAIL 14
697 +
698 +/* BCM4325 PLL resource numbers. */
699 +#define SSB_PMURES_4325_BUCK_BOOST_BURST 0
700 +#define SSB_PMURES_4325_CBUCK_BURST 1
701 +#define SSB_PMURES_4325_CBUCK_PWM 2
702 +#define SSB_PMURES_4325_CLDO_CBUCK_BURST 3
703 +#define SSB_PMURES_4325_CLDO_CBUCK_PWM 4
704 +#define SSB_PMURES_4325_BUCK_BOOST_PWM 5
705 +#define SSB_PMURES_4325_ILP_REQUEST 6
706 +#define SSB_PMURES_4325_ABUCK_BURST 7
707 +#define SSB_PMURES_4325_ABUCK_PWM 8
708 +#define SSB_PMURES_4325_LNLDO1_PU 9
709 +#define SSB_PMURES_4325_LNLDO2_PU 10
710 +#define SSB_PMURES_4325_LNLDO3_PU 11
711 +#define SSB_PMURES_4325_LNLDO4_PU 12
712 +#define SSB_PMURES_4325_XTAL_PU 13
713 +#define SSB_PMURES_4325_ALP_AVAIL 14
714 +#define SSB_PMURES_4325_RX_PWRSW_PU 15
715 +#define SSB_PMURES_4325_TX_PWRSW_PU 16
716 +#define SSB_PMURES_4325_RFPLL_PWRSW_PU 17
717 +#define SSB_PMURES_4325_LOGEN_PWRSW_PU 18
718 +#define SSB_PMURES_4325_AFE_PWRSW_PU 19
719 +#define SSB_PMURES_4325_BBPLL_PWRSW_PU 20
720 +#define SSB_PMURES_4325_HT_AVAIL 21
721 +
722 +/* BCM4328 PLL resource numbers. */
723 +#define SSB_PMURES_4328_EXT_SWITCHER_PWM 0
724 +#define SSB_PMURES_4328_BB_SWITCHER_PWM 1
725 +#define SSB_PMURES_4328_BB_SWITCHER_BURST 2
726 +#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3
727 +#define SSB_PMURES_4328_ILP_REQUEST 4
728 +#define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5
729 +#define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6
730 +#define SSB_PMURES_4328_ROM_SWITCH 7
731 +#define SSB_PMURES_4328_PA_REF_LDO 8
732 +#define SSB_PMURES_4328_RADIO_LDO 9
733 +#define SSB_PMURES_4328_AFE_LDO 10
734 +#define SSB_PMURES_4328_PLL_LDO 11
735 +#define SSB_PMURES_4328_BG_FILTBYP 12
736 +#define SSB_PMURES_4328_TX_FILTBYP 13
737 +#define SSB_PMURES_4328_RX_FILTBYP 14
738 +#define SSB_PMURES_4328_XTAL_PU 15
739 +#define SSB_PMURES_4328_XTAL_EN 16
740 +#define SSB_PMURES_4328_BB_PLL_FILTBYP 17
741 +#define SSB_PMURES_4328_RF_PLL_FILTBYP 18
742 +#define SSB_PMURES_4328_BB_PLL_PU 19
743 +
744 +/* BCM5354 PLL resource numbers. */
745 +#define SSB_PMURES_5354_EXT_SWITCHER_PWM 0
746 +#define SSB_PMURES_5354_BB_SWITCHER_PWM 1
747 +#define SSB_PMURES_5354_BB_SWITCHER_BURST 2
748 +#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3
749 +#define SSB_PMURES_5354_ILP_REQUEST 4
750 +#define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5
751 +#define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6
752 +#define SSB_PMURES_5354_ROM_SWITCH 7
753 +#define SSB_PMURES_5354_PA_REF_LDO 8
754 +#define SSB_PMURES_5354_RADIO_LDO 9
755 +#define SSB_PMURES_5354_AFE_LDO 10
756 +#define SSB_PMURES_5354_PLL_LDO 11
757 +#define SSB_PMURES_5354_BG_FILTBYP 12
758 +#define SSB_PMURES_5354_TX_FILTBYP 13
759 +#define SSB_PMURES_5354_RX_FILTBYP 14
760 +#define SSB_PMURES_5354_XTAL_PU 15
761 +#define SSB_PMURES_5354_XTAL_EN 16
762 +#define SSB_PMURES_5354_BB_PLL_FILTBYP 17
763 +#define SSB_PMURES_5354_RF_PLL_FILTBYP 18
764 +#define SSB_PMURES_5354_BB_PLL_PU 19
765 +
766 +
767 +
768 +/** Chip specific Chip-Status register contents. */
769 +#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
770 +#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
771 +#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
772 +#define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
773 +#define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
774 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
775 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
776 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
777 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3
778 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
779 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
780 +#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
781
782
783
784 @@ -353,11 +553,20 @@
785 struct ssb_device;
786 struct ssb_serial_port;
787
788 +/* Data for the PMU, if available.
789 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
790 + */
791 +struct ssb_chipcommon_pmu {
792 + u8 rev; /* PMU revision */
793 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
794 +};
795 +
796 struct ssb_chipcommon {
797 struct ssb_device *dev;
798 u32 capabilities;
799 /* Fast Powerup Delay constant */
800 u16 fast_pwrup_delay;
801 + struct ssb_chipcommon_pmu pmu;
802 };
803
804 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
805 @@ -365,6 +574,17 @@ static inline bool ssb_chipco_available(
806 return (cc->dev != NULL);
807 }
808
809 +/* Register access */
810 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
811 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
812 +
813 +#define chipco_mask32(cc, offset, mask) \
814 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
815 +#define chipco_set32(cc, offset, set) \
816 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
817 +#define chipco_maskset32(cc, offset, mask, set) \
818 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
819 +
820 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
821
822 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
823 @@ -406,4 +626,8 @@ extern int ssb_chipco_serial_init(struct
824 struct ssb_serial_port *ports);
825 #endif /* CONFIG_SSB_SERIAL */
826
827 +/* PMU support */
828 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
829 +
830 +
831 #endif /* LINUX_SSB_CHIPCO_H_ */
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