1 commit 0388a0410d590a6c239c1cfaa7d49bffd4ed1101
2 Author: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Wed Sep 18 13:32:59 2013 +0200
5 MIPS: BCM47XX: Fix clock detection for BCM5354 with 200MHz clock
7 Some BCM5354 SoCs are running at 200MHz, but it is not possible to read
8 the clock from a register like it is done on some other SoC in ssb and
9 bcma. These devices should have a clkfreq nvram configuration value set
10 to 200, read it and set the clock to the correct value.
12 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
13 Cc: linux-mips@linux-mips.org
14 Patchwork: https://patchwork.linux-mips.org/patch/5842/
15 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
17 --- a/arch/mips/bcm47xx/time.c
18 +++ b/arch/mips/bcm47xx/time.c
20 #include <linux/ssb/ssb.h>
23 +#include <bcm47xx_nvram.h>
25 void __init plat_time_init(void)
33 * Use deterministic values for initial counter interrupt
34 @@ -43,15 +47,23 @@ void __init plat_time_init(void)
35 #ifdef CONFIG_BCM47XX_SSB
36 case BCM47XX_BUS_TYPE_SSB:
37 hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
38 + chip_id = bcm47xx_bus.ssb.chip_id;
41 #ifdef CONFIG_BCM47XX_BCMA
42 case BCM47XX_BUS_TYPE_BCMA:
43 hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
44 + chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
49 + if (chip_id == 0x5354) {
50 + len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
51 + if (len >= 0 && !strncmp(buf, "200", 4))