1 --- a/drivers/net/ethernet/broadcom/tg3.c
2 +++ b/drivers/net/ethernet/broadcom/tg3.c
4 #include <linux/prefetch.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/firmware.h>
7 +#include <linux/ssb/ssb_driver_gige.h>
9 #include <net/checksum.h>
11 @@ -249,6 +250,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
12 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
13 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
14 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
15 + {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
16 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
17 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
18 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
19 @@ -530,7 +532,9 @@ static void _tw32_flush(struct tg3 *tp,
20 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
22 tp->write32_mbox(tp, off, val);
23 - if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
24 + if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
25 + (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
26 + !tg3_flag(tp, ICH_WORKAROUND)))
27 tp->read32_mbox(tp, off);
30 @@ -540,7 +544,8 @@ static void tg3_write32_tx_mbox(struct t
32 if (tg3_flag(tp, TXD_MBOX_HWBUG))
34 - if (tg3_flag(tp, MBOX_WRITE_REORDER))
35 + if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
36 + tg3_flag(tp, FLUSH_POSTED_WRITES))
40 @@ -948,7 +953,8 @@ static void tg3_switch_clocks(struct tg3
42 #define PHY_BUSY_LOOPS 5000
44 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
45 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
50 @@ -962,7 +968,7 @@ static int tg3_readphy(struct tg3 *tp, i
54 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
55 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
56 MI_COM_PHY_ADDR_MASK);
57 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
58 MI_COM_REG_ADDR_MASK);
59 @@ -997,7 +1003,13 @@ static int tg3_readphy(struct tg3 *tp, i
63 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
64 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
66 + return __tg3_readphy(tp, tp->phy_addr, reg, val);
69 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
74 @@ -1013,7 +1025,7 @@ static int tg3_writephy(struct tg3 *tp,
78 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
79 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
80 MI_COM_PHY_ADDR_MASK);
81 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
82 MI_COM_REG_ADDR_MASK);
83 @@ -1046,6 +1058,11 @@ static int tg3_writephy(struct tg3 *tp,
87 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
89 + return __tg3_writephy(tp, tp->phy_addr, reg, val);
92 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
95 @@ -1608,6 +1625,11 @@ static int tg3_poll_fw(struct tg3 *tp)
99 + if (tg3_flag(tp, IS_SSB_CORE)) {
100 + /* We don't use firmware. */
104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
105 /* Wait up to 20ms for init done. */
106 for (i = 0; i < 200; i++) {
107 @@ -3015,6 +3037,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
108 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
111 + /* There is only an Rx CPU for the 5750 derivative in the
113 + if (tg3_flag(tp, IS_SSB_CORE))
116 for (i = 0; i < 10000; i++) {
117 tw32(offset + CPU_STATE, 0xffffffff);
118 tw32(offset + CPU_MODE, CPU_MODE_HALT);
119 @@ -3029,9 +3056,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
123 - /* Clear firmware's nvram arbitration. */
124 - if (tg3_flag(tp, NVRAM))
125 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
126 + if (!tg3_flag(tp, IS_SSB_CORE)) {
127 + /* Clear firmware's nvram arbitration. */
128 + if (tg3_flag(tp, NVRAM))
129 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
135 @@ -3094,6 +3124,11 @@ static int tg3_load_5701_a0_firmware_fix
136 const __be32 *fw_data;
139 + if (tg3_flag(tp, IS_SSB_CORE)) {
140 + /* We don't use firmware. */
144 fw_data = (void *)tp->fw->data;
146 /* Firmware blob starts with version numbers, followed by
147 @@ -3150,6 +3185,11 @@ static int tg3_load_tso_firmware(struct
148 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
151 + if (tg3_flag(tp, IS_SSB_CORE)) {
152 + /* We don't use firmware. */
156 if (tg3_flag(tp, HW_TSO_1) ||
157 tg3_flag(tp, HW_TSO_2) ||
158 tg3_flag(tp, HW_TSO_3))
159 @@ -3496,8 +3536,9 @@ static int tg3_power_down_prepare(struct
160 tg3_frob_aux_power(tp, true);
162 /* Workaround for unstable PLL clock */
163 - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
164 - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
165 + if ((!tg3_flag(tp, IS_SSB_CORE)) &&
166 + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
167 + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
168 u32 val = tr32(0x7d00);
170 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
171 @@ -4011,6 +4052,14 @@ relink:
172 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
173 tg3_phy_copper_begin(tp);
175 + if (tg3_flag(tp, ROBOSWITCH)) {
176 + current_link_up = 1;
177 + current_speed = SPEED_1000; /* FIXME */
178 + current_duplex = DUPLEX_FULL;
179 + tp->link_config.active_speed = current_speed;
180 + tp->link_config.active_duplex = current_duplex;
183 tg3_readphy(tp, MII_BMSR, &bmsr);
184 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
185 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
186 @@ -4029,6 +4078,26 @@ relink:
188 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
190 + /* In order for the 5750 core in BCM4785 chip to work properly
191 + * in RGMII mode, the Led Control Register must be set up.
193 + if (tg3_flag(tp, RGMII_MODE)) {
194 + u32 led_ctrl = tr32(MAC_LED_CTRL);
195 + led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
197 + if (tp->link_config.active_speed == SPEED_10)
198 + led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
199 + else if (tp->link_config.active_speed == SPEED_100)
200 + led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
201 + LED_CTRL_100MBPS_ON);
202 + else if (tp->link_config.active_speed == SPEED_1000)
203 + led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
204 + LED_CTRL_1000MBPS_ON);
206 + tw32(MAC_LED_CTRL, led_ctrl);
210 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
211 if (tp->link_config.active_duplex == DUPLEX_HALF)
212 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
213 @@ -7833,6 +7902,14 @@ static int tg3_chip_reset(struct tg3 *tp
217 + if (tg3_flag(tp, IS_SSB_CORE)) {
218 + /* BCM4785: In order to avoid repercussions from using
219 + * potentially defective internal ROM, stop the Rx RISC CPU,
220 + * which is not required. */
222 + tg3_halt_cpu(tp, RX_CPU_BASE);
225 tw32(GRC_MODE, tp->grc_mode);
227 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
228 @@ -9247,6 +9324,11 @@ static void tg3_timer(unsigned long __op
229 tg3_flag(tp, 57765_CLASS))
230 tg3_chk_missed_msi(tp);
232 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
233 + /* BCM4785: Flush posted writes from GbE to host memory. */
237 if (!tg3_flag(tp, TAGGED_STATUS)) {
238 /* All of this garbage is because when using non-tagged
239 * IRQ status the mailbox/status_block protocol the chip
240 @@ -10959,6 +11041,11 @@ static int tg3_test_nvram(struct tg3 *tp
241 if (tg3_flag(tp, NO_NVRAM))
244 + if (tg3_flag(tp, IS_SSB_CORE)) {
245 + /* We don't have NVRAM. */
249 if (tg3_nvram_read(tp, 0, &magic) != 0)
252 @@ -11916,11 +12003,12 @@ static int tg3_ioctl(struct net_device *
253 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
254 break; /* We have no PHY */
256 - if (!netif_running(dev))
257 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
260 spin_lock_bh(&tp->lock);
261 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
262 + err = __tg3_readphy(tp, data->phy_id & 0x1f,
263 + data->reg_num & 0x1f, &mii_regval);
264 spin_unlock_bh(&tp->lock);
266 data->val_out = mii_regval;
267 @@ -11932,11 +12020,12 @@ static int tg3_ioctl(struct net_device *
268 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
269 break; /* We have no PHY */
271 - if (!netif_running(dev))
272 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
275 spin_lock_bh(&tp->lock);
276 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
277 + err = __tg3_writephy(tp, data->phy_id & 0x1f,
278 + data->reg_num & 0x1f, data->val_in);
279 spin_unlock_bh(&tp->lock);
282 @@ -12670,6 +12759,13 @@ static void __devinit tg3_get_5720_nvram
283 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
284 static void __devinit tg3_nvram_init(struct tg3 *tp)
286 + if (tg3_flag(tp, IS_SSB_CORE)) {
287 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
288 + tg3_flag_clear(tp, NVRAM);
289 + tg3_flag_clear(tp, NVRAM_BUFFERED);
293 tw32_f(GRC_EEPROM_ADDR,
294 (EEPROM_ADDR_FSM_RESET |
295 (EEPROM_DEFAULT_CLOCK_PERIOD <<
296 @@ -12936,6 +13032,9 @@ static int tg3_nvram_write_block(struct
300 + if (tg3_flag(tp, IS_SSB_CORE))
303 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
304 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
305 ~GRC_LCLCTRL_GPIO_OUTPUT1);
306 @@ -13394,10 +13493,19 @@ static int __devinit tg3_phy_probe(struc
307 * subsys device table.
309 p = tg3_lookup_by_subsys(tp);
312 + tp->phy_id = p->phy_id;
313 + } else if (!tg3_flag(tp, IS_SSB_CORE)) {
314 + /* For now we saw the IDs 0xbc050cd0,
315 + * 0xbc050f80 and 0xbc050c30 on devices
316 + * connected to an BCM4785 and there are
317 + * probably more. Just assume that the phy is
318 + * supported when it is connected to a SSB core
324 - tp->phy_id = p->phy_id;
326 tp->phy_id == TG3_PHY_ID_BCM8002)
327 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
328 @@ -14382,6 +14490,11 @@ static int __devinit tg3_get_invariants(
332 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
333 + tp->write32_tx_mbox = tg3_write_flush_reg32;
334 + tp->write32_rx_mbox = tg3_write_flush_reg32;
337 /* Get eeprom hw config before calling tg3_set_power_state().
338 * In particular, the TG3_FLAG_IS_NIC flag must be
339 * determined before calling tg3_set_power_state() so that
340 @@ -14798,6 +14911,10 @@ static int __devinit tg3_get_device_addr
343 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
344 + if (tg3_flag(tp, IS_SSB_CORE))
345 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
347 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
349 if (!tg3_get_default_macaddr_sparc(tp))
351 @@ -15082,7 +15199,8 @@ static int __devinit tg3_test_dma(struct
352 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
354 tp->dma_rwctrl |= 0x8000;
355 - else if (ccval == 0x6 || ccval == 0x7)
356 + else if ((ccval == 0x6 || ccval == 0x7) ||
357 + tg3_flag(tp, ONE_DMA_AT_ONCE))
358 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
361 @@ -15506,6 +15624,17 @@ static int __devinit tg3_init_one(struct
362 tp->msg_enable = tg3_debug;
364 tp->msg_enable = TG3_DEF_MSG_ENABLE;
365 + if (pdev_is_ssb_gige_core(pdev)) {
366 + tg3_flag_set(tp, IS_SSB_CORE);
367 + if (ssb_gige_must_flush_posted_writes(pdev))
368 + tg3_flag_set(tp, FLUSH_POSTED_WRITES);
369 + if (ssb_gige_one_dma_at_once(pdev))
370 + tg3_flag_set(tp, ONE_DMA_AT_ONCE);
371 + if (ssb_gige_have_roboswitch(pdev))
372 + tg3_flag_set(tp, ROBOSWITCH);
373 + if (ssb_gige_is_rgmii(pdev))
374 + tg3_flag_set(tp, RGMII_MODE);
377 /* The word/byte swap controls here control register access byte
378 * swapping. DMA data byte swapping is controlled in the GRC_MODE
379 --- a/drivers/net/ethernet/broadcom/tg3.h
380 +++ b/drivers/net/ethernet/broadcom/tg3.h
381 @@ -2940,6 +2940,11 @@ enum TG3_FLAGS {
383 TG3_FLAG_57765_CLASS,
385 + TG3_FLAG_IS_SSB_CORE,
386 + TG3_FLAG_FLUSH_POSTED_WRITES,
387 + TG3_FLAG_ROBOSWITCH,
388 + TG3_FLAG_ONE_DMA_AT_ONCE,
389 + TG3_FLAG_RGMII_MODE,
391 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
392 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
393 --- a/include/linux/pci_ids.h
394 +++ b/include/linux/pci_ids.h
395 @@ -2120,6 +2120,7 @@
396 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
397 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
398 #define PCI_DEVICE_ID_TIGON3_5756 0x1674
399 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676
400 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
401 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
402 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
403 --- a/include/linux/ssb/ssb_driver_gige.h
404 +++ b/include/linux/ssb/ssb_driver_gige.h
405 @@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p
409 -#ifdef CONFIG_BCM47XX
410 -#include <asm/mach-bcm47xx/nvram.h>
411 -/* Get the device MAC address */
412 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
415 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
417 - nvram_parse_macaddr(buf, macaddr);
420 static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
422 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
424 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
428 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
429 struct pci_dev *pdev);
430 @@ -175,6 +166,9 @@ static inline bool ssb_gige_must_flush_p
434 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
438 #endif /* CONFIG_SSB_DRIVER_GIGE */
439 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */