target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb.h

   1 #ifndef LINUX_SSB_H_
   2 #define LINUX_SSB_H_
   3 #ifdef __KERNEL__
   4
   5 #include <linux/device.h>
   6 #include <linux/list.h>
   7 #include <linux/types.h>
   8 #include <linux/spinlock.h>
   9
  10 #include <linux/ssb/ssb_regs.h>
  11
  12
  13 struct pcmcia_device;
  14 struct ssb_bus;
  15 struct ssb_driver;
  16
  17
  18 struct ssb_sprom_r1 {
  19         u16 pci_spid;           /* Subsystem Product ID for PCI */
  20         u16 pci_svid;           /* Subsystem Vendor ID for PCI */
  21         u16 pci_pid;            /* Product ID for PCI */
  22         u8 il0mac[6];           /* MAC address for 802.11b/g */
  23         u8 et0mac[6];           /* MAC address for Ethernet */
  24         u8 et1mac[6];           /* MAC address for 802.11a */
  25         u8 et0phyaddr:5;        /* MII address for enet0 */
  26         u8 et1phyaddr:5;        /* MII address for enet1 */
  27         u8 et0mdcport:1;        /* MDIO for enet0 */
  28         u8 et1mdcport:1;        /* MDIO for enet1 */
  29         u8 board_rev;           /* Board revision */
  30         u8 country_code:4;      /* Country Code */
  31         u8 antenna_a:2;         /* Antenna 0/1 available for A-PHY */
  32         u8 antenna_bg:2;        /* Antenna 0/1 available for B-PHY and G-PHY */
  33         u16 pa0b0;
  34         u16 pa0b1;
  35         u16 pa0b2;
  36         u16 pa1b0;
  37         u16 pa1b1;
  38         u16 pa1b2;
  39         u8 gpio0;               /* GPIO pin 0 */
  40         u8 gpio1;               /* GPIO pin 1 */
  41         u8 gpio2;               /* GPIO pin 2 */
  42         u8 gpio3;               /* GPIO pin 3 */
  43         u16 maxpwr_a;           /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */
  44         u16 maxpwr_bg;          /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */
  45         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
  46         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
  47         u16 boardflags_lo;      /* Boardflags (low 16 bits) */
  48         u8 antenna_gain_a;      /* A-PHY Antenna gain (in dBm Q5.2) */
  49         u8 antenna_gain_bg;     /* B/G-PHY Antenna gain (in dBm Q5.2) */
  50         u8 oem[8];              /* OEM string (rev 1 only) */
  51 };
  52
  53 struct ssb_sprom_r2 {
  54         u16 boardflags_hi;      /* Boardflags (high 16 bits) */
  55         u8 maxpwr_a_lo;         /* A-PHY Max Power Low */
  56         u8 maxpwr_a_hi;         /* A-PHY Max Power High */
  57         u16 pa1lob0;            /* A-PHY PA Low Settings */
  58         u16 pa1lob1;            /* A-PHY PA Low Settings */
  59         u16 pa1lob2;            /* A-PHY PA Low Settings */
  60         u16 pa1hib0;            /* A-PHY PA High Settings */
  61         u16 pa1hib1;            /* A-PHY PA High Settings */
  62         u16 pa1hib2;            /* A-PHY PA High Settings */
  63         u8 ofdm_pwr_off;        /* OFDM Power Offset from CCK Level */
  64         u8 country_str[2];      /* Two char Country Code */
  65 };
  66
  67 struct ssb_sprom_r3 {
  68         u32 ofdmapo;            /* A-PHY OFDM Mid Power Offset */
  69         u32 ofdmalpo;           /* A-PHY OFDM Low Power Offset */
  70         u32 ofdmahpo;           /* A-PHY OFDM High Power Offset */
  71         u8 gpioldc_on_cnt;      /* GPIO LED Powersave Duty Cycle ON count */
  72         u8 gpioldc_off_cnt;     /* GPIO LED Powersave Duty Cycle OFF count */
  73         u8 cckpo_1M:4;          /* CCK Power Offset for Rate 1M */
  74         u8 cckpo_2M:4;          /* CCK Power Offset for Rate 2M */
  75         u8 cckpo_55M:4;         /* CCK Power Offset for Rate 5.5M */
  76         u8 cckpo_11M:4;         /* CCK Power Offset for Rate 11M */
  77         u32 ofdmgpo;            /* G-PHY OFDM Power Offset */
  78 };
  79
  80 struct ssb_sprom_r4 {
  81         /* TODO */
  82 };
  83
  84 struct ssb_sprom {
  85         u8 revision;
  86         u8 crc;
  87         /* The valid r# fields are selected by the "revision".
  88          * Revision 3 and lower inherit from lower revisions.
  89          */
  90         union {
  91                 struct {
  92                         struct ssb_sprom_r1 r1;
  93                         struct ssb_sprom_r2 r2;
  94                         struct ssb_sprom_r3 r3;
  95                 };
  96                 struct ssb_sprom_r4 r4;
  97         };
  98 };
  99
 100
 101 /* Core-ID values. */
 102 #define SSB_DEV_CHIPCOMMON      0x800
 103 #define SSB_DEV_ILINE20         0x801
 104 #define SSB_DEV_SDRAM           0x803
 105 #define SSB_DEV_PCI             0x804
 106 #define SSB_DEV_MIPS            0x805
 107 #define SSB_DEV_ETHERNET        0x806
 108 #define SSB_DEV_V90             0x807
 109 #define SSB_DEV_USB11_HOSTDEV   0x808
 110 #define SSB_DEV_ADSL            0x809
 111 #define SSB_DEV_ILINE100        0x80A
 112 #define SSB_DEV_IPSEC           0x80B
 113 #define SSB_DEV_PCMCIA          0x80D
 114 #define SSB_DEV_INTERNAL_MEM    0x80E
 115 #define SSB_DEV_MEMC_SDRAM      0x80F
 116 #define SSB_DEV_EXTIF           0x811
 117 #define SSB_DEV_80211           0x812
 118 #define SSB_DEV_MIPS_3302       0x816
 119 #define SSB_DEV_USB11_HOST      0x817
 120 #define SSB_DEV_USB11_DEV       0x818
 121 #define SSB_DEV_USB20_HOST      0x819
 122 #define SSB_DEV_USB20_DEV       0x81A
 123 #define SSB_DEV_SDIO_HOST       0x81B
 124 #define SSB_DEV_ROBOSWITCH      0x81C
 125 #define SSB_DEV_PARA_ATA        0x81D
 126 #define SSB_DEV_SATA_XORDMA     0x81E
 127 #define SSB_DEV_ETHERNET_GBIT   0x81F
 128 #define SSB_DEV_PCIE            0x820
 129 #define SSB_DEV_MIMO_PHY        0x821
 130 #define SSB_DEV_SRAM_CTRLR      0x822
 131 #define SSB_DEV_MINI_MACPHY     0x823
 132 #define SSB_DEV_ARM_1176        0x824
 133 #define SSB_DEV_ARM_7TDMI       0x825
 134
 135 /* Vendor-ID values */
 136 #define SSB_VENDOR_BROADCOM     0x4243
 137
 138 struct ssb_device_id {
 139         u16 vendor;
 140         u16 coreid;
 141         u8 revision;
 142 };
 143 #define SSB_DEVICE(_vendor, _coreid, _revision)  \
 144         { .vendor = _vendor, .coreid = _coreid, .revision = _revision, }
 145 #define SSB_DEVTABLE_END  \
 146         { 0, },
 147
 148 #define SSB_ANY_VENDOR          0xFFFF
 149 #define SSB_ANY_ID              0xFFFF
 150 #define SSB_ANY_REV             0xFF
 151
 152
 153 struct ssb_device {
 154         struct device dev;
 155         struct ssb_bus *bus;
 156         struct ssb_device_id id;
 157
 158         u8 core_index;
 159         unsigned int irq;
 160         void *drvdata;          /* Per-device data */
 161         void *devtypedata;      /* Per-devicetype (eg 802.11) data */
 162 };
 163 #define dev_to_ssb_dev(_dev) container_of(_dev, struct ssb_device, dev)
 164
 165 /* Device specific user data */
 166 static inline
 167 void ssb_set_drvdata(struct ssb_device *dev, void *data)
 168 {
 169         dev->drvdata = data;
 170 }
 171 static inline
 172 void * ssb_get_drvdata(struct ssb_device *dev)
 173 {
 174         return dev->drvdata;
 175 }
 176
 177 /* Devicetype specific user data. This is per device-type (not per device) */
 178 void ssb_set_devtypedata(struct ssb_device *dev, void *data);
 179 static inline
 180 void * ssb_get_devtypedata(struct ssb_device *dev)
 181 {
 182         return dev->devtypedata;
 183 }
 184
 185 struct ssb_bus_ops {
 186         u16 (*read16)(struct ssb_device *dev, u16 offset);
 187         u32 (*read32)(struct ssb_device *dev, u16 offset);
 188         void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
 189         void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
 190 };
 191
 192
 193 struct ssb_driver {
 194         const char *name;
 195         const struct ssb_device_id *id_table;
 196
 197         int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
 198         void (*remove)(struct ssb_device *dev);
 199         int (*suspend)(struct ssb_device *dev, pm_message_t state);
 200         int (*resume)(struct ssb_device *dev);
 201         void (*shutdown)(struct ssb_device *dev);
 202
 203         struct device_driver drv;
 204 };
 205 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
 206
 207 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
 208 static inline int ssb_driver_register(struct ssb_driver *drv)
 209 {
 210         return __ssb_driver_register(drv, THIS_MODULE);
 211 }
 212 extern void ssb_driver_unregister(struct ssb_driver *drv);
 213
 214
 215
 216
 217 enum ssb_bustype {
 218         SSB_BUSTYPE_SSB,        /* This SSB bus is the system bus */
 219         SSB_BUSTYPE_PCI,        /* SSB is connected to PCI bus */
 220         SSB_BUSTYPE_PCMCIA,     /* SSB is connected to PCMCIA bus */
 221         //TODO SSB_BUSTYPE_JTAG,
 222 };
 223
 224 /* board_vendor */
 225 #define SSB_BOARDVENDOR_BCM     0x14E4  /* Broadcom */
 226 #define SSB_BOARDVENDOR_DELL    0x1028  /* Dell */
 227 #define SSB_BOARDVENDOR_HP      0x0E11  /* HP */
 228 /* board_type */
 229 #define SSB_BOARD_BCM94306MP    0x0418
 230 #define SSB_BOARD_BCM4309G      0x0421
 231 #define SSB_BOARD_BCM4306CB     0x0417
 232 #define SSB_BOARD_BCM4309MP     0x040C
 233 #define SSB_BOARD_MP4318        0x044A
 234 #define SSB_BOARD_BU4306        0x0416
 235 #define SSB_BOARD_BU4309        0x040A
 236 /* chip_package */
 237 #define SSB_CHIPPACK_BCM4712S   1       /* Small 200pin 4712 */
 238 #define SSB_CHIPPACK_BCM4712M   2       /* Medium 225pin 4712 */
 239 #define SSB_CHIPPACK_BCM4712L   0       /* Large 340pin 4712 */
 240
 241 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset);
 242 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset);
 243 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value);
 244 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value);
 245 static inline u32 ssb_write32_masked(struct ssb_device *dev, u16 offset, u32 mask, u32 value);
 246
 247 #include <linux/ssb/ssb_driver_chipcommon.h>
 248 #include <linux/ssb/ssb_driver_mips.h>
 249 #include <linux/ssb/ssb_driver_extif.h>
 250 #include <linux/ssb/ssb_driver_pci.h>
 251
 252 struct ssb_bus {
 253         /* The MMIO area. */
 254         void __iomem *mmio;
 255
 256         const struct ssb_bus_ops *ops;
 257
 258         /* The core in the basic address register window. (PCI bus only) */
 259         struct ssb_device *mapped_device;
 260         /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
 261         u8 mapped_pcmcia_seg;
 262         /* Lock for core and segment switching. */
 263         spinlock_t bar_lock;
 264
 265         /* The bus this backplane is running on. */
 266         enum ssb_bustype bustype;
 267         /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
 268         struct pci_dev *host_pci;
 269         /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
 270         struct pcmcia_device *host_pcmcia;
 271
 272         /* ID information about the PCB. */
 273         u16 board_vendor;
 274         u16 board_type;
 275         u16 board_rev;
 276         /* ID information about the Chip. */
 277         u16 chip_id;
 278         u16 chip_rev;
 279         u8 chip_package;
 280
 281         /* Contents of the SPROM.
 282          * If there is no sprom (not on PCI-bus), this is emulated. */
 283         struct ssb_sprom sprom;
 284
 285         /* List of devices (cores) on the backplane. */
 286         struct ssb_device devices[SSB_MAX_NR_CORES];
 287         u8 nr_devices;
 288
 289         /* Reference count. Number of suspended devices. */
 290         u8 suspend_cnt;
 291
 292         /* Software ID number for this bus. */
 293         int busnumber;
 294
 295         /* The ChipCommon device (if available). */
 296         struct ssb_chipcommon chipco;
 297         /* The PCI-core device (if available). */
 298         struct ssb_pcicore pcicore;
 299         /* The MIPS-core device (if available). */
 300         struct ssb_mipscore mipscore;
 301         /* The EXTif-core device (if available). */
 302         struct ssb_extif extif;
 303
 304         /* Internal. */
 305         struct list_head list;
 306 };
 307
 308 extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
 309                                    unsigned long baseaddr,
 310                                    void (*fill_sprom)(struct ssb_sprom *sprom));
 311 #ifdef CONFIG_SSB_PCIHOST
 312 extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
 313                                    struct pci_dev *host_pci);
 314 #endif /* CONFIG_SSB_PCIHOST */
 315 #ifdef CONFIG_SSB_PCMCIAHOST
 316 extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
 317                                       struct pcmcia_device *pcmcia_dev,
 318                                       unsigned long baseaddr,
 319                                       void (*fill_sprom)(struct ssb_sprom *sprom));
 320 #endif /* CONFIG_SSB_PCMCIAHOST */
 321
 322 extern void ssb_bus_unregister(struct ssb_bus *bus);
 323
 324 extern u32 ssb_clockspeed(struct ssb_bus *bus);
 325
 326 int ssb_device_is_enabled(struct ssb_device *dev);
 327 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
 328 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
 329
 330
 331 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
 332 {
 333         return dev->bus->ops->read16(dev, offset);
 334 }
 335 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
 336 {
 337         return dev->bus->ops->read32(dev, offset);
 338 }
 339 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
 340 {
 341         dev->bus->ops->write16(dev, offset, value);
 342 }
 343 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
 344 {
 345         dev->bus->ops->write32(dev, offset, value);
 346 }
 347
 348 static inline u32 ssb_write32_masked(struct ssb_device *dev,
 349                                   u16 offset,
 350                                   u32 mask,
 351                                   u32 value)
 352 {
 353         value &= mask;
 354         value |= ssb_read32(dev, offset) & ~mask;
 355         ssb_write32(dev, offset, value);
 356         return value;
 357 }
 358
 359
 360 /* Translation (routing) bits that need to be ORed to DMA
 361  * addresses before they are given to a device. */
 362 extern u32 ssb_dma_translation(struct ssb_device *dev);
 363 #define SSB_DMA_TRANSLATION_MASK        0xC0000000
 364 #define SSB_DMA_TRANSLATION_SHIFT       30
 365
 366 extern int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask);
 367
 368
 369 /* Various helper functions */
 370 extern u32 ssb_admatch_base(u32 adm);
 371 extern u32 ssb_admatch_size(u32 adm);
 372
 373
 374 #endif /* __KERNEL__ */
 375 #endif /* LINUX_SSB_H_ */