4 compatible = "brcm,bcm3368";
20 compatible = "brcm,bmips4350", "mips,mips4Kc";
26 compatible = "brcm,bmips4350", "mips,mips4Kc";
32 cpu_intc: interrupt-controller {
34 compatible = "mti,cpu-interrupt-controller";
37 #interrupt-cells = <1>;
40 memory { device_type = "memory"; reg = <0 0>; };
42 pflash: nor@1e000000 {
43 compatible = "cfi-flash";
44 reg = <0x1e000000 0x2000000>;
56 compatible = "simple-bus";
57 interrupt-parent = <&periph_intc>;
59 periph_intc: interrupt-controller@fff8c00c {
60 compatible = "brcm,bcm6345-l1-intc";
61 reg = <0xfff8c00c 0x8>;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 ext_intc0: interrupt-controller@fff8c014 {
71 compatible = "brcm,bcm6345-ext-intc";
72 reg = <0xfff8c014 0x4>;
75 #interrupt-cells = <2>;
77 interrupts = <25>, <26>, <27>, <28>;
80 gpio1: gpio-controller@fff8c080 {
81 compatible = "brcm,bcm6345-gpio";
82 reg = <0xfff8c080 4>, <0xfff8c088 4>;
90 gpio0: gpio-controller@fff8c084 {
91 compatible = "brcm,bcm6345-gpio";
92 reg = <0xfff8c084 4>, <0xfff8c08c 4>;
98 uart0: serial@fff8c100 {
99 compatible = "brcm,bcm6345-uart";
100 reg = <0xfff8c100 0x18>;
102 interrupt-parent = <&periph_intc>;
105 /* clocks = <&periph_clk>; */
106 /* clock-names = "refclk"; */
111 uart1: serial@fff8c120 {
112 compatible = "brcm,bcm6345-uart";
113 reg = <0xfff8c120 0x18>;
115 interrupt-parent = <&periph_intc>;
118 /* clocks = <&periph_clk>; */
119 /* clock-names = "refclk"; */
124 lsspi: spi@fff8c800 {
125 #address-cells = <1>;
127 compatible = "brcm,bcm6358-spi";
128 reg = <0xfff8c800 0x70c>;
130 /* clocks = <&clkctl 9>; */