dfe709ce680fde539cd2fe5907be74e738d89da2
[openwrt/staging/lynxis/omap.git] / target / linux / brcm63xx / patches-3.10 / 205-USB-fix-bcm63xx_udc.patch
1 --- a/drivers/usb/gadget/bcm63xx_udc.c
2 +++ b/drivers/usb/gadget/bcm63xx_udc.c
3 @@ -362,24 +362,30 @@ static inline void usb_dma_writel(struct
4 bcm_writel(val, udc->iudma_regs + off);
5 }
6
7 -static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off)
8 +static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off, int chan)
9 {
10 - return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off);
11 + return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off +
12 + (ENETDMA_CHAN_WIDTH * chan));
13 }
14
15 -static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
16 +static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off,
17 + int chan)
18 {
19 - bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off);
20 + bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off +
21 + (ENETDMA_CHAN_WIDTH* chan));
22 }
23
24 -static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off)
25 +static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off, int chan)
26 {
27 - return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off);
28 + return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off +
29 + (ENETDMA_CHAN_WIDTH* chan));
30 }
31
32 -static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
33 +static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off,
34 + int chan)
35 {
36 - bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off);
37 + bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off +
38 + (ENETDMA_CHAN_WIDTH * chan));
39 }
40
41 static inline void set_clocks(struct bcm63xx_udc *udc, bool is_enabled)
42 @@ -639,7 +645,7 @@ static void iudma_write(struct bcm63xx_u
43 } while (!last_bd);
44
45 usb_dmac_writel(udc, ENETDMAC_CHANCFG_EN_MASK,
46 - ENETDMAC_CHANCFG_REG(iudma->ch_idx));
47 + ENETDMAC_CHANCFG_REG, iudma->ch_idx);
48 }
49
50 /**
51 @@ -695,9 +701,9 @@ static void iudma_reset_channel(struct b
52 bcm63xx_fifo_reset_ep(udc, max(0, iudma->ep_num));
53
54 /* stop DMA, then wait for the hardware to wrap up */
55 - usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG(ch_idx));
56 + usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG, ch_idx);
57
58 - while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)) &
59 + while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx) &
60 ENETDMAC_CHANCFG_EN_MASK) {
61 udelay(1);
62
63 @@ -714,10 +720,10 @@ static void iudma_reset_channel(struct b
64 dev_warn(udc->dev, "forcibly halting IUDMA channel %d\n",
65 ch_idx);
66 usb_dmac_writel(udc, ENETDMAC_CHANCFG_BUFHALT_MASK,
67 - ENETDMAC_CHANCFG_REG(ch_idx));
68 + ENETDMAC_CHANCFG_REG, ch_idx);
69 }
70 }
71 - usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG(ch_idx));
72 + usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG, ch_idx);
73
74 /* don't leave "live" HW-owned entries for the next guy to step on */
75 for (d = iudma->bd_ring; d <= iudma->end_bd; d++)
76 @@ -729,11 +735,11 @@ static void iudma_reset_channel(struct b
77
78 /* set up IRQs, UBUS burst size, and BD base for this channel */
79 usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK,
80 - ENETDMAC_IRMASK_REG(ch_idx));
81 - usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG(ch_idx));
82 + ENETDMAC_IRMASK_REG, ch_idx);
83 + usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG, ch_idx);
84
85 - usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG(ch_idx));
86 - usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG(ch_idx));
87 + usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG, ch_idx);
88 + usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG, ch_idx);
89 }
90
91 /**
92 @@ -2016,7 +2022,7 @@ static irqreturn_t bcm63xx_udc_data_isr(
93 spin_lock(&udc->lock);
94
95 usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK,
96 - ENETDMAC_IR_REG(iudma->ch_idx));
97 + ENETDMAC_IR_REG, iudma->ch_idx);
98 bep = iudma->bep;
99 rc = iudma_read(udc, iudma);
100
101 @@ -2156,18 +2162,18 @@ static int bcm63xx_iudma_dbg_show(struct
102 seq_printf(s, " [ep%d]:\n",
103 max_t(int, iudma_defaults[ch_idx].ep_num, 0));
104 seq_printf(s, " cfg: %08x; irqstat: %08x; irqmask: %08x; maxburst: %08x\n",
105 - usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)),
106 - usb_dmac_readl(udc, ENETDMAC_IR_REG(ch_idx)),
107 - usb_dmac_readl(udc, ENETDMAC_IRMASK_REG(ch_idx)),
108 - usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG(ch_idx)));
109 + usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx),
110 + usb_dmac_readl(udc, ENETDMAC_IR_REG, ch_idx)),
111 + usb_dmac_readl(udc, ENETDMAC_IRMASK_REG, ch_idx),
112 + usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG, ch_idx);
113
114 - sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG(ch_idx));
115 - sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG(ch_idx));
116 + sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG, ch_idx);
117 + sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG, ch_idx);
118 seq_printf(s, " base: %08x; index: %04x_%04x; desc: %04x_%04x %08x\n",
119 - usb_dmas_readl(udc, ENETDMAS_RSTART_REG(ch_idx)),
120 + usb_dmas_readl(udc, ENETDMAS_RSTART_REG, ch_idx),
121 sram2 >> 16, sram2 & 0xffff,
122 sram3 >> 16, sram3 & 0xffff,
123 - usb_dmas_readl(udc, ENETDMAS_SRAM4_REG(ch_idx)));
124 + usb_dmas_readl(udc, ENETDMAS_SRAM4_REG, ch_idx));
125 seq_printf(s, " desc: %d/%d used", iudma->n_bds_used,
126 iudma->n_bds);
127