1 From 5f592b818a2c5731bb12137e7cffc3aa6e24ee5a Mon Sep 17 00:00:00 2001
2 From: Florian Fainelli <florian@openwrt.org>
3 Date: Wed, 1 Feb 2012 09:14:09 +0000
4 Subject: [PATCH 13/63] spi: add Broadcom BCM63xx SPI controller driver
6 This patch adds support for the SPI controller found on the Broadcom BCM63xx
9 Signed-off-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
10 Signed-off-by: Florian Fainelli <florian@openwrt.org>
11 Acked-by: Grant Likely <grant.likely@secretlab.ca>
13 drivers/spi/Kconfig | 6 +
14 drivers/spi/Makefile | 1 +
15 drivers/spi/spi-bcm63xx.c | 486 +++++++++++++++++++++++++++++++++++++++++++++
16 3 files changed, 493 insertions(+), 0 deletions(-)
17 create mode 100644 drivers/spi/spi-bcm63xx.c
19 --- a/drivers/spi/Kconfig
20 +++ b/drivers/spi/Kconfig
21 @@ -94,6 +94,12 @@ config SPI_AU1550
22 If you say yes to this option, support will be included for the
23 PSC SPI controller found on Au1550, Au1200 and Au1300 series.
26 + tristate "Broadcom BCM63xx SPI controller"
29 + Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
32 tristate "Utilities for Bitbanging SPI masters"
34 --- a/drivers/spi/Makefile
35 +++ b/drivers/spi/Makefile
36 @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.
37 obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
38 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
39 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
40 +obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
41 obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
42 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
43 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
45 +++ b/drivers/spi/spi-bcm63xx.c
48 + * Broadcom BCM63xx SPI controller support
50 + * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
51 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
53 + * This program is free software; you can redistribute it and/or
54 + * modify it under the terms of the GNU General Public License
55 + * as published by the Free Software Foundation; either version 2
56 + * of the License, or (at your option) any later version.
58 + * This program is distributed in the hope that it will be useful,
59 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
60 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
61 + * GNU General Public License for more details.
63 + * You should have received a copy of the GNU General Public License
64 + * along with this program; if not, write to the
65 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
68 +#include <linux/kernel.h>
69 +#include <linux/init.h>
70 +#include <linux/clk.h>
71 +#include <linux/io.h>
72 +#include <linux/module.h>
73 +#include <linux/platform_device.h>
74 +#include <linux/delay.h>
75 +#include <linux/interrupt.h>
76 +#include <linux/spi/spi.h>
77 +#include <linux/completion.h>
78 +#include <linux/err.h>
80 +#include <bcm63xx_dev_spi.h>
82 +#define PFX KBUILD_MODNAME
83 +#define DRV_VER "0.1.2"
88 + struct completion done;
98 + const unsigned char *tx_ptr;
99 + unsigned char *rx_ptr;
103 + const u8 __iomem *rx_io;
105 + int remaining_bytes;
108 + struct platform_device *pdev;
111 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
112 + unsigned int offset)
114 + return bcm_readb(bs->regs + bcm63xx_spireg(offset));
117 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
118 + unsigned int offset)
120 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
123 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
124 + u8 value, unsigned int offset)
126 + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
129 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
130 + u16 value, unsigned int offset)
132 + bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
135 +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
136 + { 20000000, SPI_CLK_20MHZ },
137 + { 12500000, SPI_CLK_12_50MHZ },
138 + { 6250000, SPI_CLK_6_250MHZ },
139 + { 3125000, SPI_CLK_3_125MHZ },
140 + { 1563000, SPI_CLK_1_563MHZ },
141 + { 781000, SPI_CLK_0_781MHZ },
142 + { 391000, SPI_CLK_0_391MHZ }
145 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
146 + struct spi_transfer *t)
148 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
154 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
155 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
156 + if (bits_per_word != 8) {
157 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
158 + __func__, bits_per_word);
162 + if (spi->chip_select > spi->master->num_chipselect) {
163 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
164 + __func__, spi->chip_select);
168 + /* Find the closest clock configuration */
169 + for (i = 0; i < SPI_CLK_MASK; i++) {
170 + if (hz >= bcm63xx_spi_freq_table[i][0]) {
171 + clk_cfg = bcm63xx_spi_freq_table[i][1];
176 + /* No matching configuration found, default to lowest */
177 + if (i == SPI_CLK_MASK)
178 + clk_cfg = SPI_CLK_0_391MHZ;
180 + /* clear existing clock configuration bits of the register */
181 + reg = bcm_spi_readb(bs, SPI_CLK_CFG);
182 + reg &= ~SPI_CLK_MASK;
185 + bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
186 + dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
192 +/* the spi->mode bits understood by this driver: */
193 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
195 +static int bcm63xx_spi_setup(struct spi_device *spi)
197 + struct bcm63xx_spi *bs;
200 + bs = spi_master_get_devdata(spi->master);
205 + if (!spi->bits_per_word)
206 + spi->bits_per_word = 8;
208 + if (spi->mode & ~MODEBITS) {
209 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
210 + __func__, spi->mode & ~MODEBITS);
214 + ret = bcm63xx_spi_setup_transfer(spi, NULL);
216 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
217 + spi->mode & ~MODEBITS);
221 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
222 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
227 +/* Fill the TX FIFO with as many bytes as possible */
228 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
232 + /* Fill the Tx FIFO with as many bytes as possible */
233 + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
235 + memcpy_toio(bs->tx_io, bs->tx_ptr, size);
236 + bs->remaining_bytes -= size;
239 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
241 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
245 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
246 + t->tx_buf, t->rx_buf, t->len);
248 + /* Transmitter is inhibited */
249 + bs->tx_ptr = t->tx_buf;
250 + bs->rx_ptr = t->rx_buf;
251 + init_completion(&bs->done);
254 + bs->remaining_bytes = t->len;
255 + bcm63xx_spi_fill_tx_fifo(bs);
258 + /* Enable the command done interrupt which
259 + * we use to determine completion of a command */
260 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
262 + /* Fill in the Message control register */
263 + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
265 + if (t->rx_buf && t->tx_buf)
266 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
267 + else if (t->rx_buf)
268 + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
269 + else if (t->tx_buf)
270 + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
272 + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
274 + /* Issue the transfer */
275 + cmd = SPI_CMD_START_IMMEDIATE;
276 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
277 + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
278 + bcm_spi_writew(bs, cmd, SPI_CMD);
279 + wait_for_completion(&bs->done);
281 + /* Disable the CMD_DONE interrupt */
282 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
284 + return t->len - bs->remaining_bytes;
287 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
289 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
290 + struct spi_transfer *t;
293 + if (unlikely(list_empty(&m->transfers)))
299 + list_for_each_entry(t, &m->transfers, transfer_list) {
300 + ret += bcm63xx_txrx_bufs(spi, t);
303 + m->complete(m->context);
308 +/* This driver supports single master mode only. Hence
309 + * CMD_DONE is the only interrupt we care about
311 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
313 + struct spi_master *master = (struct spi_master *)dev_id;
314 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
318 + /* Read interupts and clear them immediately */
319 + intr = bcm_spi_readb(bs, SPI_INT_STATUS);
320 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
321 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
323 + /* A tansfer completed */
324 + if (intr & SPI_INTR_CMD_DONE) {
327 + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
329 + /* Read out all the data */
331 + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
333 + /* See if there is more data to send */
334 + if (bs->remaining_bytes > 0) {
335 + bcm63xx_spi_fill_tx_fifo(bs);
337 + /* Start the transfer */
338 + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
340 + cmd = bcm_spi_readw(bs, SPI_CMD);
341 + cmd |= SPI_CMD_START_IMMEDIATE;
342 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
343 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
344 + bcm_spi_writew(bs, cmd, SPI_CMD);
346 + complete(&bs->done);
350 + return IRQ_HANDLED;
354 +static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
356 + struct resource *r;
357 + struct device *dev = &pdev->dev;
358 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
360 + struct spi_master *master;
362 + struct bcm63xx_spi *bs;
365 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
367 + dev_err(dev, "no iomem\n");
372 + irq = platform_get_irq(pdev, 0);
374 + dev_err(dev, "no irq\n");
379 + clk = clk_get(dev, "spi");
381 + dev_err(dev, "no clock for device\n");
382 + ret = PTR_ERR(clk);
386 + master = spi_alloc_master(dev, sizeof(*bs));
388 + dev_err(dev, "out of memory\n");
393 + bs = spi_master_get_devdata(master);
394 + init_completion(&bs->done);
396 + platform_set_drvdata(pdev, master);
399 + if (!devm_request_mem_region(&pdev->dev, r->start,
400 + resource_size(r), PFX)) {
401 + dev_err(dev, "iomem request failed\n");
406 + bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
409 + dev_err(dev, "unable to ioremap regs\n");
416 + bs->fifo_size = pdata->fifo_size;
418 + ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
419 + pdev->name, master);
421 + dev_err(dev, "unable to request irq\n");
425 + master->bus_num = pdata->bus_num;
426 + master->num_chipselect = pdata->num_chipselect;
427 + master->setup = bcm63xx_spi_setup;
428 + master->transfer = bcm63xx_transfer;
429 + bs->speed_hz = pdata->speed_hz;
431 + bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
432 + bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
433 + spin_lock_init(&bs->lock);
435 + /* Initialize hardware */
436 + clk_enable(bs->clk);
437 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
439 + /* register and we are done */
440 + ret = spi_register_master(master);
442 + dev_err(dev, "spi register failed\n");
443 + goto out_clk_disable;
446 + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
447 + r->start, irq, bs->fifo_size, DRV_VER);
454 + platform_set_drvdata(pdev, NULL);
455 + spi_master_put(master);
462 +static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
464 + struct spi_master *master = platform_get_drvdata(pdev);
465 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
467 + /* reset spi block */
468 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
469 + spin_lock(&bs->lock);
473 + clk_disable(bs->clk);
476 + spin_unlock(&bs->lock);
477 + platform_set_drvdata(pdev, 0);
478 + spi_unregister_master(master);
484 +static int bcm63xx_spi_suspend(struct device *dev)
486 + struct spi_master *master =
487 + platform_get_drvdata(to_platform_device(dev));
488 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
490 + clk_disable(bs->clk);
495 +static int bcm63xx_spi_resume(struct device *dev)
497 + struct spi_master *master =
498 + platform_get_drvdata(to_platform_device(dev));
499 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
501 + clk_enable(bs->clk);
506 +static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
507 + .suspend = bcm63xx_spi_suspend,
508 + .resume = bcm63xx_spi_resume,
511 +#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
513 +#define BCM63XX_SPI_PM_OPS NULL
516 +static struct platform_driver bcm63xx_spi_driver = {
518 + .name = "bcm63xx-spi",
519 + .owner = THIS_MODULE,
520 + .pm = BCM63XX_SPI_PM_OPS,
522 + .probe = bcm63xx_spi_probe,
523 + .remove = __devexit_p(bcm63xx_spi_remove),
526 +module_platform_driver(bcm63xx_spi_driver);
528 +MODULE_ALIAS("platform:bcm63xx_spi");
529 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
530 +MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
531 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
532 +MODULE_LICENSE("GPL");