1 From 3f4570c9794fcae1cf62fbf3266a2e23edac67a5 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Wed, 27 Jun 2012 15:01:09 +0200
4 Subject: [PATCH 3/7] MIPS: BCM63XX: rework chip detection
6 Instead of trying to use a correlation of cpu prid and chip id and
7 hoping they will always be unique, use the cpu prid to determine the
8 chip id register location and just read out the chip id.
10 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
12 arch/mips/bcm63xx/cpu.c | 87 +++++++++++++++++++++++------------------------
13 1 file changed, 42 insertions(+), 45 deletions(-)
15 --- a/arch/mips/bcm63xx/cpu.c
16 +++ b/arch/mips/bcm63xx/cpu.c
17 @@ -240,53 +240,27 @@ static unsigned int detect_memory_size(v
19 void __init bcm63xx_cpu_init(void)
21 - unsigned int tmp, expected_cpu_id;
23 struct cpuinfo_mips *c = ¤t_cpu_data;
24 unsigned int cpu = smp_processor_id();
27 /* soc registers location depends on cpu type */
28 - expected_cpu_id = 0;
33 - if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
34 - expected_cpu_id = BCM6348_CPU_ID;
35 - bcm63xx_regs_base = bcm6348_regs_base;
36 - bcm63xx_irqs = bcm6348_irqs;
38 + if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
39 __cpu_name[cpu] = "Broadcom BCM6338";
40 - expected_cpu_id = BCM6338_CPU_ID;
41 - bcm63xx_regs_base = bcm6338_regs_base;
42 - bcm63xx_irqs = bcm6338_irqs;
47 - expected_cpu_id = BCM6345_CPU_ID;
48 - bcm63xx_regs_base = bcm6345_regs_base;
49 - bcm63xx_irqs = bcm6345_irqs;
50 + chipid_reg = BCM_6345_PERF_BASE;
53 - if ((read_c0_prid() & 0xf0) == 0x10) {
54 - expected_cpu_id = BCM6358_CPU_ID;
55 - bcm63xx_regs_base = bcm6358_regs_base;
56 - bcm63xx_irqs = bcm6358_irqs;
58 - /* all newer chips have the same chip id location */
59 - u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
62 - case BCM6328_CPU_ID:
63 - expected_cpu_id = BCM6328_CPU_ID;
64 - bcm63xx_regs_base = bcm6328_regs_base;
65 - bcm63xx_irqs = bcm6328_irqs;
67 - case BCM6368_CPU_ID:
68 - expected_cpu_id = BCM6368_CPU_ID;
69 - bcm63xx_regs_base = bcm6368_regs_base;
70 - bcm63xx_irqs = bcm6368_irqs;
74 + if ((read_c0_prid() & 0xf0) == 0x10)
75 + chipid_reg = BCM_6345_PERF_BASE;
77 + chipid_reg = BCM_6368_PERF_BASE;
81 @@ -294,20 +268,43 @@ void __init bcm63xx_cpu_init(void)
82 * really early to panic, but delaying panic would not help since we
83 * will never get any working console
85 - if (!expected_cpu_id)
87 panic("unsupported Broadcom CPU");
90 - * bcm63xx_regs_base is set, we can access soc registers
93 - /* double check CPU type */
94 - tmp = bcm_perf_readl(PERF_REV_REG);
95 + /* read out CPU type */
96 + tmp = bcm_readl(chipid_reg);
97 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
98 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
100 - if (bcm63xx_cpu_id != expected_cpu_id)
101 - panic("bcm63xx CPU id mismatch");
102 + switch (bcm63xx_cpu_id) {
103 + case BCM6328_CPU_ID:
104 + bcm63xx_regs_base = bcm6328_regs_base;
105 + bcm63xx_irqs = bcm6328_irqs;
107 + case BCM6338_CPU_ID:
108 + bcm63xx_regs_base = bcm6338_regs_base;
109 + bcm63xx_irqs = bcm6338_irqs;
111 + case BCM6345_CPU_ID:
112 + bcm63xx_regs_base = bcm6345_regs_base;
113 + bcm63xx_irqs = bcm6345_irqs;
115 + case BCM6348_CPU_ID:
116 + bcm63xx_regs_base = bcm6348_regs_base;
117 + bcm63xx_irqs = bcm6348_irqs;
119 + case BCM6358_CPU_ID:
120 + bcm63xx_regs_base = bcm6358_regs_base;
121 + bcm63xx_irqs = bcm6358_irqs;
123 + case BCM6368_CPU_ID:
124 + bcm63xx_regs_base = bcm6368_regs_base;
125 + bcm63xx_irqs = bcm6368_irqs;
128 + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
132 bcm63xx_cpu_freq = detect_cpu_clock();
133 bcm63xx_memory_size = detect_memory_size();