1 From 4b27423676485d05bcd6fc6f3809164fb8f9d22d Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sat, 12 Nov 2011 12:19:55 +0100
4 Subject: [PATCH 30/60] SPI: MIPS: BCM63XX: Add HSSPI driver
6 Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
8 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
10 .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h | 2 +
11 drivers/spi/Kconfig | 7 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/spi-bcm63xx-hsspi.c | 427 ++++++++++++++++++++
14 4 files changed, 437 insertions(+), 0 deletions(-)
15 create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c
17 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
18 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
19 @@ -18,4 +18,6 @@ struct bcm63xx_hsspi_pdata {
20 #define HSSPI_PLL_HZ_6328 133333333
21 #define HSSPI_PLL_HZ_6362 400000000
23 +#define HSSPI_BUFFER_LEN 512
25 #endif /* BCM63XX_DEV_HSSPI_H */
26 --- a/drivers/spi/Kconfig
27 +++ b/drivers/spi/Kconfig
28 @@ -100,6 +100,13 @@ config SPI_BCM63XX
30 Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
32 +config SPI_BCM63XX_HSSPI
33 + tristate "Broadcom BCM63XX HS SPI controller driver"
36 + This enables support for the High Speed SPI controller present on
37 + newer Broadcom BCM63XX SoCs.
40 tristate "Utilities for Bitbanging SPI masters"
42 --- a/drivers/spi/Makefile
43 +++ b/drivers/spi/Makefile
44 @@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
45 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
46 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
47 obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
48 +obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
49 obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
50 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
51 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
53 +++ b/drivers/spi/spi-bcm63xx-hsspi.c
56 + * Broadcom BCM63XX High Speed SPI Controller driver
58 + * Copyright 2000-2010 Broadcom Corporation
59 + * Copyright 2012 Jonas Gorski <jonas.gorski@gmail.com>
61 + * Licensed under the GNU/GPL. See COPYING for details.
64 +#include <linux/kernel.h>
65 +#include <linux/init.h>
66 +#include <linux/io.h>
67 +#include <linux/clk.h>
68 +#include <linux/module.h>
69 +#include <linux/platform_device.h>
70 +#include <linux/delay.h>
71 +#include <linux/dma-mapping.h>
72 +#include <linux/err.h>
73 +#include <linux/interrupt.h>
74 +#include <linux/spi/spi.h>
75 +#include <linux/workqueue.h>
77 +#include <bcm63xx_regs.h>
78 +#include <bcm63xx_dev_hsspi.h>
80 +#define HSSPI_OP_CODE_SHIFT 13
81 +#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
82 +#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
83 +#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
84 +#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
86 +#define HSSPI_MAX_PREPEND_LEN 15
88 +#define HSSPI_MAX_SYNC_CLOCK 30000000
90 +struct bcm63xx_hsspi {
91 + struct completion done;
92 + struct spi_transfer *curr_trans;
94 + struct platform_device *pdev;
103 +static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, int hz,
108 + reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
109 + bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
110 + HSSPI_PROFILE_CLK_CTRL_REG(profile));
112 + reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
113 + if (hz > HSSPI_MAX_SYNC_CLOCK)
114 + reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
116 + reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
117 + bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
120 +static int bcm63xx_hsspi_do_txrx(struct spi_device *spi,
121 + struct spi_transfer *t1,
122 + struct spi_transfer *t2)
124 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
125 + u8 chip_select = spi->chip_select;
127 + int len, prepend_size = 0;
129 + init_completion(&bs->done);
131 + bs->curr_trans = t2 ? t2 : t1;
132 + bcm63xx_hsspi_set_clk(bs, bs->curr_trans->speed_hz, chip_select);
134 + if (t2 && !t2->tx_buf)
135 + prepend_size = t1->len;
137 + bcm_hsspi_writel(prepend_size << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
138 + 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
139 + 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
140 + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
142 + if (t1->rx_buf && t1->tx_buf)
143 + opcode = HSSPI_OP_READ_WRITE;
144 + else if (t1->rx_buf || (t2 && t2->rx_buf))
145 + opcode = HSSPI_OP_READ;
146 + else if (t1->tx_buf)
147 + opcode = HSSPI_OP_WRITE;
149 + if (opcode == HSSPI_OP_READ && t2)
155 + memcpy_toio(bs->fifo + 2, t1->tx_buf, t1->len);
156 + if (t2 && t2->tx_buf) {
157 + memcpy_toio(bs->fifo + 2 + t1->len,
158 + t2->tx_buf, t2->len);
164 + memcpy_toio(bs->fifo, &opcode, sizeof(opcode));
166 + /* enable interrupt */
167 + bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
169 + /* start the transfer */
170 + bcm_hsspi_writel(chip_select << PINGPONG_CMD_SS_SHIFT |
171 + chip_select << PINGPONG_CMD_PROFILE_SHIFT |
172 + PINGPONG_COMMAND_START_NOW,
173 + HSSPI_PINGPONG_COMMAND_REG(0));
175 + if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
176 + dev_err(&bs->pdev->dev, "transfer timed out!\n");
180 + return t1->len + (t2 ? t2->len : 0);
183 +static int bcm63xx_hsspi_setup(struct spi_device *spi)
187 + if (spi->bits_per_word != 8)
190 + if (spi->max_speed_hz == 0)
193 + reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
194 + reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
195 + if (spi->mode & SPI_CPHA)
196 + reg |= SIGNAL_CTRL_LAUNCH_RISING;
198 + reg |= SIGNAL_CTRL_LATCH_RISING;
199 + bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
204 +static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
205 + struct spi_message *msg)
207 + struct spi_transfer *t, *prev = NULL;
208 + struct spi_device *spi = msg->spi;
213 + /* check if we are able to make these transfers */
214 + list_for_each_entry(t, &msg->transfers, transfer_list) {
215 + if (!t->tx_buf && !t->rx_buf)
218 + if (t->speed_hz == 0)
219 + t->speed_hz = spi->max_speed_hz;
221 + if (t->speed_hz > spi->max_speed_hz)
224 + if (t->len > HSSPI_BUFFER_LEN)
228 + * This controller does not support keeping the chip select
229 + * active between transfers.
230 + * This logic currently supports combining:
231 + * write then read with no cs_change (e.g. m25p80 RDSR)
232 + * write then write with no cs_change (e.g. m25p80 PP)
234 + if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
236 + * reject if we have to combine two tx transfers and
237 + * their combined length is bigger than the buffer
239 + if (prev->tx_buf && t->tx_buf &&
240 + (prev->len + t->len) > HSSPI_BUFFER_LEN)
243 + * reject if we need write more than 15 bytes in read
246 + if (prev->tx_buf && t->rx_buf &&
247 + prev->len > HSSPI_MAX_PREPEND_LEN)
253 + /* setup clock polarity */
254 + reg = bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG);
255 + reg &= ~GLOBAL_CTRL_CLK_POLARITY;
256 + if (spi->mode & SPI_CPOL)
257 + reg |= GLOBAL_CTRL_CLK_POLARITY;
258 + bcm_hsspi_writel(reg, HSSPI_GLOBAL_CTRL_REG);
260 + list_for_each_entry(t, &msg->transfers, transfer_list) {
261 + if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
262 + /* combine write with following transfer */
263 + ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
272 + /* write the previous pending transfer */
273 + if (prev != NULL) {
274 + ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
284 + /* do last pending transfer */
285 + if (prev != NULL) {
286 + ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
292 + msg->actual_length = len;
296 + spi_finalize_current_message(master);
300 +static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
302 + struct spi_master *master = (struct spi_master *)dev_id;
303 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
305 + if (bcm_hsspi_readl(HSSPI_INT_STATUS_MASKED_REG) == 0)
308 + bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
309 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
311 + if (bs->curr_trans && bs->curr_trans->rx_buf)
312 + memcpy_fromio(bs->curr_trans->rx_buf, bs->fifo,
313 + bs->curr_trans->len);
314 + complete(&bs->done);
316 + return IRQ_HANDLED;
319 +static int bcm63xx_hsspi_probe(struct platform_device *pdev)
322 + struct spi_master *master;
323 + struct bcm63xx_hsspi *bs;
324 + struct resource *res_mem;
325 + void __iomem *regs;
326 + struct device *dev = &pdev->dev;
327 + struct bcm63xx_hsspi_pdata *pdata = pdev->dev.platform_data;
332 + irq = platform_get_irq(pdev, 0);
334 + dev_err(dev, "no irq\n");
338 + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339 + regs = devm_request_and_ioremap(dev, res_mem);
341 + dev_err(dev, "unable to ioremap regs\n");
345 + clk = clk_get(dev, "hsspi");
348 + ret = PTR_ERR(clk);
352 + clk_prepare_enable(clk);
354 + master = spi_alloc_master(&pdev->dev, sizeof(*bs));
357 + goto out_disable_clk;
360 + bs = spi_master_get_devdata(master);
365 + master->bus_num = pdata->bus_num;
366 + master->num_chipselect = 8;
367 + master->setup = bcm63xx_hsspi_setup;
368 + master->transfer_one_message = bcm63xx_hsspi_transfer_one;
369 + master->mode_bits = SPI_CPOL | SPI_CPHA;
371 + bs->speed_hz = pdata->speed_hz;
372 + bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
374 + platform_set_drvdata(pdev, master);
376 + bs->curr_trans = NULL;
378 + /* Initialize the hardware */
379 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
381 + /* clean up any pending interrupts */
382 + bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
384 + bcm_hsspi_writel(bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG) |
385 + GLOBAL_CTRL_CLK_GATE_SSOFF,
386 + HSSPI_GLOBAL_CTRL_REG);
388 + ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
389 + pdev->name, master);
392 + goto out_put_master;
394 + /* register and we are done */
395 + ret = spi_register_master(master);
402 + devm_free_irq(dev, bs->irq, master);
404 + spi_master_put(master);
406 + clk_disable_unprepare(clk);
409 + devm_ioremap_release(dev, regs);
415 +static int __exit bcm63xx_hsspi_remove(struct platform_device *pdev)
417 + struct spi_master *master = platform_get_drvdata(pdev);
418 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
420 + spi_unregister_master(master);
422 + /* reset the hardware and block queue progress */
423 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
424 + clk_disable_unprepare(bs->clk);
431 +static int bcm63xx_hsspi_suspend(struct platform_device *pdev,
434 + struct spi_master *master = platform_get_drvdata(pdev);
435 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
437 + spi_master_suspend(master);
438 + clk_disable(bs->clk);
443 +static int bcm63xx_hsspi_resume(struct platform_device *pdev)
445 + struct spi_master *master = platform_get_drvdata(pdev);
446 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
448 + clk_enable(bs->clk);
449 + spi_master_resume(master);
454 +static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
455 + .suspend = bcm63xx_hsspi_suspend,
456 + .resume = bcm63xx_hsspi_resume,
459 +#define BCM63XX_HSSPI_PM_OPS (&bcm63xx_hsspi_pm_ops)
461 +#define BCM63XX_HSSPI_PM_OPS NULL
466 +static struct platform_driver bcm63xx_hsspi_driver = {
468 + .name = "bcm63xx-hsspi",
469 + .owner = THIS_MODULE,
470 + .pm = BCM63XX_HSSPI_PM_OPS,
472 + .probe = bcm63xx_hsspi_probe,
473 + .remove = __exit_p(bcm63xx_hsspi_remove),
476 +module_platform_driver(bcm63xx_hsspi_driver);
478 +MODULE_ALIAS("platform:bcm63xx_hsspi");
479 +MODULE_DESCRIPTION("Broadcom BCM63xx HS SPI Controller driver");
480 +MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
481 +MODULE_LICENSE("GPL");