target/linux/brcm63xx/patches-3.8/440-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch

   1 From eef84812bc7ffd590da6ad6b83bfeebaa43a7055 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Thu, 5 Jul 2012 21:19:20 +0200
   4 Subject: [PATCH 58/84] MIPS: BCM63XX: enable SPI controller for BCM6362
   5
   6 ---
   7  arch/mips/bcm63xx/clk.c                            |    2 ++
   8  arch/mips/bcm63xx/dev-spi.c                        |   11 ++++++++++-
   9  .../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h     |    3 +++
  10  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   16 ++++++++++++++++
  11  4 files changed, 31 insertions(+), 1 deletions(-)
  12
  13 --- a/arch/mips/bcm63xx/clk.c
  14 +++ b/arch/mips/bcm63xx/clk.c
  15 @@ -213,6 +213,8 @@ static void spi_set(struct clk *clk, int
  16                 mask = CKCTL_6348_SPI_EN;
  17         else if (BCMCPU_IS_6358())
  18                 mask = CKCTL_6358_SPI_EN;
  19 +       else if (BCMCPU_IS_6362())
  20 +               mask = CKCTL_6362_SPI_EN;
  21         else
  22                 /* BCMCPU_IS_6368 */
  23                 mask = CKCTL_6368_SPI_EN;
  24 --- a/arch/mips/bcm63xx/dev-spi.c
  25 +++ b/arch/mips/bcm63xx/dev-spi.c
  26 @@ -34,6 +34,10 @@ static const unsigned long bcm6358_regs_
  27         __GEN_SPI_REGS_TABLE(6358)
  28  };
  29
  30 +static const unsigned long bcm6362_regs_spi[] = {
  31 +       __GEN_SPI_REGS_TABLE(6362)
  32 +};
  33 +
  34  static const unsigned long bcm6368_regs_spi[] = {
  35         __GEN_SPI_REGS_TABLE(6368)
  36  };
  37 @@ -49,6 +53,8 @@ static __init void bcm63xx_spi_regs_init
  38                 bcm63xx_regs_spi = bcm6348_regs_spi;
  39         if (BCMCPU_IS_6358())
  40                 bcm63xx_regs_spi = bcm6358_regs_spi;
  41 +       if (BCMCPU_IS_6362())
  42 +               bcm63xx_regs_spi = bcm6362_regs_spi;
  43         if (BCMCPU_IS_6368())
  44                 bcm63xx_regs_spi = bcm6368_regs_spi;
  45  }
  46 @@ -99,6 +105,9 @@ int __init bcm63xx_spi_register(void)
  47         /* Set bus frequency */
  48         spi_pdata.speed_hz = clk_get_rate(periph_clk);
  49
  50 +       if (BCMCPU_IS_6362())
  51 +               spi_pdata.bus_num = 1;
  52 +
  53         spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
  54         spi_resources[0].end = spi_resources[0].start;
  55         spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
  56 @@ -110,7 +119,7 @@ int __init bcm63xx_spi_register(void)
  57                 spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
  58         }
  59
  60 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
  61 +       if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
  62                 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
  63                 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
  64                 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
  65 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
  66 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
  67 @@ -81,6 +81,9 @@ static inline unsigned long bcm63xx_spir
  68  #ifdef CONFIG_BCM63XX_CPU_6358
  69         __GEN_SPI_RSET(6358)
  70  #endif
  71 +#ifdef CONFIG_BCM63XX_CPU_6362
  72 +       __GEN_SPI_RSET(6362)
  73 +#endif
  74  #ifdef CONFIG_BCM63XX_CPU_6368
  75         __GEN_SPI_RSET(6368)
  76  #endif
  77 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  78 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  79 @@ -1393,6 +1393,22 @@
  80  #define SPI_6358_MSG_TAIL              0x709
  81  #define SPI_6358_RX_TAIL               0x70B
  82
  83 +/* BCM 6362 SPI core */
  84 +#define SPI_6362_MSG_CTL               0x00    /* 16-bits register */
  85 +#define SPI_6362_MSG_DATA              0x02
  86 +#define SPI_6362_MSG_DATA_SIZE         0x21e
  87 +#define SPI_6362_RX_DATA               0x400
  88 +#define SPI_6362_RX_DATA_SIZE          0x220
  89 +#define SPI_6362_CMD                   0x700   /* 16-bits register */
  90 +#define SPI_6362_INT_STATUS            0x702
  91 +#define SPI_6362_INT_MASK_ST           0x703
  92 +#define SPI_6362_INT_MASK              0x704
  93 +#define SPI_6362_ST                    0x705
  94 +#define SPI_6362_CLK_CFG               0x706
  95 +#define SPI_6362_FILL_BYTE             0x707
  96 +#define SPI_6362_MSG_TAIL              0x709
  97 +#define SPI_6362_RX_TAIL               0x70B
  98 +
  99  /* BCM 6358 SPI core */
 100  #define SPI_6368_MSG_CTL               0x00    /* 16-bits register */
 101  #define SPI_6368_MSG_CTL_WIDTH         16