1 From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sun, 3 Jul 2011 15:00:38 +0200
4 Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
8 arch/mips/bcm63xx/dev-flash.c | 35 +++++++++++++++++++-
9 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 +
10 2 files changed, 33 insertions(+), 2 deletions(-)
12 --- a/arch/mips/bcm63xx/dev-flash.c
13 +++ b/arch/mips/bcm63xx/dev-flash.c
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/mtd/spi-nor.h>
18 +#include <linux/of.h>
19 +#include <linux/spi/spi.h>
20 +#include <linux/spi/flash.h>
22 #include <bcm63xx_cpu.h>
23 #include <bcm63xx_dev_flash.h>
24 +#include <bcm63xx_dev_hsspi.h>
25 #include <bcm63xx_regs.h>
26 #include <bcm63xx_io.h>
28 @@ -66,6 +70,41 @@ void __init bcm63xx_flash_force_phys_bas
29 mtd_resources[0].end = end;
32 +static struct spi_board_info bcm63xx_spi_flash_info[] = {
37 + .max_speed_hz = 781000,
38 + .modalias = "m25p80",
42 +static void bcm63xx_of_update_spi_flash_speed(struct device_node *np,
43 + unsigned int new_hz)
45 + struct property *max_hz;
48 + max_hz = kzalloc(sizeof(*max_hz) + sizeof(*hz), GFP_KERNEL);
52 + max_hz->name = kstrdup("spi-max-frequency", GFP_KERNEL);
53 + if (!max_hz->name) {
58 + max_hz->value = max_hz + 1;
59 + max_hz->length = sizeof(*hz);
62 + *hz = cpu_to_be32(new_hz);
64 + of_update_property(np, max_hz);
67 static int __init bcm63xx_detect_flash_type(void)
70 @@ -73,9 +112,15 @@ static int __init bcm63xx_detect_flash_t
71 switch (bcm63xx_get_cpu_id()) {
73 /* only support serial flash */
74 + bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
75 return BCM63XX_FLASH_TYPE_SERIAL;
77 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
78 + if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
79 + bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
81 + bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
83 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
84 return BCM63XX_FLASH_TYPE_SERIAL;
86 @@ -94,12 +139,20 @@ static int __init bcm63xx_detect_flash_t
87 return BCM63XX_FLASH_TYPE_SERIAL;
89 val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
90 + if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
91 + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
93 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
95 if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
96 return BCM63XX_FLASH_TYPE_SERIAL;
98 return BCM63XX_FLASH_TYPE_NAND;
100 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
101 + if (val & STRAPBUS_6368_SPI_CLK_FAST)
102 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
104 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
105 case STRAPBUS_6368_BOOT_SEL_NAND:
106 return BCM63XX_FLASH_TYPE_NAND;
107 @@ -110,6 +163,11 @@ static int __init bcm63xx_detect_flash_t
109 case BCM63268_CPU_ID:
110 val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
111 + if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
112 + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
114 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
116 if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
117 return BCM63XX_FLASH_TYPE_SERIAL;
119 @@ -176,6 +234,7 @@ void __init bcm63xx_flash_detect(void)
121 int __init bcm63xx_flash_register(void)
123 + struct device_node *np;
126 switch (flash_type) {
127 @@ -195,8 +254,14 @@ int __init bcm63xx_flash_register(void)
129 return platform_device_register(&mtd_dev);
130 case BCM63XX_FLASH_TYPE_SERIAL:
131 - pr_warn("unsupported serial flash detected\n");
133 + np = of_find_compatible_node(NULL, NULL, "jedec,spi-nor");
135 + bcm63xx_of_update_spi_flash_speed(np, bcm63xx_spi_flash_info[0].max_speed_hz);
141 case BCM63XX_FLASH_TYPE_NAND:
142 pr_warn("unsupported NAND flash detected\n");
144 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
145 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
147 #define GPIO_STRAPBUS_REG 0x40
148 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
149 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
150 +#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6)
151 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
152 #define STRAPBUS_6368_BOOT_SEL_NAND 0
153 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
154 @@ -1564,6 +1565,7 @@
155 #define IDDQ_CTRL_63268_USBH (1 << 4)
157 #define MISC_STRAPBUS_6328_REG 0x240
158 +#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
159 #define STRAPBUS_6328_FCVO_SHIFT 7
160 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
161 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)