target/linux/brcm63xx/patches-4.4/908-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch

   1 From 8725e6135d45bcda346073516c063c94a78e582f Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Fri, 24 Jun 2016 22:17:20 +0200
   4 Subject: [PATCH] pinctrl: add a pincontrol driver for BCM6362
   5
   6 Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual
   7 GPIO pins to the LED controller, to be available by the integrated
   8 wifi, or other functions. It also supports overlay groups, of which
   9 only NAND is documented.
  10
  11 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  12 ---
  13  drivers/pinctrl/bcm63xx/Kconfig           |   7 +
  14  drivers/pinctrl/bcm63xx/Makefile          |   1 +
  15  drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c | 739 ++++++++++++++++++++++++++++++
  16  3 files changed, 747 insertions(+)
  17  create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c
  18
  19 --- a/drivers/pinctrl/bcm63xx/Kconfig
  20 +++ b/drivers/pinctrl/bcm63xx/Kconfig
  21 @@ -22,3 +22,10 @@ config PINCTRL_BCM6358
  22         select PINCONF
  23         select PINCTRL_BCM63XX
  24         select GENERIC_PINCONF
  25 +
  26 +config PINCTRL_BCM6362
  27 +       bool "BCM6362 pincontrol driver" if COMPILE_TEST
  28 +       select PINMUX
  29 +       select PINCONF
  30 +       select PINCTRL_BCM63XX
  31 +       select GENERIC_PINCONF
  32 --- a/drivers/pinctrl/bcm63xx/Makefile
  33 +++ b/drivers/pinctrl/bcm63xx/Makefile
  34 @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_BCM63XX)   += pinctrl
  35  obj-$(CONFIG_PINCTRL_BCM6328)  += pinctrl-bcm6328.o
  36  obj-$(CONFIG_PINCTRL_BCM6348)  += pinctrl-bcm6348.o
  37  obj-$(CONFIG_PINCTRL_BCM6358)  += pinctrl-bcm6358.o
  38 +obj-$(CONFIG_PINCTRL_BCM6362)  += pinctrl-bcm6362.o
  39 --- /dev/null
  40 +++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c
  41 @@ -0,0 +1,739 @@
  42 +/*
  43 + * This file is subject to the terms and conditions of the GNU General Public
  44 + * License.  See the file "COPYING" in the main directory of this archive
  45 + * for more details.
  46 + *
  47 + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
  48 + */
  49 +
  50 +#include <linux/kernel.h>
  51 +#include <linux/spinlock.h>
  52 +#include <linux/bitops.h>
  53 +#include <linux/gpio.h>
  54 +#include <linux/of.h>
  55 +#include <linux/of_gpio.h>
  56 +#include <linux/slab.h>
  57 +#include <linux/platform_device.h>
  58 +
  59 +#include <linux/pinctrl/pinconf.h>
  60 +#include <linux/pinctrl/pinconf-generic.h>
  61 +#include <linux/pinctrl/pinmux.h>
  62 +#include <linux/pinctrl/machine.h>
  63 +
  64 +#include "../core.h"
  65 +#include "../pinctrl-utils.h"
  66 +
  67 +#include "pinctrl-bcm63xx.h"
  68 +
  69 +#define BCM6362_NGPIO  48
  70 +
  71 +/* GPIO_BASEMODE register */
  72 +#define BASEMODE_NAND  BIT(2)
  73 +
  74 +enum bcm6362_pinctrl_reg {
  75 +       BCM6362_LEDCTRL,
  76 +       BCM6362_MODE,
  77 +       BCM6362_CTRL,
  78 +       BCM6362_BASEMODE,
  79 +};
  80 +
  81 +struct bcm6362_pingroup {
  82 +       const char *name;
  83 +       const unsigned * const pins;
  84 +       const unsigned num_pins;
  85 +};
  86 +
  87 +struct bcm6362_function {
  88 +       const char *name;
  89 +       const char * const *groups;
  90 +       const unsigned num_groups;
  91 +
  92 +       enum bcm6362_pinctrl_reg reg;
  93 +       u32 basemode_mask;
  94 +};
  95 +
  96 +struct bcm6362_pinctrl {
  97 +       struct device *dev;
  98 +       struct pinctrl_dev *pctldev;
  99 +       struct pinctrl_desc desc;
 100 +
 101 +       void __iomem *led;
 102 +       void __iomem *mode;
 103 +       void __iomem *ctrl;
 104 +       void __iomem *basemode;
 105 +
 106 +       /* register access lock */
 107 +       spinlock_t lock;
 108 +
 109 +       unsigned long requested[2];
 110 +
 111 +       struct gpio_chip gpio[2];
 112 +};
 113 +
 114 +#define BCM6362_PIN(a, b, mask)                        \
 115 +       {                                       \
 116 +               .number = a,                    \
 117 +               .name = b,                      \
 118 +               .drv_data = (void *)(mask),     \
 119 +       }
 120 +
 121 +static const struct pinctrl_pin_desc bcm6362_pins[] = {
 122 +       PINCTRL_PIN(0, "gpio0"),
 123 +       PINCTRL_PIN(1, "gpio1"),
 124 +       PINCTRL_PIN(2, "gpio2"),
 125 +       PINCTRL_PIN(3, "gpio3"),
 126 +       PINCTRL_PIN(4, "gpio4"),
 127 +       PINCTRL_PIN(5, "gpio5"),
 128 +       PINCTRL_PIN(6, "gpio6"),
 129 +       PINCTRL_PIN(7, "gpio7"),
 130 +       BCM6362_PIN(8, "gpio8", BASEMODE_NAND),
 131 +       PINCTRL_PIN(9, "gpio9"),
 132 +       PINCTRL_PIN(10, "gpio10"),
 133 +       PINCTRL_PIN(11, "gpio11"),
 134 +       BCM6362_PIN(12, "gpio12", BASEMODE_NAND),
 135 +       BCM6362_PIN(13, "gpio13", BASEMODE_NAND),
 136 +       BCM6362_PIN(14, "gpio14", BASEMODE_NAND),
 137 +       BCM6362_PIN(15, "gpio15", BASEMODE_NAND),
 138 +       BCM6362_PIN(16, "gpio16", BASEMODE_NAND),
 139 +       BCM6362_PIN(17, "gpio17", BASEMODE_NAND),
 140 +       BCM6362_PIN(18, "gpio18", BASEMODE_NAND),
 141 +       BCM6362_PIN(19, "gpio19", BASEMODE_NAND),
 142 +       BCM6362_PIN(20, "gpio20", BASEMODE_NAND),
 143 +       BCM6362_PIN(21, "gpio21", BASEMODE_NAND),
 144 +       BCM6362_PIN(22, "gpio22", BASEMODE_NAND),
 145 +       BCM6362_PIN(23, "gpio23", BASEMODE_NAND),
 146 +       PINCTRL_PIN(24, "gpio24"),
 147 +       PINCTRL_PIN(25, "gpio25"),
 148 +       PINCTRL_PIN(26, "gpio26"),
 149 +       BCM6362_PIN(27, "gpio27", BASEMODE_NAND),
 150 +       PINCTRL_PIN(28, "gpio28"),
 151 +       PINCTRL_PIN(29, "gpio29"),
 152 +       PINCTRL_PIN(30, "gpio30"),
 153 +       PINCTRL_PIN(31, "gpio31"),
 154 +       PINCTRL_PIN(32, "gpio32"),
 155 +       PINCTRL_PIN(33, "gpio33"),
 156 +       PINCTRL_PIN(34, "gpio34"),
 157 +       PINCTRL_PIN(35, "gpio35"),
 158 +       PINCTRL_PIN(36, "gpio36"),
 159 +       PINCTRL_PIN(37, "gpio37"),
 160 +       PINCTRL_PIN(38, "gpio38"),
 161 +       PINCTRL_PIN(39, "gpio39"),
 162 +       PINCTRL_PIN(40, "gpio40"),
 163 +       PINCTRL_PIN(41, "gpio41"),
 164 +       PINCTRL_PIN(42, "gpio42"),
 165 +       PINCTRL_PIN(43, "gpio43"),
 166 +       PINCTRL_PIN(44, "gpio44"),
 167 +       PINCTRL_PIN(45, "gpio45"),
 168 +       PINCTRL_PIN(46, "gpio46"),
 169 +       PINCTRL_PIN(47, "gpio47"),
 170 +};
 171 +
 172 +static unsigned gpio0_pins[] = { 0 };
 173 +static unsigned gpio1_pins[] = { 1 };
 174 +static unsigned gpio2_pins[] = { 2 };
 175 +static unsigned gpio3_pins[] = { 3 };
 176 +static unsigned gpio4_pins[] = { 4 };
 177 +static unsigned gpio5_pins[] = { 5 };
 178 +static unsigned gpio6_pins[] = { 6 };
 179 +static unsigned gpio7_pins[] = { 7 };
 180 +static unsigned gpio8_pins[] = { 8 };
 181 +static unsigned gpio9_pins[] = { 9 };
 182 +static unsigned gpio10_pins[] = { 10 };
 183 +static unsigned gpio11_pins[] = { 11 };
 184 +static unsigned gpio12_pins[] = { 12 };
 185 +static unsigned gpio13_pins[] = { 13 };
 186 +static unsigned gpio14_pins[] = { 14 };
 187 +static unsigned gpio15_pins[] = { 15 };
 188 +static unsigned gpio16_pins[] = { 16 };
 189 +static unsigned gpio17_pins[] = { 17 };
 190 +static unsigned gpio18_pins[] = { 18 };
 191 +static unsigned gpio19_pins[] = { 19 };
 192 +static unsigned gpio20_pins[] = { 20 };
 193 +static unsigned gpio21_pins[] = { 21 };
 194 +static unsigned gpio22_pins[] = { 22 };
 195 +static unsigned gpio23_pins[] = { 23 };
 196 +static unsigned gpio24_pins[] = { 24 };
 197 +static unsigned gpio25_pins[] = { 25 };
 198 +static unsigned gpio26_pins[] = { 26 };
 199 +static unsigned gpio27_pins[] = { 27 };
 200 +static unsigned gpio28_pins[] = { 28 };
 201 +static unsigned gpio29_pins[] = { 29 };
 202 +static unsigned gpio30_pins[] = { 30 };
 203 +static unsigned gpio31_pins[] = { 31 };
 204 +static unsigned gpio32_pins[] = { 32 };
 205 +static unsigned gpio33_pins[] = { 33 };
 206 +static unsigned gpio34_pins[] = { 34 };
 207 +static unsigned gpio35_pins[] = { 35 };
 208 +static unsigned gpio36_pins[] = { 36 };
 209 +static unsigned gpio37_pins[] = { 37 };
 210 +static unsigned gpio38_pins[] = { 38 };
 211 +static unsigned gpio39_pins[] = { 39 };
 212 +static unsigned gpio40_pins[] = { 40 };
 213 +static unsigned gpio41_pins[] = { 41 };
 214 +static unsigned gpio42_pins[] = { 42 };
 215 +static unsigned gpio43_pins[] = { 43 };
 216 +static unsigned gpio44_pins[] = { 44 };
 217 +static unsigned gpio45_pins[] = { 45 };
 218 +static unsigned gpio46_pins[] = { 46 };
 219 +static unsigned gpio47_pins[] = { 47 };
 220 +
 221 +static unsigned nand_grp_pins[] = {
 222 +       8, 12, 13, 14, 15, 16, 17,
 223 +       18, 19, 20, 21, 22, 23, 27,
 224 +};
 225 +
 226 +#define BCM6362_GROUP(n)                               \
 227 +       {                                               \
 228 +               .name = #n,                             \
 229 +               .pins = n##_pins,                       \
 230 +               .num_pins = ARRAY_SIZE(n##_pins),       \
 231 +       }
 232 +
 233 +static struct bcm6362_pingroup bcm6362_groups[] = {
 234 +       BCM6362_GROUP(gpio0),
 235 +       BCM6362_GROUP(gpio1),
 236 +       BCM6362_GROUP(gpio2),
 237 +       BCM6362_GROUP(gpio3),
 238 +       BCM6362_GROUP(gpio4),
 239 +       BCM6362_GROUP(gpio5),
 240 +       BCM6362_GROUP(gpio6),
 241 +       BCM6362_GROUP(gpio7),
 242 +       BCM6362_GROUP(gpio8),
 243 +       BCM6362_GROUP(gpio9),
 244 +       BCM6362_GROUP(gpio10),
 245 +       BCM6362_GROUP(gpio11),
 246 +       BCM6362_GROUP(gpio12),
 247 +       BCM6362_GROUP(gpio13),
 248 +       BCM6362_GROUP(gpio14),
 249 +       BCM6362_GROUP(gpio15),
 250 +       BCM6362_GROUP(gpio16),
 251 +       BCM6362_GROUP(gpio17),
 252 +       BCM6362_GROUP(gpio18),
 253 +       BCM6362_GROUP(gpio19),
 254 +       BCM6362_GROUP(gpio20),
 255 +       BCM6362_GROUP(gpio21),
 256 +       BCM6362_GROUP(gpio22),
 257 +       BCM6362_GROUP(gpio23),
 258 +       BCM6362_GROUP(gpio24),
 259 +       BCM6362_GROUP(gpio25),
 260 +       BCM6362_GROUP(gpio26),
 261 +       BCM6362_GROUP(gpio27),
 262 +       BCM6362_GROUP(gpio28),
 263 +       BCM6362_GROUP(gpio29),
 264 +       BCM6362_GROUP(gpio30),
 265 +       BCM6362_GROUP(gpio31),
 266 +       BCM6362_GROUP(gpio32),
 267 +       BCM6362_GROUP(gpio33),
 268 +       BCM6362_GROUP(gpio34),
 269 +       BCM6362_GROUP(gpio35),
 270 +       BCM6362_GROUP(gpio36),
 271 +       BCM6362_GROUP(gpio37),
 272 +       BCM6362_GROUP(gpio38),
 273 +       BCM6362_GROUP(gpio39),
 274 +       BCM6362_GROUP(gpio40),
 275 +       BCM6362_GROUP(gpio41),
 276 +       BCM6362_GROUP(gpio42),
 277 +       BCM6362_GROUP(gpio43),
 278 +       BCM6362_GROUP(gpio44),
 279 +       BCM6362_GROUP(gpio45),
 280 +       BCM6362_GROUP(gpio46),
 281 +       BCM6362_GROUP(gpio47),
 282 +       BCM6362_GROUP(nand_grp),
 283 +};
 284 +
 285 +static const char * const led_groups[] = {
 286 +       "gpio0",
 287 +       "gpio1",
 288 +       "gpio2",
 289 +       "gpio3",
 290 +       "gpio4",
 291 +       "gpio5",
 292 +       "gpio6",
 293 +       "gpio7",
 294 +       "gpio8",
 295 +       "gpio9",
 296 +       "gpio10",
 297 +       "gpio11",
 298 +       "gpio12",
 299 +       "gpio13",
 300 +       "gpio14",
 301 +       "gpio15",
 302 +       "gpio16",
 303 +       "gpio17",
 304 +       "gpio18",
 305 +       "gpio19",
 306 +       "gpio20",
 307 +       "gpio21",
 308 +       "gpio22",
 309 +       "gpio23",
 310 +};
 311 +
 312 +static const char * const usb_device_led_groups[] = {
 313 +       "gpio0",
 314 +};
 315 +
 316 +static const char * const sys_irq_groups[] = {
 317 +       "gpio1",
 318 +};
 319 +
 320 +static const char * const serial_led_clk_groups[] = {
 321 +       "gpio2",
 322 +};
 323 +
 324 +static const char * const serial_led_data_groups[] = {
 325 +       "gpio3",
 326 +};
 327 +
 328 +static const char * const robosw_led_data_groups[] = {
 329 +       "gpio4",
 330 +};
 331 +
 332 +static const char * const robosw_led_clk_groups[] = {
 333 +       "gpio5",
 334 +};
 335 +
 336 +static const char * const robosw_led0_groups[] = {
 337 +       "gpio6",
 338 +};
 339 +
 340 +static const char * const robosw_led1_groups[] = {
 341 +       "gpio7",
 342 +};
 343 +
 344 +static const char * const inet_led_groups[] = {
 345 +       "gpio8",
 346 +};
 347 +
 348 +static const char * const spi_cs2_groups[] = {
 349 +       "gpio9",
 350 +};
 351 +
 352 +static const char * const spi_cs3_groups[] = {
 353 +       "gpio10",
 354 +};
 355 +
 356 +static const char * const ntr_pulse_groups[] = {
 357 +       "gpio11",
 358 +};
 359 +
 360 +static const char * const uart1_scts_groups[] = {
 361 +       "gpio12",
 362 +};
 363 +
 364 +static const char * const uart1_srts_groups[] = {
 365 +       "gpio13",
 366 +};
 367 +
 368 +static const char * const uart1_sdin_groups[] = {
 369 +       "gpio14",
 370 +};
 371 +
 372 +static const char * const uart1_sdout_groups[] = {
 373 +       "gpio15",
 374 +};
 375 +
 376 +static const char * const adsl_spi_miso_groups[] = {
 377 +       "gpio16",
 378 +};
 379 +
 380 +static const char * const adsl_spi_mosi_groups[] = {
 381 +       "gpio17",
 382 +};
 383 +
 384 +static const char * const adsl_spi_clk_groups[] = {
 385 +       "gpio18",
 386 +};
 387 +
 388 +static const char * const adsl_spi_cs_groups[] = {
 389 +       "gpio19",
 390 +};
 391 +
 392 +static const char * const ephy0_led_groups[] = {
 393 +       "gpio20",
 394 +};
 395 +
 396 +static const char * const ephy1_led_groups[] = {
 397 +       "gpio21",
 398 +};
 399 +
 400 +static const char * const ephy2_led_groups[] = {
 401 +       "gpio22",
 402 +};
 403 +
 404 +static const char * const ephy3_led_groups[] = {
 405 +       "gpio23",
 406 +};
 407 +
 408 +static const char * const ext_irq0_groups[] = {
 409 +       "gpio24",
 410 +};
 411 +
 412 +static const char * const ext_irq1_groups[] = {
 413 +       "gpio25",
 414 +};
 415 +
 416 +static const char * const ext_irq2_groups[] = {
 417 +       "gpio26",
 418 +};
 419 +
 420 +static const char * const ext_irq3_groups[] = {
 421 +       "gpio27",
 422 +};
 423 +
 424 +static const char * const wifi_groups[] = {
 425 +       "gpio32",
 426 +       "gpio33",
 427 +       "gpio34",
 428 +       "gpio35",
 429 +       "gpio36",
 430 +       "gpio37",
 431 +       "gpio38",
 432 +       "gpio39",
 433 +       "gpio40",
 434 +       "gpio41",
 435 +       "gpio42",
 436 +       "gpio43",
 437 +       "gpio44",
 438 +       "gpio45",
 439 +       "gpio46",
 440 +       "gpio47",
 441 +};
 442 +
 443 +static const char * const nand_groups[] = {
 444 +       "nand_grp",
 445 +};
 446 +
 447 +#define BCM6362_LED_FUN(n)                             \
 448 +       {                                               \
 449 +               .name = #n,                             \
 450 +               .groups = n##_groups,                   \
 451 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 452 +               .reg = BCM6362_LEDCTRL,                 \
 453 +       }
 454 +
 455 +#define BCM6362_MODE_FUN(n)                            \
 456 +       {                                               \
 457 +               .name = #n,                             \
 458 +               .groups = n##_groups,                   \
 459 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 460 +               .reg = BCM6362_MODE,                    \
 461 +       }
 462 +
 463 +#define BCM6362_CTRL_FUN(n)                            \
 464 +       {                                               \
 465 +               .name = #n,                             \
 466 +               .groups = n##_groups,                   \
 467 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 468 +               .reg = BCM6362_CTRL,                    \
 469 +       }
 470 +
 471 +#define BCM6362_BASEMODE_FUN(n, mask)                  \
 472 +       {                                               \
 473 +               .name = #n,                             \
 474 +               .groups = n##_groups,                   \
 475 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 476 +               .reg = BCM6362_BASEMODE,                \
 477 +               .basemode_mask = (mask),                \
 478 +       }
 479 +
 480 +static const struct bcm6362_function bcm6362_funcs[] = {
 481 +       BCM6362_LED_FUN(led),
 482 +       BCM6362_MODE_FUN(usb_device_led),
 483 +       BCM6362_MODE_FUN(sys_irq),
 484 +       BCM6362_MODE_FUN(serial_led_clk),
 485 +       BCM6362_MODE_FUN(serial_led_data),
 486 +       BCM6362_MODE_FUN(robosw_led_data),
 487 +       BCM6362_MODE_FUN(robosw_led_clk),
 488 +       BCM6362_MODE_FUN(robosw_led0),
 489 +       BCM6362_MODE_FUN(robosw_led1),
 490 +       BCM6362_MODE_FUN(inet_led),
 491 +       BCM6362_MODE_FUN(spi_cs2),
 492 +       BCM6362_MODE_FUN(spi_cs3),
 493 +       BCM6362_MODE_FUN(ntr_pulse),
 494 +       BCM6362_MODE_FUN(uart1_scts),
 495 +       BCM6362_MODE_FUN(uart1_srts),
 496 +       BCM6362_MODE_FUN(uart1_sdin),
 497 +       BCM6362_MODE_FUN(uart1_sdout),
 498 +       BCM6362_MODE_FUN(adsl_spi_miso),
 499 +       BCM6362_MODE_FUN(adsl_spi_mosi),
 500 +       BCM6362_MODE_FUN(adsl_spi_clk),
 501 +       BCM6362_MODE_FUN(adsl_spi_cs),
 502 +       BCM6362_MODE_FUN(ephy0_led),
 503 +       BCM6362_MODE_FUN(ephy1_led),
 504 +       BCM6362_MODE_FUN(ephy2_led),
 505 +       BCM6362_MODE_FUN(ephy3_led),
 506 +       BCM6362_MODE_FUN(ext_irq0),
 507 +       BCM6362_MODE_FUN(ext_irq1),
 508 +       BCM6362_MODE_FUN(ext_irq2),
 509 +       BCM6362_MODE_FUN(ext_irq3),
 510 +       BCM6362_CTRL_FUN(wifi),
 511 +       BCM6362_BASEMODE_FUN(nand, BASEMODE_NAND),
 512 +};
 513 +
 514 +static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
 515 +{
 516 +       return ARRAY_SIZE(bcm6362_groups);
 517 +}
 518 +
 519 +static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 520 +                                                 unsigned group)
 521 +{
 522 +       return bcm6362_groups[group].name;
 523 +}
 524 +
 525 +static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 526 +                                         unsigned group, const unsigned **pins,
 527 +                                         unsigned *num_pins)
 528 +{
 529 +       *pins = bcm6362_groups[group].pins;
 530 +       *num_pins = bcm6362_groups[group].num_pins;
 531 +
 532 +       return 0;
 533 +}
 534 +
 535 +static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
 536 +{
 537 +       return ARRAY_SIZE(bcm6362_funcs);
 538 +}
 539 +
 540 +static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 541 +                                                unsigned selector)
 542 +{
 543 +       return bcm6362_funcs[selector].name;
 544 +}
 545 +
 546 +static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev,
 547 +                                     unsigned selector,
 548 +                                     const char * const **groups,
 549 +                                     unsigned * const num_groups)
 550 +{
 551 +       *groups = bcm6362_funcs[selector].groups;
 552 +       *num_groups = bcm6362_funcs[selector].num_groups;
 553 +
 554 +       return 0;
 555 +}
 556 +
 557 +static void bcm6362_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 558 +                                        struct seq_file *s,
 559 +                                        unsigned offset)
 560 +{
 561 +       seq_printf(s, " %s", dev_name(pctldev->dev));
 562 +}
 563 +
 564 +static void bcm6362_rmw_mux(struct bcm6362_pinctrl *pctl, void __iomem *reg,
 565 +                           u32 mask, u32 val)
 566 +{
 567 +       unsigned long flags;
 568 +       u32 tmp;
 569 +
 570 +       spin_lock_irqsave(&pctl->lock, flags);
 571 +       tmp = __raw_readl(reg);
 572 +       tmp &= ~mask;
 573 +       tmp |= val & mask;
 574 +       __raw_writel(tmp, reg);
 575 +
 576 +       spin_unlock_irqrestore(&pctl->lock, flags);
 577 +}
 578 +
 579 +static void bcm6362_set_gpio(struct bcm6362_pinctrl *pctl, unsigned pin)
 580 +{
 581 +       const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];
 582 +       u32 mask = BIT(pin % 32);
 583 +
 584 +       if (desc->drv_data)
 585 +               bcm6362_rmw_mux(pctl, pctl->basemode, (u32)desc->drv_data, 0);
 586 +
 587 +       if (pin < 32) {
 588 +               /* base mode 0 => gpio 1 => mux function */
 589 +               bcm6362_rmw_mux(pctl, pctl->mode, mask, 0);
 590 +
 591 +               /* pins 0-23 might be muxed to led */
 592 +               if (pin < 24)
 593 +                       bcm6362_rmw_mux(pctl, pctl->led, mask, 0);
 594 +       } else {
 595 +               /* ctrl reg 0 => wifi function 1 => gpio */
 596 +               bcm6362_rmw_mux(pctl, pctl->ctrl, mask, mask);
 597 +       }
 598 +}
 599 +
 600 +static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 601 +                                  unsigned selector, unsigned group)
 602 +{
 603 +       struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 604 +       const struct bcm6362_pingroup *grp = &bcm6362_groups[group];
 605 +       const struct bcm6362_function *f = &bcm6362_funcs[selector];
 606 +       unsigned i;
 607 +       void __iomem *reg;
 608 +       u32 val, mask;
 609 +
 610 +       for (i = 0; i < grp->num_pins; i++)
 611 +               bcm6362_set_gpio(pctl, grp->pins[i]);
 612 +
 613 +       switch (f->reg) {
 614 +       case BCM6362_LEDCTRL:
 615 +               reg = pctl->led;
 616 +               mask = BIT(grp->pins[0]);
 617 +               val = BIT(grp->pins[0]);
 618 +               break;
 619 +       case BCM6362_MODE:
 620 +               reg = pctl->ctrl;
 621 +               mask = BIT(grp->pins[0]);
 622 +               val = BIT(grp->pins[0]);
 623 +               break;
 624 +       case BCM6362_CTRL:
 625 +               reg = pctl->ctrl;
 626 +               mask = BIT(grp->pins[0]);
 627 +               val = 0;
 628 +               break;
 629 +       case BCM6362_BASEMODE:
 630 +               reg = pctl->basemode;
 631 +               mask = f->basemode_mask;
 632 +               val = f->basemode_mask;
 633 +               break;
 634 +       default:
 635 +               WARN_ON(1);
 636 +               return -EINVAL;
 637 +       }
 638 +
 639 +       bcm6362_rmw_mux(pctl, reg, mask, val);
 640 +
 641 +       return 0;
 642 +}
 643 +
 644 +static int bcm6362_pinctrl_request(struct pinctrl_dev *pctldev,
 645 +                                  unsigned offset)
 646 +{
 647 +       struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 648 +
 649 +       if (test_and_set_bit(offset, pctl->requested))
 650 +               return -EBUSY;
 651 +
 652 +       return 0;
 653 +}
 654 +
 655 +static int bcm6362_pinctrl_free(struct pinctrl_dev *pctldev,
 656 +                               unsigned offset)
 657 +{
 658 +       struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 659 +
 660 +       clear_bit(offset, pctl->requested);
 661 +
 662 +       return 0;
 663 +}
 664 +
 665 +static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev,
 666 +                                      struct pinctrl_gpio_range *range,
 667 +                                      unsigned offset)
 668 +{
 669 +       struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 670 +
 671 +       if (test_and_set_bit(offset, pctl->requested))
 672 +               return -EBUSY;
 673 +
 674 +       /* disable all functions using this pin */
 675 +       bcm6362_set_gpio(pctl, offset);
 676 +
 677 +       return 0;
 678 +}
 679 +
 680 +static void bcm6362_gpio_disable_free(struct pinctrl_dev *pctldev,
 681 +                                     struct pinctrl_gpio_range *range,
 682 +                                     unsigned offset)
 683 +{
 684 +       struct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 685 +
 686 +       clear_bit(offset, pctl->requested);
 687 +}
 688 +
 689 +static struct pinctrl_ops bcm6362_pctl_ops = {
 690 +       .get_groups_count       = bcm6362_pinctrl_get_group_count,
 691 +       .get_group_name         = bcm6362_pinctrl_get_group_name,
 692 +       .get_group_pins         = bcm6362_pinctrl_get_group_pins,
 693 +#ifdef CONFIG_OF
 694 +       .dt_node_to_map         = pinconf_generic_dt_node_to_map_pin,
 695 +       .dt_free_map            = pinctrl_utils_dt_free_map,
 696 +#endif
 697 +       .pin_dbg_show           = bcm6362_pinctrl_pin_dbg_show,
 698 +};
 699 +
 700 +static struct pinmux_ops bcm6362_pmx_ops = {
 701 +       .request                = bcm6362_pinctrl_request,
 702 +       .free                   = bcm6362_pinctrl_free,
 703 +       .get_functions_count    = bcm6362_pinctrl_get_func_count,
 704 +       .get_function_name      = bcm6362_pinctrl_get_func_name,
 705 +       .get_function_groups    = bcm6362_pinctrl_get_groups,
 706 +       .set_mux                = bcm6362_pinctrl_set_mux,
 707 +       .gpio_request_enable    = bcm6362_gpio_request_enable,
 708 +       .gpio_disable_free      = bcm6362_gpio_disable_free,
 709 +};
 710 +
 711 +static int bcm6362_pinctrl_probe(struct platform_device *pdev)
 712 +{
 713 +       struct bcm6362_pinctrl *pctl;
 714 +       struct resource *res;
 715 +       void __iomem *led, *mode, *ctrl, *basemode;
 716 +
 717 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "led");
 718 +       led = devm_ioremap_resource(&pdev->dev, res);
 719 +       if (IS_ERR(led))
 720 +               return PTR_ERR(led);
 721 +
 722 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
 723 +       mode = devm_ioremap_resource(&pdev->dev, res);
 724 +       if (IS_ERR(mode))
 725 +               return PTR_ERR(mode);
 726 +
 727 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
 728 +       ctrl = devm_ioremap_resource(&pdev->dev, res);
 729 +       if (IS_ERR(ctrl))
 730 +               return PTR_ERR(ctrl);
 731 +
 732 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "basemode");
 733 +       basemode = devm_ioremap_resource(&pdev->dev, res);
 734 +       if (IS_ERR(basemode))
 735 +               return PTR_ERR(basemode);
 736 +
 737 +       pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 738 +       if (!pctl)
 739 +               return -ENOMEM;
 740 +
 741 +       spin_lock_init(&pctl->lock);
 742 +
 743 +       pctl->led = led;
 744 +       pctl->mode = mode;
 745 +       pctl->ctrl = ctrl;
 746 +       pctl->basemode = basemode;
 747 +
 748 +       pctl->desc.name = dev_name(&pdev->dev);
 749 +       pctl->desc.owner = THIS_MODULE;
 750 +       pctl->desc.pctlops = &bcm6362_pctl_ops;
 751 +       pctl->desc.pmxops = &bcm6362_pmx_ops;
 752 +       pctl->dev = &pdev->dev;
 753 +
 754 +       pctl->desc.npins = ARRAY_SIZE(bcm6362_pins);
 755 +       pctl->desc.pins = bcm6362_pins;
 756 +
 757 +       platform_set_drvdata(pdev, pctl);
 758 +
 759 +       pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
 760 +                                                pctl->gpio, BCM6362_NGPIO);
 761 +       if (IS_ERR(pctl->pctldev))
 762 +               return PTR_ERR(pctl->pctldev);
 763 +
 764 +       return 0;
 765 +}
 766 +
 767 +static const struct of_device_id bcm6362_pinctrl_match[] = {
 768 +       { .compatible = "brcm,bcm6362-pinctrl", },
 769 +       { },
 770 +};
 771 +
 772 +static struct platform_driver bcm6362_pinctrl_driver = {
 773 +       .probe = bcm6362_pinctrl_probe,
 774 +       .driver = {
 775 +               .name = "bcm6362-pinctrl",
 776 +               .of_match_table = bcm6362_pinctrl_match,
 777 +       },
 778 +};
 779 +
 780 +builtin_platform_driver(bcm6362_pinctrl_driver);