2 * Gateworks Corporation Laguna Platform
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
24 #include <linux/gpio.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/leds.h>
33 #include <linux/i2c.h>
34 #include <linux/platform_data/at24.h>
35 #include <linux/platform_data/pca953x.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/if_ether.h>
39 #include <linux/pps-gpio.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/clk-provider.h>
43 #include <linux/clkdev.h>
44 #include <linux/platform_data/cns3xxx.h>
45 #include <asm/setup.h>
46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/time.h>
50 #include <mach/gpio.h>
56 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
59 #define ETH0_LOAD BIT(0)
60 #define ETH1_LOAD BIT(1)
61 #define ETH2_LOAD BIT(2)
62 #define SATA0_LOAD BIT(3)
63 #define SATA1_LOAD BIT(4)
64 #define PCM_LOAD BIT(5)
65 #define I2S_LOAD BIT(6)
66 #define SPI0_LOAD BIT(7)
67 #define SPI1_LOAD BIT(8)
68 #define PCIE0_LOAD BIT(9)
69 #define PCIE1_LOAD BIT(10)
70 #define USB0_LOAD BIT(11)
71 #define USB1_LOAD BIT(12)
72 #define USB1_ROUTE BIT(13)
73 #define SD_LOAD BIT(14)
74 #define UART0_LOAD BIT(15)
75 #define UART1_LOAD BIT(16)
76 #define UART2_LOAD BIT(17)
77 #define MPCI0_LOAD BIT(18)
78 #define MPCI1_LOAD BIT(19)
79 #define MPCI2_LOAD BIT(20)
80 #define MPCI3_LOAD BIT(21)
81 #define FP_BUT_LOAD BIT(22)
82 #define FP_BUT_HEADER_LOAD BIT(23)
83 #define FP_LED_LOAD BIT(24)
84 #define FP_LED_HEADER_LOAD BIT(25)
85 #define FP_TAMPER_LOAD BIT(26)
86 #define HEADER_33V_LOAD BIT(27)
87 #define SATA_POWER_LOAD BIT(28)
88 #define FP_POWER_LOAD BIT(29)
89 #define GPIO_HEADER_LOAD BIT(30)
90 #define GSP_BAT_LOAD BIT(31)
93 #define FAN_LOAD BIT(0)
94 #define SPI_FLASH_LOAD BIT(1)
95 #define NOR_FLASH_LOAD BIT(2)
96 #define GPS_LOAD BIT(3)
97 #define SUPPLY_5V_LOAD BIT(6)
98 #define SUPPLY_33V_LOAD BIT(7)
100 struct laguna_board_info
{
108 static struct laguna_board_info laguna_info __initdata
;
113 static struct mtd_partition laguna_nor_partitions
[] = {
118 .mask_flags
= MTD_WRITEABLE
,
126 .offset
= SZ_256K
+ SZ_128K
,
129 .size
= SZ_16M
- SZ_256K
- SZ_128K
- SZ_2M
,
130 .offset
= SZ_256K
+ SZ_128K
+ SZ_2M
,
134 static struct physmap_flash_data laguna_nor_pdata
= {
136 .parts
= laguna_nor_partitions
,
137 .nr_parts
= ARRAY_SIZE(laguna_nor_partitions
),
140 static struct resource laguna_nor_res
= {
141 .start
= CNS3XXX_FLASH_BASE
,
142 .end
= CNS3XXX_FLASH_BASE
+ SZ_128M
- 1,
143 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_32BIT
,
146 static struct platform_device laguna_nor_pdev
= {
147 .name
= "physmap-flash",
149 .resource
= &laguna_nor_res
,
152 .platform_data
= &laguna_nor_pdata
,
159 static struct mtd_partition laguna_spi_partitions
[] = {
164 .mask_flags
= MTD_WRITEABLE
,
171 .size
= SZ_1M
+ SZ_512K
,
175 .size
= SZ_16M
- SZ_2M
,
180 static struct flash_platform_data laguna_spi_pdata
= {
181 .parts
= laguna_spi_partitions
,
182 .nr_parts
= ARRAY_SIZE(laguna_spi_partitions
),
185 static struct spi_board_info __initdata laguna_spi_devices
[] = {
187 .modalias
= "m25p80",
188 .platform_data
= &laguna_spi_pdata
,
189 .max_speed_hz
= 50000000,
195 static struct resource laguna_spi_resource
= {
196 .start
= CNS3XXX_SSP_BASE
+ 0x40,
197 .end
= CNS3XXX_SSP_BASE
+ 0x6f,
198 .flags
= IORESOURCE_MEM
,
201 static struct platform_device laguna_spi_controller
= {
202 .name
= "cns3xxx_spi",
203 .resource
= &laguna_spi_resource
,
210 static struct gpio_led laguna_gpio_leds
[] = {
212 .name
= "user1", /* Green Led */
216 .name
= "user2", /* Red Led */
220 .name
= "pwr1", /* Green Led */
224 .name
= "pwr2", /* Yellow Led */
228 .name
= "txd1", /* Green Led */
232 .name
= "txd2", /* Yellow Led */
236 .name
= "rxd1", /* Green Led */
240 .name
= "rxd2", /* Yellow Led */
244 .name
= "ser1", /* Green Led */
248 .name
= "ser2", /* Yellow Led */
252 .name
= "enet1", /* Green Led */
256 .name
= "enet2", /* Yellow Led */
260 .name
= "sig1_1", /* Green Led */
264 .name
= "sig1_2", /* Yellow Led */
268 .name
= "sig2_1", /* Green Led */
272 .name
= "sig2_2", /* Yellow Led */
276 .name
= "sig3_1", /* Green Led */
280 .name
= "sig3_2", /* Yellow Led */
284 .name
= "net1", /*Green Led */
288 .name
= "net2", /* Red Led */
292 .name
= "mod1", /* Green Led */
296 .name
= "mod2", /* Red Led */
302 static struct gpio_led_platform_data laguna_gpio_leds_data
= {
304 .leds
= laguna_gpio_leds
,
307 static struct platform_device laguna_gpio_leds_device
= {
310 .dev
.platform_data
= &laguna_gpio_leds_data
,
316 static struct cns3xxx_plat_info laguna_net_data
= {
325 static struct resource laguna_net_resource
[] = {
328 .start
= CNS3XXX_SWITCH_BASE
,
329 .end
= CNS3XXX_SWITCH_BASE
+ SZ_4K
- 1,
330 .flags
= IORESOURCE_MEM
333 .start
= IRQ_CNS3XXX_SW_R0RXC
,
334 .end
= IRQ_CNS3XXX_SW_R0RXC
,
335 .flags
= IORESOURCE_IRQ
338 .start
= IRQ_CNS3XXX_SW_STATUS
,
339 .end
= IRQ_CNS3XXX_SW_STATUS
,
340 .flags
= IORESOURCE_IRQ
344 static u64 laguna_net_dmamask
= DMA_BIT_MASK(32);
345 static struct platform_device laguna_net_device
= {
346 .name
= "cns3xxx_eth",
348 .resource
= laguna_net_resource
,
349 .num_resources
= ARRAY_SIZE(laguna_net_resource
),
351 .dma_mask
= &laguna_net_dmamask
,
352 .coherent_dma_mask
= DMA_BIT_MASK(32),
353 .platform_data
= &laguna_net_data
,
360 static void __init
laguna_early_serial_setup(void)
362 #ifdef CONFIG_SERIAL_8250_CONSOLE
363 static struct uart_port laguna_serial_port
= {
364 .membase
= (void __iomem
*)CNS3XXX_UART0_BASE_VIRT
,
365 .mapbase
= CNS3XXX_UART0_BASE
,
366 .irq
= IRQ_CNS3XXX_UART0
,
368 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
,
376 early_serial_setup(&laguna_serial_port
);
380 static struct resource laguna_uart_resources
[] = {
382 .start
= CNS3XXX_UART0_BASE
,
383 .end
= CNS3XXX_UART0_BASE
+ SZ_4K
- 1,
384 .flags
= IORESOURCE_MEM
386 .start
= CNS3XXX_UART2_BASE
,
387 .end
= CNS3XXX_UART2_BASE
+ SZ_4K
- 1,
388 .flags
= IORESOURCE_MEM
390 .start
= CNS3XXX_UART2_BASE
,
391 .end
= CNS3XXX_UART2_BASE
+ SZ_4K
- 1,
392 .flags
= IORESOURCE_MEM
396 static struct plat_serial8250_port laguna_uart_data
[] = {
398 .mapbase
= (CNS3XXX_UART0_BASE
),
399 .irq
= IRQ_CNS3XXX_UART0
,
401 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
| UPF_NO_TXEN_TEST
| UPF_IOREMAP
,
406 .mapbase
= (CNS3XXX_UART1_BASE
),
407 .irq
= IRQ_CNS3XXX_UART1
,
409 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
| UPF_NO_TXEN_TEST
| UPF_IOREMAP
,
414 .mapbase
= (CNS3XXX_UART2_BASE
),
415 .irq
= IRQ_CNS3XXX_UART2
,
417 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
| UPF_NO_TXEN_TEST
| UPF_IOREMAP
,
425 static struct platform_device laguna_uart
= {
426 .name
= "serial8250",
427 .id
= PLAT8250_DEV_PLATFORM
,
428 .dev
.platform_data
= laguna_uart_data
,
430 .resource
= laguna_uart_resources
436 static struct resource cns3xxx_usb_ehci_resources
[] = {
438 .start
= CNS3XXX_USB_BASE
,
439 .end
= CNS3XXX_USB_BASE
+ SZ_16M
- 1,
440 .flags
= IORESOURCE_MEM
,
443 .start
= IRQ_CNS3XXX_USB_EHCI
,
444 .flags
= IORESOURCE_IRQ
,
448 static u64 cns3xxx_usb_ehci_dma_mask
= DMA_BIT_MASK(32);
450 static int csn3xxx_usb_power_on(struct platform_device
*pdev
)
453 * EHCI and OHCI share the same clock and power,
454 * resetting twice would cause the 1st controller been reset.
455 * Therefore only do power up at the first up device, and
456 * power down at the last down device.
458 * Set USB AHB INCR length to 16
460 if (atomic_inc_return(&usb_pwr_ref
) == 1) {
461 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB
);
462 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST
);
463 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST
);
464 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG
) | (0X2 << 24)),
465 MISC_CHIP_CONFIG_REG
);
471 static void csn3xxx_usb_power_off(struct platform_device
*pdev
)
474 * EHCI and OHCI share the same clock and power,
475 * resetting twice would cause the 1st controller been reset.
476 * Therefore only do power up at the first up device, and
477 * power down at the last down device.
479 if (atomic_dec_return(&usb_pwr_ref
) == 0)
480 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST
);
483 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata
= {
484 .power_on
= csn3xxx_usb_power_on
,
485 .power_off
= csn3xxx_usb_power_off
,
488 static struct platform_device cns3xxx_usb_ehci_device
= {
489 .name
= "ehci-platform",
490 .num_resources
= ARRAY_SIZE(cns3xxx_usb_ehci_resources
),
491 .resource
= cns3xxx_usb_ehci_resources
,
493 .dma_mask
= &cns3xxx_usb_ehci_dma_mask
,
494 .coherent_dma_mask
= DMA_BIT_MASK(32),
495 .platform_data
= &cns3xxx_usb_ehci_pdata
,
499 static struct resource cns3xxx_usb_ohci_resources
[] = {
501 .start
= CNS3XXX_USB_OHCI_BASE
,
502 .end
= CNS3XXX_USB_OHCI_BASE
+ SZ_16M
- 1,
503 .flags
= IORESOURCE_MEM
,
506 .start
= IRQ_CNS3XXX_USB_OHCI
,
507 .flags
= IORESOURCE_IRQ
,
511 static u64 cns3xxx_usb_ohci_dma_mask
= DMA_BIT_MASK(32);
513 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata
= {
515 .power_on
= csn3xxx_usb_power_on
,
516 .power_off
= csn3xxx_usb_power_off
,
519 static struct platform_device cns3xxx_usb_ohci_device
= {
520 .name
= "ohci-platform",
521 .num_resources
= ARRAY_SIZE(cns3xxx_usb_ohci_resources
),
522 .resource
= cns3xxx_usb_ohci_resources
,
524 .dma_mask
= &cns3xxx_usb_ohci_dma_mask
,
525 .coherent_dma_mask
= DMA_BIT_MASK(32),
526 .platform_data
= &cns3xxx_usb_ohci_pdata
,
530 static struct resource cns3xxx_usb_otg_resources
[] = {
532 .start
= CNS3XXX_USBOTG_BASE
,
533 .end
= CNS3XXX_USBOTG_BASE
+ SZ_16M
- 1,
534 .flags
= IORESOURCE_MEM
,
537 .start
= IRQ_CNS3XXX_USB_OTG
,
538 .flags
= IORESOURCE_IRQ
,
542 static u64 cns3xxx_usb_otg_dma_mask
= DMA_BIT_MASK(32);
544 static struct platform_device cns3xxx_usb_otg_device
= {
546 .num_resources
= ARRAY_SIZE(cns3xxx_usb_otg_resources
),
547 .resource
= cns3xxx_usb_otg_resources
,
549 .dma_mask
= &cns3xxx_usb_otg_dma_mask
,
550 .coherent_dma_mask
= DMA_BIT_MASK(32),
557 static struct resource laguna_i2c_resource
[] = {
559 .start
= CNS3XXX_SSP_BASE
+ 0x20,
560 .end
= CNS3XXX_SSP_BASE
+ 0x3f,
561 .flags
= IORESOURCE_MEM
,
563 .start
= IRQ_CNS3XXX_I2C
,
564 .flags
= IORESOURCE_IRQ
,
568 static struct platform_device laguna_i2c_controller
= {
569 .name
= "cns3xxx-i2c",
571 .resource
= laguna_i2c_resource
,
574 static struct memory_accessor
*at24_mem_acc
;
576 static void at24_setup(struct memory_accessor
*mem_acc
, void *context
)
580 at24_mem_acc
= mem_acc
;
582 /* Read MAC addresses */
583 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x100, 6) == 6)
584 memcpy(&laguna_net_data
.hwaddr
[0], buf
, ETH_ALEN
);
585 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x106, 6) == 6)
586 memcpy(&laguna_net_data
.hwaddr
[1], buf
, ETH_ALEN
);
587 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x10C, 6) == 6)
588 memcpy(&laguna_net_data
.hwaddr
[2], buf
, ETH_ALEN
);
589 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x112, 6) == 6)
590 memcpy(&laguna_net_data
.hwaddr
[3], buf
, ETH_ALEN
);
592 /* Read out Model Information */
593 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x130, 16) == 16)
594 memcpy(&laguna_info
.model
, buf
, 16);
595 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x140, 1) == 1)
596 memcpy(&laguna_info
.nor_flash_size
, buf
, 1);
597 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x141, 1) == 1)
598 memcpy(&laguna_info
.spi_flash_size
, buf
, 1);
599 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x142, 4) == 4)
600 memcpy(&laguna_info
.config_bitmap
, buf
, 4);
601 if (at24_mem_acc
->read(at24_mem_acc
, buf
, 0x146, 4) == 4)
602 memcpy(&laguna_info
.config2_bitmap
, buf
, 4);
605 static struct at24_platform_data laguna_eeprom_info
= {
608 .flags
= AT24_FLAG_READONLY
,
612 static struct pca953x_platform_data laguna_pca_data
= {
617 static struct pca953x_platform_data laguna_pca2_data
= {
622 static struct i2c_board_info __initdata laguna_i2c_devices
[] = {
624 I2C_BOARD_INFO("pca9555", 0x23),
625 .platform_data
= &laguna_pca_data
,
627 I2C_BOARD_INFO("pca9555", 0x27),
628 .platform_data
= &laguna_pca2_data
,
630 I2C_BOARD_INFO("gsp", 0x29),
632 I2C_BOARD_INFO ("24c08",0x50),
633 .platform_data
= &laguna_eeprom_info
,
635 I2C_BOARD_INFO("ds1672", 0x68),
643 static struct resource laguna_watchdog_resources
[] = {
645 .start
= CNS3XXX_TC11MP_TWD_BASE
+ 0x100, // CPU0 watchdog
646 .end
= CNS3XXX_TC11MP_TWD_BASE
+ SZ_4K
- 1,
647 .flags
= IORESOURCE_MEM
,
651 static struct platform_device laguna_watchdog
= {
652 .name
= "mpcore_wdt",
654 .num_resources
= ARRAY_SIZE(laguna_watchdog_resources
),
655 .resource
= laguna_watchdog_resources
,
661 static struct pps_gpio_platform_data laguna_pps_data
= {
663 .gpio_label
= "GPS_PPS",
664 .assert_falling_edge
= 0,
668 static struct platform_device laguna_pps_device
= {
671 .dev
.platform_data
= &laguna_pps_data
,
678 static struct gpio laguna_gpio_gw2391
[] = {
679 { 0, GPIOF_IN
, "*GPS_PPS" },
680 { 1, GPIOF_IN
, "*GSC_IRQ#" },
681 { 2, GPIOF_IN
, "*USB_FAULT#" },
682 { 5, GPIOF_OUT_INIT_LOW
, "*USB0_PCI_SEL" },
683 { 6, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
684 { 7, GPIOF_OUT_INIT_LOW
, "*USB1_PCI_SEL" },
685 { 8, GPIOF_OUT_INIT_HIGH
, "*PERST#" },
686 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN#" },
687 { 100, GPIOF_IN
, "*USER_PB#" },
688 { 103, GPIOF_OUT_INIT_HIGH
, "*V5_EN" },
689 { 108, GPIOF_IN
, "DIO0" },
690 { 109, GPIOF_IN
, "DIO1" },
691 { 110, GPIOF_IN
, "DIO2" },
692 { 111, GPIOF_IN
, "DIO3" },
693 { 112, GPIOF_IN
, "DIO4" },
696 static struct gpio laguna_gpio_gw2388
[] = {
697 { 0, GPIOF_IN
, "*GPS_PPS" },
698 { 1, GPIOF_IN
, "*GSC_IRQ#" },
699 { 3, GPIOF_IN
, "*USB_FAULT#" },
700 { 6, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
701 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
702 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
703 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN" },
704 { 100, GPIOF_OUT_INIT_HIGH
, "*USER_PB#" },
705 { 108, GPIOF_IN
, "DIO0" },
706 { 109, GPIOF_IN
, "DIO1" },
707 { 110, GPIOF_IN
, "DIO2" },
708 { 111, GPIOF_IN
, "DIO3" },
709 { 112, GPIOF_IN
, "DIO4" },
712 static struct gpio laguna_gpio_gw2387
[] = {
713 { 0, GPIOF_IN
, "*GPS_PPS" },
714 { 1, GPIOF_IN
, "*GSC_IRQ#" },
715 { 2, GPIOF_IN
, "*USB_FAULT#" },
716 { 5, GPIOF_OUT_INIT_LOW
, "*USB_PCI_SEL" },
717 { 6, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
718 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
719 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
720 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN" },
721 { 100, GPIOF_IN
, "*USER_PB#" },
722 { 103, GPIOF_OUT_INIT_HIGH
, "*V5_EN" },
723 { 108, GPIOF_IN
, "DIO0" },
724 { 109, GPIOF_IN
, "DIO1" },
725 { 110, GPIOF_IN
, "DIO2" },
726 { 111, GPIOF_IN
, "DIO3" },
727 { 112, GPIOF_IN
, "DIO4" },
728 { 113, GPIOF_IN
, "DIO5" },
731 static struct gpio laguna_gpio_gw2385
[] = {
732 { 0, GPIOF_IN
, "*GSC_IRQ#" },
733 { 1, GPIOF_OUT_INIT_HIGH
, "*USB_HST_VBUS_EN" },
734 { 2, GPIOF_IN
, "*USB_HST_FAULT#" },
735 { 5, GPIOF_IN
, "*USB_OTG_FAULT#" },
736 { 6, GPIOF_OUT_INIT_LOW
, "*USB_HST_PCI_SEL" },
737 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
738 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
739 { 9, GPIOF_OUT_INIT_LOW
, "*SER_EN" },
740 { 10, GPIOF_IN
, "*USER_PB#" },
741 { 11, GPIOF_OUT_INIT_HIGH
, "*PERST#" },
742 { 100, GPIOF_IN
, "*USER_PB#" },
743 { 103, GPIOF_OUT_INIT_HIGH
, "V5_EN" },
746 static struct gpio laguna_gpio_gw2384
[] = {
747 { 0, GPIOF_IN
, "*GSC_IRQ#" },
748 { 1, GPIOF_OUT_INIT_HIGH
, "*USB_HST_VBUS_EN" },
749 { 2, GPIOF_IN
, "*USB_HST_FAULT#" },
750 { 5, GPIOF_IN
, "*USB_OTG_FAULT#" },
751 { 6, GPIOF_OUT_INIT_LOW
, "*USB_HST_PCI_SEL" },
752 { 7, GPIOF_OUT_INIT_LOW
, "*GSM_SEL0" },
753 { 8, GPIOF_OUT_INIT_LOW
, "*GSM_SEL1" },
754 { 9, GPIOF_OUT_INIT_LOW
, "*FP_SER_EN" },
755 { 12, GPIOF_OUT_INIT_LOW
, "J10_DIOLED0" },
756 { 13, GPIOF_OUT_INIT_HIGH
, "*I2CMUX_RST#" },
757 { 14, GPIOF_OUT_INIT_LOW
, "J10_DIOLED1" },
758 { 15, GPIOF_OUT_INIT_LOW
, "J10_DIOLED2" },
759 { 100, GPIOF_IN
, "*USER_PB#" },
760 { 103, GPIOF_OUT_INIT_HIGH
, "V5_EN" },
761 { 108, GPIOF_IN
, "J9_DIOGSC0" },
764 static struct gpio laguna_gpio_gw2383
[] = {
765 { 0, GPIOF_IN
, "*GPS_PPS" },
766 { 1, GPIOF_IN
, "*GSC_IRQ#" },
767 { 2, GPIOF_OUT_INIT_HIGH
, "*PCIE_RST#" },
768 { 3, GPIOF_IN
, "GPIO0" },
769 { 8, GPIOF_IN
, "GPIO1" },
770 { 100, GPIOF_IN
, "DIO0" },
771 { 101, GPIOF_IN
, "DIO1" },
772 { 108, GPIOF_IN
, "*USER_PB#" },
775 static struct gpio laguna_gpio_gw2382
[] = {
776 { 0, GPIOF_IN
, "*GPS_PPS" },
777 { 1, GPIOF_IN
, "*GSC_IRQ#" },
778 { 2, GPIOF_OUT_INIT_HIGH
, "*PCIE_RST#" },
779 { 3, GPIOF_IN
, "GPIO0" },
780 { 4, GPIOF_IN
, "GPIO1" },
781 { 9, GPIOF_OUT_INIT_HIGH
, "*USB_VBUS_EN" },
782 { 10, GPIOF_OUT_INIT_HIGH
, "*USB_PCI_SEL#" },
783 { 100, GPIOF_IN
, "DIO0" },
784 { 101, GPIOF_IN
, "DIO1" },
785 { 108, GPIOF_IN
, "*USER_PB#" },
788 static struct gpio laguna_gpio_gw2380
[] = {
789 { 0, GPIOF_IN
, "*GPS_PPS" },
790 { 1, GPIOF_IN
, "*GSC_IRQ#" },
791 { 3, GPIOF_IN
, "GPIO0" },
792 { 8, GPIOF_IN
, "GPIO1" },
793 { 100, GPIOF_IN
, "DIO0" },
794 { 101, GPIOF_IN
, "DIO1" },
795 { 102, GPIOF_IN
, "DIO2" },
796 { 103, GPIOF_IN
, "DIO3" },
797 { 108, GPIOF_IN
, "*USER_PB#" },
803 static void __init
laguna_init(void)
808 clk
= clk_register_fixed_rate(NULL
, "cpu", NULL
,
809 CLK_IS_ROOT
| CLK_IGNORE_UNUSED
,
810 cns3xxx_cpu_clock() * (1000000 / 8));
811 clk_register_clkdev(clk
, "cpu", NULL
);
813 platform_device_register(&laguna_watchdog
);
815 platform_device_register(&laguna_i2c_controller
);
817 /* Set I2C 0-3 drive strength to 21 mA */
818 reg
= MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B
;
821 /* Enable SCL/SDA for I2C */
822 reg
= MISC_GPIOB_PIN_ENABLE_REG
;
823 *reg
|= BIT(12) | BIT(13);
825 /* Enable MMC/SD pins */
826 *reg
|= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
828 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C
);
829 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C
);
830 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C
);
832 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C
));
833 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C
));
835 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices
));
837 pm_power_off
= cns3xxx_power_off
;
840 static struct map_desc laguna_io_desc
[] __initdata
= {
842 .virtual = CNS3XXX_UART0_BASE_VIRT
,
843 .pfn
= __phys_to_pfn(CNS3XXX_UART0_BASE
),
849 static void __init
laguna_map_io(void)
852 cns3xxx_pcie_iotable_init();
853 iotable_init(ARRAY_AND_SIZE(laguna_io_desc
));
854 laguna_early_serial_setup();
857 static int laguna_register_gpio(struct gpio
*array
, size_t num
)
862 for (i
= 0; i
< num
; i
++, array
++) {
863 const char *label
= array
->label
;
866 err
= gpio_request_one(array
->gpio
, array
->flags
, label
);
870 err
= gpio_export(array
->gpio
, array
->label
[0] != '*');
876 static int __init
laguna_pcie_init(void)
878 if (!machine_is_gw2388())
881 return cns3xxx_pcie_init();
883 subsys_initcall(laguna_pcie_init
);
885 static int __init
laguna_model_setup(void)
890 if (!machine_is_gw2388())
893 printk("Running on Gateworks Laguna %s\n", laguna_info
.model
);
894 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT
, IRQ_CNS3XXX_GPIOA
,
896 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT
, IRQ_CNS3XXX_GPIOB
,
897 NR_IRQS_CNS3XXX
+ 32);
899 if (strncmp(laguna_info
.model
, "GW", 2) == 0) {
900 if (laguna_info
.config_bitmap
& ETH0_LOAD
)
901 laguna_net_data
.ports
|= BIT(0);
902 if (laguna_info
.config_bitmap
& ETH1_LOAD
)
903 laguna_net_data
.ports
|= BIT(1);
904 if (laguna_info
.config_bitmap
& ETH2_LOAD
)
905 laguna_net_data
.ports
|= BIT(2);
906 if (laguna_net_data
.ports
)
907 platform_device_register(&laguna_net_device
);
909 if ((laguna_info
.config_bitmap
& SATA0_LOAD
) ||
910 (laguna_info
.config_bitmap
& SATA1_LOAD
))
913 if (laguna_info
.config_bitmap
& (USB0_LOAD
)) {
914 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB
);
916 /* DRVVBUS pins share with GPIOA */
917 mem
= (void __iomem
*)(CNS3XXX_MISC_BASE_VIRT
+ 0x0014);
918 reg
= __raw_readl(mem
);
920 __raw_writel(reg
, mem
);
923 mem
= (void __iomem
*)(CNS3XXX_MISC_BASE_VIRT
+ 0x0808);
924 reg
= __raw_readl(mem
);
926 __raw_writel(reg
, mem
);
928 platform_device_register(&cns3xxx_usb_otg_device
);
931 if (laguna_info
.config_bitmap
& (USB1_LOAD
)) {
932 platform_device_register(&cns3xxx_usb_ehci_device
);
933 platform_device_register(&cns3xxx_usb_ohci_device
);
936 if (laguna_info
.config_bitmap
& (SD_LOAD
))
937 cns3xxx_sdhci_init();
939 if (laguna_info
.config_bitmap
& (UART0_LOAD
))
940 laguna_uart
.num_resources
= 1;
941 if (laguna_info
.config_bitmap
& (UART1_LOAD
))
942 laguna_uart
.num_resources
= 2;
943 if (laguna_info
.config_bitmap
& (UART2_LOAD
))
944 laguna_uart
.num_resources
= 3;
945 platform_device_register(&laguna_uart
);
947 if (laguna_info
.config2_bitmap
& (NOR_FLASH_LOAD
)) {
948 switch (laguna_info
.nor_flash_size
) {
950 laguna_nor_partitions
[3].size
= SZ_8M
- SZ_256K
- SZ_128K
- SZ_2M
;
951 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_8M
- 1;
954 laguna_nor_partitions
[3].size
= SZ_16M
- SZ_256K
- SZ_128K
- SZ_2M
;
955 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_16M
- 1;
958 laguna_nor_partitions
[3].size
= SZ_32M
- SZ_256K
- SZ_128K
- SZ_2M
;
959 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_32M
- 1;
962 laguna_nor_partitions
[3].size
= SZ_64M
- SZ_256K
- SZ_128K
- SZ_2M
;
963 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_64M
- 1;
966 laguna_nor_partitions
[3].size
= SZ_128M
- SZ_256K
- SZ_128K
- SZ_2M
;
967 laguna_nor_res
.end
= CNS3XXX_FLASH_BASE
+ SZ_128M
- 1;
970 platform_device_register(&laguna_nor_pdev
);
973 if (laguna_info
.config2_bitmap
& (SPI_FLASH_LOAD
)) {
974 switch (laguna_info
.spi_flash_size
) {
976 laguna_spi_partitions
[3].size
= SZ_4M
- SZ_2M
;
979 laguna_spi_partitions
[3].size
= SZ_8M
- SZ_2M
;
982 laguna_spi_partitions
[3].size
= SZ_16M
- SZ_2M
;
985 laguna_spi_partitions
[3].size
= SZ_32M
- SZ_2M
;
988 laguna_spi_partitions
[3].size
= SZ_64M
- SZ_2M
;
991 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices
));
994 if ((laguna_info
.config_bitmap
& SPI0_LOAD
) ||
995 (laguna_info
.config_bitmap
& SPI1_LOAD
))
996 platform_device_register(&laguna_spi_controller
);
998 if (laguna_info
.config2_bitmap
& GPS_LOAD
)
999 platform_device_register(&laguna_pps_device
);
1002 * Do any model specific setup not known by the bitmap by matching
1003 * the first 6 characters of the model name
1006 if ( (strncmp(laguna_info
.model
, "GW2388", 6) == 0)
1007 || (strncmp(laguna_info
.model
, "GW2389", 6) == 0) )
1010 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388
));
1012 laguna_gpio_leds_data
.num_leds
= 2;
1013 } else if (strncmp(laguna_info
.model
, "GW2387", 6) == 0) {
1015 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387
));
1017 laguna_gpio_leds_data
.num_leds
= 2;
1018 } else if (strncmp(laguna_info
.model
, "GW2385", 6) == 0) {
1020 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385
));
1022 laguna_gpio_leds
[0].gpio
= 115;
1023 laguna_gpio_leds
[1].gpio
= 12;
1024 laguna_gpio_leds
[1].name
= "red";
1025 laguna_gpio_leds
[1].active_low
= 0,
1026 laguna_gpio_leds
[2].gpio
= 14;
1027 laguna_gpio_leds
[2].name
= "green";
1028 laguna_gpio_leds
[2].active_low
= 0,
1029 laguna_gpio_leds
[3].gpio
= 15;
1030 laguna_gpio_leds
[3].name
= "blue";
1031 laguna_gpio_leds
[3].active_low
= 0,
1032 laguna_gpio_leds_data
.num_leds
= 4;
1033 } else if ( (strncmp(laguna_info
.model
, "GW2384", 6) == 0)
1034 || (strncmp(laguna_info
.model
, "GW2394", 6) == 0) )
1037 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384
));
1039 laguna_gpio_leds_data
.num_leds
= 1;
1040 } else if (strncmp(laguna_info
.model
, "GW2383", 6) == 0) {
1042 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383
));
1044 laguna_gpio_leds
[0].gpio
= 107;
1045 laguna_gpio_leds_data
.num_leds
= 1;
1046 } else if (strncmp(laguna_info
.model
, "GW2382", 6) == 0) {
1048 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382
));
1050 laguna_gpio_leds
[0].gpio
= 107;
1051 laguna_gpio_leds_data
.num_leds
= 1;
1052 } else if (strncmp(laguna_info
.model
, "GW2380", 6) == 0) {
1054 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380
));
1056 laguna_gpio_leds
[0].gpio
= 107;
1057 laguna_gpio_leds
[1].gpio
= 106;
1058 laguna_gpio_leds_data
.num_leds
= 2;
1059 } else if ( (strncmp(laguna_info
.model
, "GW2391", 6) == 0)
1060 || (strncmp(laguna_info
.model
, "GW2393", 6) == 0) )
1063 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391
));
1065 laguna_gpio_leds_data
.num_leds
= 2;
1067 platform_device_register(&laguna_gpio_leds_device
);
1069 // Do some defaults here, not sure what yet
1073 late_initcall(laguna_model_setup
);
1075 MACHINE_START(GW2388
, "Gateworks Corporation Laguna Platform")
1076 .smp
= smp_ops(cns3xxx_smp_ops
),
1077 .atag_offset
= 0x100,
1078 .map_io
= laguna_map_io
,
1079 .init_irq
= cns3xxx_init_irq
,
1080 .init_time
= cns3xxx_timer_init
,
1081 .init_machine
= laguna_init
,
1082 .restart
= cns3xxx_restart
,