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[openwrt/staging/dedeckeh.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / laguna.c
1 /*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
23 #include <linux/io.h>
24 #include <linux/irq.h>
25 #include <linux/gpio.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial_8250.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/physmap.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/leds.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_data/at24.h>
36 #include <linux/platform_data/pca953x.h>
37 #include <linux/spi/spi.h>
38 #include <linux/spi/flash.h>
39 #include <linux/if_ether.h>
40 #include <linux/pps-gpio.h>
41 #include <linux/usb/ehci_pdriver.h>
42 #include <linux/usb/ohci_pdriver.h>
43 #include <linux/clk-provider.h>
44 #include <linux/clkdev.h>
45 #include <linux/platform_data/cns3xxx.h>
46 #include <asm/setup.h>
47 #include <asm/mach-types.h>
48 #include <asm/mach/arch.h>
49 #include <asm/mach/map.h>
50 #include <asm/mach/time.h>
51 #include <mach/gpio.h>
52 #include "core.h"
53 #include "devices.h"
54 #include "cns3xxx.h"
55 #include "pm.h"
56
57 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
58
59 // Config 1 Bitmap
60 #define ETH0_LOAD BIT(0)
61 #define ETH1_LOAD BIT(1)
62 #define ETH2_LOAD BIT(2)
63 #define SATA0_LOAD BIT(3)
64 #define SATA1_LOAD BIT(4)
65 #define PCM_LOAD BIT(5)
66 #define I2S_LOAD BIT(6)
67 #define SPI0_LOAD BIT(7)
68 #define SPI1_LOAD BIT(8)
69 #define PCIE0_LOAD BIT(9)
70 #define PCIE1_LOAD BIT(10)
71 #define USB0_LOAD BIT(11)
72 #define USB1_LOAD BIT(12)
73 #define USB1_ROUTE BIT(13)
74 #define SD_LOAD BIT(14)
75 #define UART0_LOAD BIT(15)
76 #define UART1_LOAD BIT(16)
77 #define UART2_LOAD BIT(17)
78 #define MPCI0_LOAD BIT(18)
79 #define MPCI1_LOAD BIT(19)
80 #define MPCI2_LOAD BIT(20)
81 #define MPCI3_LOAD BIT(21)
82 #define FP_BUT_LOAD BIT(22)
83 #define FP_BUT_HEADER_LOAD BIT(23)
84 #define FP_LED_LOAD BIT(24)
85 #define FP_LED_HEADER_LOAD BIT(25)
86 #define FP_TAMPER_LOAD BIT(26)
87 #define HEADER_33V_LOAD BIT(27)
88 #define SATA_POWER_LOAD BIT(28)
89 #define FP_POWER_LOAD BIT(29)
90 #define GPIO_HEADER_LOAD BIT(30)
91 #define GSP_BAT_LOAD BIT(31)
92
93 // Config 2 Bitmap
94 #define FAN_LOAD BIT(0)
95 #define SPI_FLASH_LOAD BIT(1)
96 #define NOR_FLASH_LOAD BIT(2)
97 #define GPS_LOAD BIT(3)
98 #define SUPPLY_5V_LOAD BIT(6)
99 #define SUPPLY_33V_LOAD BIT(7)
100
101 struct laguna_board_info {
102 char model[16];
103 u32 config_bitmap;
104 u32 config2_bitmap;
105 u8 nor_flash_size;
106 u8 spi_flash_size;
107 };
108
109 static struct laguna_board_info laguna_info __initdata;
110
111 /*
112 * NOR Flash
113 */
114 static struct mtd_partition laguna_nor_partitions[] = {
115 {
116 .name = "uboot",
117 .offset = 0,
118 .size = SZ_256K,
119 .mask_flags = MTD_WRITEABLE,
120 }, {
121 .name = "params",
122 .offset = MTDPART_OFS_APPEND,
123 .size = SZ_128K,
124 }, {
125 .name = "firmware",
126 .offset = MTDPART_OFS_APPEND,
127 .size = MTDPART_SIZ_FULL,
128 },
129 };
130
131 static struct physmap_flash_data laguna_nor_pdata = {
132 .width = 2,
133 .parts = laguna_nor_partitions,
134 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
135 };
136
137 static struct resource laguna_nor_res = {
138 .start = CNS3XXX_FLASH_BASE,
139 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
140 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
141 };
142
143 static struct platform_device laguna_nor_pdev = {
144 .name = "physmap-flash",
145 .id = 0,
146 .resource = &laguna_nor_res,
147 .num_resources = 1,
148 .dev = {
149 .platform_data = &laguna_nor_pdata,
150 },
151 };
152
153 /*
154 * SPI
155 */
156 static struct mtd_partition laguna_spi_partitions[] = {
157 {
158 .name = "uboot",
159 .offset = 0,
160 .size = SZ_256K,
161 .mask_flags = MTD_WRITEABLE,
162 }, {
163 .name = "params",
164 .offset = MTDPART_OFS_APPEND,
165 .size = SZ_256K,
166 }, {
167 .name = "firmware",
168 .offset = MTDPART_OFS_APPEND,
169 .size = MTDPART_SIZ_FULL,
170 },
171 };
172
173 static struct flash_platform_data laguna_spi_pdata = {
174 .parts = laguna_spi_partitions,
175 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
176 };
177
178 static struct spi_board_info __initdata laguna_spi_devices[] = {
179 {
180 .modalias = "m25p80",
181 .platform_data = &laguna_spi_pdata,
182 .max_speed_hz = 50000000,
183 .bus_num = 1,
184 .chip_select = 0,
185 },
186 };
187
188 static struct resource laguna_spi_resource = {
189 .start = CNS3XXX_SSP_BASE + 0x40,
190 .end = CNS3XXX_SSP_BASE + 0x6f,
191 .flags = IORESOURCE_MEM,
192 };
193
194 static struct platform_device laguna_spi_controller = {
195 .name = "cns3xxx_spi",
196 .resource = &laguna_spi_resource,
197 .num_resources = 1,
198 };
199
200 /*
201 * LED's
202 */
203 static struct gpio_led laguna_gpio_leds[] = {
204 {
205 .name = "user1", /* Green Led */
206 .gpio = 115,
207 .active_low = 1,
208 },{
209 .name = "user2", /* Red Led */
210 .gpio = 114,
211 .active_low = 1,
212 },{
213 .name = "pwr1", /* Green Led */
214 .gpio = 116,
215 .active_low = 1,
216 },{
217 .name = "pwr2", /* Yellow Led */
218 .gpio = 117,
219 .active_low = 1,
220 },{
221 .name = "txd1", /* Green Led */
222 .gpio = 118,
223 .active_low = 1,
224 },{
225 .name = "txd2", /* Yellow Led */
226 .gpio = 119,
227 .active_low = 1,
228 },{
229 .name = "rxd1", /* Green Led */
230 .gpio = 120,
231 .active_low = 1,
232 },{
233 .name = "rxd2", /* Yellow Led */
234 .gpio = 121,
235 .active_low = 1,
236 },{
237 .name = "ser1", /* Green Led */
238 .gpio = 122,
239 .active_low = 1,
240 },{
241 .name = "ser2", /* Yellow Led */
242 .gpio = 123,
243 .active_low = 1,
244 },{
245 .name = "enet1", /* Green Led */
246 .gpio = 124,
247 .active_low = 1,
248 },{
249 .name = "enet2", /* Yellow Led */
250 .gpio = 125,
251 .active_low = 1,
252 },{
253 .name = "sig1_1", /* Green Led */
254 .gpio = 126,
255 .active_low = 1,
256 },{
257 .name = "sig1_2", /* Yellow Led */
258 .gpio = 127,
259 .active_low = 1,
260 },{
261 .name = "sig2_1", /* Green Led */
262 .gpio = 128,
263 .active_low = 1,
264 },{
265 .name = "sig2_2", /* Yellow Led */
266 .gpio = 129,
267 .active_low = 1,
268 },{
269 .name = "sig3_1", /* Green Led */
270 .gpio = 130,
271 .active_low = 1,
272 },{
273 .name = "sig3_2", /* Yellow Led */
274 .gpio = 131,
275 .active_low = 1,
276 },{
277 .name = "net1", /*Green Led */
278 .gpio = 109,
279 .active_low = 1,
280 },{
281 .name = "net2", /* Red Led */
282 .gpio = 110,
283 .active_low = 1,
284 },{
285 .name = "mod1", /* Green Led */
286 .gpio = 111,
287 .active_low = 1,
288 },{
289 .name = "mod2", /* Red Led */
290 .gpio = 112,
291 .active_low = 1,
292 },
293 };
294
295 static struct gpio_led_platform_data laguna_gpio_leds_data = {
296 .num_leds = 22,
297 .leds = laguna_gpio_leds,
298 };
299
300 static struct platform_device laguna_gpio_leds_device = {
301 .name = "leds-gpio",
302 .id = PLATFORM_DEVID_NONE,
303 .dev.platform_data = &laguna_gpio_leds_data,
304 };
305
306 /*
307 * Ethernet
308 */
309 static struct cns3xxx_plat_info laguna_net_data = {
310 .ports = 0,
311 .phy = {
312 0,
313 1,
314 2,
315 },
316 };
317
318 static struct resource laguna_net_resource[] = {
319 {
320 .name = "eth0_mem",
321 .start = CNS3XXX_SWITCH_BASE,
322 .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
323 .flags = IORESOURCE_MEM
324 }, {
325 .name = "eth_rx",
326 .start = IRQ_CNS3XXX_SW_R0RXC,
327 .end = IRQ_CNS3XXX_SW_R0RXC,
328 .flags = IORESOURCE_IRQ
329 }, {
330 .name = "eth_stat",
331 .start = IRQ_CNS3XXX_SW_STATUS,
332 .end = IRQ_CNS3XXX_SW_STATUS,
333 .flags = IORESOURCE_IRQ
334 }
335 };
336
337 static u64 laguna_net_dmamask = DMA_BIT_MASK(32);
338 static struct platform_device laguna_net_device = {
339 .name = "cns3xxx_eth",
340 .id = 0,
341 .resource = laguna_net_resource,
342 .num_resources = ARRAY_SIZE(laguna_net_resource),
343 .dev = {
344 .dma_mask = &laguna_net_dmamask,
345 .coherent_dma_mask = DMA_BIT_MASK(32),
346 .platform_data = &laguna_net_data,
347 }
348 };
349
350 /*
351 * UART
352 */
353 static void __init laguna_early_serial_setup(void)
354 {
355 #ifdef CONFIG_SERIAL_8250_CONSOLE
356 static struct uart_port laguna_serial_port = {
357 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
358 .mapbase = CNS3XXX_UART0_BASE,
359 .irq = IRQ_CNS3XXX_UART0,
360 .iotype = UPIO_MEM,
361 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
362 .regshift = 2,
363 .uartclk = 24000000,
364 .line = 0,
365 .type = PORT_16550A,
366 .fifosize = 16,
367 };
368
369 early_serial_setup(&laguna_serial_port);
370 #endif
371 }
372
373 static struct resource laguna_uart_resources[] = {
374 {
375 .start = CNS3XXX_UART0_BASE,
376 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
377 .flags = IORESOURCE_MEM
378 },{
379 .start = CNS3XXX_UART1_BASE,
380 .end = CNS3XXX_UART1_BASE + SZ_4K - 1,
381 .flags = IORESOURCE_MEM
382 },{
383 .start = CNS3XXX_UART2_BASE,
384 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
385 .flags = IORESOURCE_MEM
386 },
387 };
388
389 static struct plat_serial8250_port laguna_uart_data[] = {
390 {
391 .mapbase = (CNS3XXX_UART0_BASE),
392 .irq = IRQ_CNS3XXX_UART0,
393 .iotype = UPIO_MEM,
394 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP,
395 .regshift = 2,
396 .uartclk = 24000000,
397 .type = PORT_16550A,
398 },{
399 .mapbase = (CNS3XXX_UART1_BASE),
400 .irq = IRQ_CNS3XXX_UART1,
401 .iotype = UPIO_MEM,
402 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP,
403 .regshift = 2,
404 .uartclk = 24000000,
405 .type = PORT_16550A,
406 },{
407 .mapbase = (CNS3XXX_UART2_BASE),
408 .irq = IRQ_CNS3XXX_UART2,
409 .iotype = UPIO_MEM,
410 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP,
411 .regshift = 2,
412 .uartclk = 24000000,
413 .type = PORT_16550A,
414 },
415 { },
416 };
417
418 static struct platform_device laguna_uart = {
419 .name = "serial8250",
420 .id = PLAT8250_DEV_PLATFORM,
421 .dev.platform_data = laguna_uart_data,
422 .num_resources = 3,
423 .resource = laguna_uart_resources
424 };
425
426 /*
427 * USB
428 */
429 static struct resource cns3xxx_usb_ehci_resources[] = {
430 [0] = {
431 .start = CNS3XXX_USB_BASE,
432 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 [1] = {
436 .start = IRQ_CNS3XXX_USB_EHCI,
437 .flags = IORESOURCE_IRQ,
438 },
439 };
440
441 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
442
443 static int csn3xxx_usb_power_on(struct platform_device *pdev)
444 {
445 /*
446 * EHCI and OHCI share the same clock and power,
447 * resetting twice would cause the 1st controller been reset.
448 * Therefore only do power up at the first up device, and
449 * power down at the last down device.
450 *
451 * Set USB AHB INCR length to 16
452 */
453 if (atomic_inc_return(&usb_pwr_ref) == 1) {
454 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
455 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
456 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
457 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
458 MISC_CHIP_CONFIG_REG);
459 }
460
461 return 0;
462 }
463
464 static void csn3xxx_usb_power_off(struct platform_device *pdev)
465 {
466 /*
467 * EHCI and OHCI share the same clock and power,
468 * resetting twice would cause the 1st controller been reset.
469 * Therefore only do power up at the first up device, and
470 * power down at the last down device.
471 */
472 if (atomic_dec_return(&usb_pwr_ref) == 0)
473 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
474 }
475
476 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
477 .power_on = csn3xxx_usb_power_on,
478 .power_off = csn3xxx_usb_power_off,
479 };
480
481 static struct platform_device cns3xxx_usb_ehci_device = {
482 .name = "ehci-platform",
483 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
484 .resource = cns3xxx_usb_ehci_resources,
485 .dev = {
486 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
487 .coherent_dma_mask = DMA_BIT_MASK(32),
488 .platform_data = &cns3xxx_usb_ehci_pdata,
489 },
490 };
491
492 static struct resource cns3xxx_usb_ohci_resources[] = {
493 [0] = {
494 .start = CNS3XXX_USB_OHCI_BASE,
495 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
496 .flags = IORESOURCE_MEM,
497 },
498 [1] = {
499 .start = IRQ_CNS3XXX_USB_OHCI,
500 .flags = IORESOURCE_IRQ,
501 },
502 };
503
504 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
505
506 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
507 .num_ports = 1,
508 .power_on = csn3xxx_usb_power_on,
509 .power_off = csn3xxx_usb_power_off,
510 };
511
512 static struct platform_device cns3xxx_usb_ohci_device = {
513 .name = "ohci-platform",
514 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
515 .resource = cns3xxx_usb_ohci_resources,
516 .dev = {
517 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
518 .coherent_dma_mask = DMA_BIT_MASK(32),
519 .platform_data = &cns3xxx_usb_ohci_pdata,
520 },
521 };
522
523 static struct resource cns3xxx_usb_otg_resources[] = {
524 [0] = {
525 .start = CNS3XXX_USBOTG_BASE,
526 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
527 .flags = IORESOURCE_MEM,
528 },
529 [1] = {
530 .start = IRQ_CNS3XXX_USB_OTG,
531 .flags = IORESOURCE_IRQ,
532 },
533 };
534
535 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
536
537 static struct platform_device cns3xxx_usb_otg_device = {
538 .name = "dwc2",
539 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
540 .resource = cns3xxx_usb_otg_resources,
541 .dev = {
542 .dma_mask = &cns3xxx_usb_otg_dma_mask,
543 .coherent_dma_mask = DMA_BIT_MASK(32),
544 },
545 };
546
547 /*
548 * I2C
549 */
550 static struct resource laguna_i2c_resource[] = {
551 {
552 .start = CNS3XXX_SSP_BASE + 0x20,
553 .end = CNS3XXX_SSP_BASE + 0x3f,
554 .flags = IORESOURCE_MEM,
555 },{
556 .start = IRQ_CNS3XXX_I2C,
557 .flags = IORESOURCE_IRQ,
558 },
559 };
560
561 static struct platform_device laguna_i2c_controller = {
562 .name = "cns3xxx-i2c",
563 .num_resources = 2,
564 .resource = laguna_i2c_resource,
565 };
566
567 static struct nvmem_device *at24_nvmem;
568
569 static void at24_setup(struct nvmem_device *mem_acc, void *context)
570 {
571 char buf[16];
572
573 at24_nvmem = mem_acc;
574
575 /* Read MAC addresses */
576 if (nvmem_device_read(at24_nvmem, 0x100, 6, buf) == 6)
577 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
578 if (nvmem_device_read(at24_nvmem, 0x106, 6, buf) == 6)
579 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
580 if (nvmem_device_read(at24_nvmem, 0x10C, 6, buf) == 6)
581 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
582 if (nvmem_device_read(at24_nvmem, 0x112, 6, buf) == 6)
583 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
584
585 /* Read out Model Information */
586 if (nvmem_device_read(at24_nvmem, 0x130, 16, buf) == 16)
587 memcpy(&laguna_info.model, buf, 16);
588 if (nvmem_device_read(at24_nvmem, 0x140, 1, buf) == 1)
589 memcpy(&laguna_info.nor_flash_size, buf, 1);
590 if (nvmem_device_read(at24_nvmem, 0x141, 1, buf) == 1)
591 memcpy(&laguna_info.spi_flash_size, buf, 1);
592 if (nvmem_device_read(at24_nvmem, 0x142, 4, buf) == 4)
593 memcpy(&laguna_info.config_bitmap, buf, 4);
594 if (nvmem_device_read(at24_nvmem, 0x146, 4, buf) == 4)
595 memcpy(&laguna_info.config2_bitmap, buf, 4);
596 };
597
598 static struct at24_platform_data laguna_eeprom_info = {
599 .byte_len = 1024,
600 .page_size = 16,
601 .flags = AT24_FLAG_READONLY,
602 .setup = at24_setup,
603 };
604
605 static struct pca953x_platform_data laguna_pca_data = {
606 .gpio_base = 100,
607 .irq_base = -1,
608 };
609
610 static struct pca953x_platform_data laguna_pca2_data = {
611 .gpio_base = 116,
612 .irq_base = -1,
613 };
614
615 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
616 {
617 I2C_BOARD_INFO("pca9555", 0x23),
618 .platform_data = &laguna_pca_data,
619 },{
620 I2C_BOARD_INFO("pca9555", 0x27),
621 .platform_data = &laguna_pca2_data,
622 },{
623 I2C_BOARD_INFO("gsp", 0x29),
624 },{
625 I2C_BOARD_INFO ("24c08",0x50),
626 .platform_data = &laguna_eeprom_info,
627 },{
628 I2C_BOARD_INFO("ds1672", 0x68),
629 },
630 };
631
632 /*
633 * Watchdog
634 */
635
636 static struct resource laguna_watchdog_resources[] = {
637 [0] = {
638 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
639 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
640 .flags = IORESOURCE_MEM,
641 },
642 };
643
644 static struct platform_device laguna_watchdog = {
645 .name = "mpcore_wdt",
646 .id = PLATFORM_DEVID_NONE,
647 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
648 .resource = laguna_watchdog_resources,
649 };
650
651 /*
652 * GPS PPS
653 */
654 static struct pps_gpio_platform_data laguna_pps_data = {
655 .gpio_pin = 0,
656 .gpio_label = "GPS_PPS",
657 .assert_falling_edge = 0,
658 .capture_clear = 0,
659 };
660
661 static struct platform_device laguna_pps_device = {
662 .name = "pps-gpio",
663 .id = PLATFORM_DEVID_NONE,
664 .dev.platform_data = &laguna_pps_data,
665 };
666
667 /*
668 * GPIO
669 */
670
671 static struct gpio laguna_gpio_gw2391[] = {
672 { 0, GPIOF_IN , "*GPS_PPS" },
673 { 1, GPIOF_IN , "*GSC_IRQ#" },
674 { 2, GPIOF_IN , "*USB_FAULT#" },
675 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
676 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
677 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
678 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
679 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
680 { 100, GPIOF_IN , "*USER_PB#" },
681 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
682 { 108, GPIOF_IN , "DIO0" },
683 { 109, GPIOF_IN , "DIO1" },
684 { 110, GPIOF_IN , "DIO2" },
685 { 111, GPIOF_IN , "DIO3" },
686 { 112, GPIOF_IN , "DIO4" },
687 };
688
689 static struct gpio laguna_gpio_gw2388[] = {
690 { 0, GPIOF_IN , "*GPS_PPS" },
691 { 1, GPIOF_IN , "*GSC_IRQ#" },
692 { 3, GPIOF_IN , "*USB_FAULT#" },
693 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
694 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
695 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
696 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
697 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
698 { 108, GPIOF_IN , "DIO0" },
699 { 109, GPIOF_IN , "DIO1" },
700 { 110, GPIOF_IN , "DIO2" },
701 { 111, GPIOF_IN , "DIO3" },
702 { 112, GPIOF_IN , "DIO4" },
703 };
704
705 static struct gpio laguna_gpio_gw2387[] = {
706 { 0, GPIOF_IN , "*GPS_PPS" },
707 { 1, GPIOF_IN , "*GSC_IRQ#" },
708 { 2, GPIOF_IN , "*USB_FAULT#" },
709 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
710 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
711 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
712 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
713 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
714 { 100, GPIOF_IN , "*USER_PB#" },
715 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
716 { 108, GPIOF_IN , "DIO0" },
717 { 109, GPIOF_IN , "DIO1" },
718 { 110, GPIOF_IN , "DIO2" },
719 { 111, GPIOF_IN , "DIO3" },
720 { 112, GPIOF_IN , "DIO4" },
721 { 113, GPIOF_IN , "DIO5" },
722 };
723
724 static struct gpio laguna_gpio_gw2386[] = {
725 { 0, GPIOF_IN , "*GPS_PPS" },
726 { 2, GPIOF_IN , "*USB_FAULT#" },
727 { 6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
728 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
729 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
730 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
731 { 108, GPIOF_IN , "DIO0" },
732 { 109, GPIOF_IN , "DIO1" },
733 { 110, GPIOF_IN , "DIO2" },
734 { 111, GPIOF_IN , "DIO3" },
735 { 112, GPIOF_IN , "DIO4" },
736 { 113, GPIOF_IN , "DIO5" },
737 };
738
739 static struct gpio laguna_gpio_gw2385[] = {
740 { 0, GPIOF_IN , "*GSC_IRQ#" },
741 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
742 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
743 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
744 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
745 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
746 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
747 { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
748 { 10, GPIOF_IN, "*USER_PB#" },
749 { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
750 { 100, GPIOF_IN , "*USER_PB#" },
751 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
752 };
753
754 static struct gpio laguna_gpio_gw2384[] = {
755 { 0, GPIOF_IN , "*GSC_IRQ#" },
756 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
757 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
758 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
759 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
760 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
761 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
762 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
763 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
764 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
765 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
766 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
767 { 100, GPIOF_IN , "*USER_PB#" },
768 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
769 { 108, GPIOF_IN , "J9_DIOGSC0" },
770 };
771
772 static struct gpio laguna_gpio_gw2383[] = {
773 { 0, GPIOF_IN , "*GPS_PPS" },
774 { 1, GPIOF_IN , "*GSC_IRQ#" },
775 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
776 { 3, GPIOF_IN , "GPIO0" },
777 { 8, GPIOF_IN , "GPIO1" },
778 { 100, GPIOF_IN , "DIO0" },
779 { 101, GPIOF_IN , "DIO1" },
780 { 108, GPIOF_IN , "*USER_PB#" },
781 };
782
783 static struct gpio laguna_gpio_gw2382[] = {
784 { 0, GPIOF_IN , "*GPS_PPS" },
785 { 1, GPIOF_IN , "*GSC_IRQ#" },
786 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
787 { 3, GPIOF_IN , "GPIO0" },
788 { 4, GPIOF_IN , "GPIO1" },
789 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
790 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
791 { 100, GPIOF_IN , "DIO0" },
792 { 101, GPIOF_IN , "DIO1" },
793 { 108, GPIOF_IN , "*USER_PB#" },
794 };
795
796 static struct gpio laguna_gpio_gw2380[] = {
797 { 0, GPIOF_IN , "*GPS_PPS" },
798 { 1, GPIOF_IN , "*GSC_IRQ#" },
799 { 3, GPIOF_IN , "GPIO0" },
800 { 8, GPIOF_IN , "GPIO1" },
801 { 100, GPIOF_IN , "DIO0" },
802 { 101, GPIOF_IN , "DIO1" },
803 { 102, GPIOF_IN , "DIO2" },
804 { 103, GPIOF_IN , "DIO3" },
805 { 108, GPIOF_IN , "*USER_PB#" },
806 };
807
808 /*
809 * Initialization
810 */
811 static void __init laguna_init(void)
812 {
813 struct clk *clk;
814 u32 __iomem *reg;
815
816 clk = clk_register_fixed_rate(NULL, "cpu", NULL,
817 CLK_IGNORE_UNUSED,
818 cns3xxx_cpu_clock() * (1000000 / 8));
819 clk_register_clkdev(clk, "cpu", NULL);
820
821 platform_device_register(&laguna_watchdog);
822
823 platform_device_register(&laguna_i2c_controller);
824
825 /* Set I2C 0-3 drive strength to 21 mA */
826 reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
827 *reg |= 0x300;
828
829 /* Enable SCL/SDA for I2C */
830 reg = MISC_GPIOB_PIN_ENABLE_REG;
831 *reg |= BIT(12) | BIT(13);
832
833 /* Enable MMC/SD pins */
834 *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
835
836 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
837 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
838 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
839
840 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
841 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
842
843 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
844
845 pm_power_off = cns3xxx_power_off;
846 }
847
848 static struct map_desc laguna_io_desc[] __initdata = {
849 {
850 .virtual = CNS3XXX_UART0_BASE_VIRT,
851 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
852 .length = SZ_4K,
853 .type = MT_DEVICE,
854 },
855 };
856
857 static void __init laguna_map_io(void)
858 {
859 cns3xxx_map_io();
860 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
861 laguna_early_serial_setup();
862 }
863
864 static int laguna_register_gpio(struct gpio *array, size_t num)
865 {
866 int i, err, ret;
867
868 ret = 0;
869 for (i = 0; i < num; i++, array++) {
870 const char *label = array->label;
871 if (label[0] == '*')
872 label++;
873 err = gpio_request_one(array->gpio, array->flags, label);
874 if (err)
875 ret = err;
876 else {
877 err = gpio_export(array->gpio, array->label[0] != '*');
878 }
879 }
880 return ret;
881 }
882
883 /* allow disabling of external isolated PCIe IRQs */
884 static int cns3xxx_pciextirq = 1;
885 static int __init cns3xxx_pciextirq_disable(char *s)
886 {
887 cns3xxx_pciextirq = 0;
888 return 1;
889 }
890 __setup("noextirq", cns3xxx_pciextirq_disable);
891
892 static int __init laguna_pcie_init_irq(void)
893 {
894 u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
895 u32 reg = (__raw_readl(mem) >> 26) & 0xf;
896 int irqs[] = {
897 IRQ_CNS3XXX_EXTERNAL_PIN0,
898 IRQ_CNS3XXX_EXTERNAL_PIN1,
899 IRQ_CNS3XXX_EXTERNAL_PIN2,
900 154,
901 };
902
903 if (!machine_is_gw2388())
904 return 0;
905
906 /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
907 if (cns3xxx_pciextirq && reg != 1)
908 cns3xxx_pciextirq = 0;
909
910 if (cns3xxx_pciextirq) {
911 printk("laguna: using isolated PCI interrupts:"
912 " irq%d/irq%d/irq%d/irq%d\n",
913 irqs[0], irqs[1], irqs[2], irqs[3]);
914 cns3xxx_pcie_set_irqs(0, irqs);
915 } else {
916 printk("laguna: using shared PCI interrupts: irq%d\n",
917 IRQ_CNS3XXX_PCIE0_DEVICE);
918 }
919
920 return 0;
921 }
922 subsys_initcall(laguna_pcie_init_irq);
923
924 static int __init laguna_model_setup(void)
925 {
926 u32 __iomem *mem;
927 u32 reg;
928
929 if (!machine_is_gw2388())
930 return 0;
931
932 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
933 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
934 NR_IRQS_CNS3XXX);
935
936 /*
937 * If pcie external interrupts are supported and desired
938 * configure IRQ types and configure pin function.
939 * Note that cns3xxx_pciextirq is enabled by default, but can be
940 * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
941 * the baseboard model does not support this hardware feature.
942 */
943 if (cns3xxx_pciextirq) {
944 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
945 reg = __raw_readl(mem);
946 /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
947 reg &= ~0x3c000000;
948 reg |= 0x38000000;
949 __raw_writel(reg, mem);
950
951 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
952 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
953
954 irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
955 irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
956 irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
957 irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
958 } else {
959 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
960 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
961 }
962
963 if (strncmp(laguna_info.model, "GW", 2) == 0) {
964 if (laguna_info.config_bitmap & ETH0_LOAD)
965 laguna_net_data.ports |= BIT(0);
966 if (laguna_info.config_bitmap & ETH1_LOAD)
967 laguna_net_data.ports |= BIT(1);
968 if (laguna_info.config_bitmap & ETH2_LOAD)
969 laguna_net_data.ports |= BIT(2);
970 if (laguna_net_data.ports)
971 platform_device_register(&laguna_net_device);
972
973 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
974 (laguna_info.config_bitmap & SATA1_LOAD))
975 cns3xxx_ahci_init();
976
977 if (laguna_info.config_bitmap & (USB0_LOAD)) {
978 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
979
980 /* DRVVBUS pins share with GPIOA */
981 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
982 reg = __raw_readl(mem);
983 reg |= 0x8;
984 __raw_writel(reg, mem);
985
986 /* Enable OTG */
987 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
988 reg = __raw_readl(mem);
989 reg &= ~(1 << 10);
990 __raw_writel(reg, mem);
991
992 platform_device_register(&cns3xxx_usb_otg_device);
993 }
994
995 if (laguna_info.config_bitmap & (USB1_LOAD)) {
996 platform_device_register(&cns3xxx_usb_ehci_device);
997 platform_device_register(&cns3xxx_usb_ohci_device);
998 }
999
1000 if (laguna_info.config_bitmap & (SD_LOAD))
1001 cns3xxx_sdhci_init();
1002
1003 if (laguna_info.config_bitmap & (UART0_LOAD))
1004 laguna_uart.num_resources = 1;
1005 if (laguna_info.config_bitmap & (UART1_LOAD))
1006 laguna_uart.num_resources = 2;
1007 if (laguna_info.config_bitmap & (UART2_LOAD))
1008 laguna_uart.num_resources = 3;
1009 platform_device_register(&laguna_uart);
1010
1011 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
1012 laguna_nor_partitions[2].size =
1013 (SZ_4M << laguna_info.nor_flash_size) -
1014 laguna_nor_partitions[2].offset;
1015 laguna_nor_res.end = CNS3XXX_FLASH_BASE +
1016 laguna_nor_partitions[2].offset +
1017 laguna_nor_partitions[2].size - 1;
1018 platform_device_register(&laguna_nor_pdev);
1019 }
1020
1021 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
1022 laguna_spi_partitions[2].size =
1023 (SZ_2M << laguna_info.spi_flash_size) -
1024 laguna_spi_partitions[2].offset;
1025 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
1026 }
1027
1028 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
1029 (laguna_info.config_bitmap & SPI1_LOAD))
1030 platform_device_register(&laguna_spi_controller);
1031
1032 if (laguna_info.config2_bitmap & GPS_LOAD)
1033 platform_device_register(&laguna_pps_device);
1034
1035 /*
1036 * Do any model specific setup not known by the bitmap by matching
1037 * the first 6 characters of the model name
1038 */
1039
1040 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
1041 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
1042 {
1043 // configure GPIO's
1044 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
1045 // configure LED's
1046 laguna_gpio_leds_data.num_leds = 2;
1047 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
1048 // configure GPIO's
1049 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
1050 // configure LED's
1051 laguna_gpio_leds_data.num_leds = 2;
1052 } else if (strncmp(laguna_info.model, "GW2386", 6) == 0) {
1053 // configure GPIO's
1054 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386));
1055 // configure LED's
1056 laguna_gpio_leds_data.num_leds = 2;
1057 } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
1058 // configure GPIO's
1059 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
1060 // configure LED's
1061 laguna_gpio_leds[0].gpio = 115;
1062 laguna_gpio_leds[1].gpio = 12;
1063 laguna_gpio_leds[1].name = "red";
1064 laguna_gpio_leds[1].active_low = 0,
1065 laguna_gpio_leds[2].gpio = 14;
1066 laguna_gpio_leds[2].name = "green";
1067 laguna_gpio_leds[2].active_low = 0,
1068 laguna_gpio_leds[3].gpio = 15;
1069 laguna_gpio_leds[3].name = "blue";
1070 laguna_gpio_leds[3].active_low = 0,
1071 laguna_gpio_leds_data.num_leds = 4;
1072 } else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0)
1073 || (strncmp(laguna_info.model, "GW2394", 6) == 0) )
1074 {
1075 // configure GPIO's
1076 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
1077 // configure LED's
1078 laguna_gpio_leds_data.num_leds = 1;
1079 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
1080 // configure GPIO's
1081 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
1082 // configure LED's
1083 laguna_gpio_leds[0].gpio = 107;
1084 laguna_gpio_leds_data.num_leds = 1;
1085 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
1086 // configure GPIO's
1087 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
1088 // configure LED's
1089 laguna_gpio_leds[0].gpio = 107;
1090 laguna_gpio_leds_data.num_leds = 1;
1091 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
1092 // configure GPIO's
1093 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
1094 // configure LED's
1095 laguna_gpio_leds[0].gpio = 107;
1096 laguna_gpio_leds[1].gpio = 106;
1097 laguna_gpio_leds_data.num_leds = 2;
1098 } else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0)
1099 || (strncmp(laguna_info.model, "GW2393", 6) == 0) )
1100 {
1101 // configure GPIO's
1102 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
1103 // configure LED's
1104 laguna_gpio_leds_data.num_leds = 2;
1105 }
1106 platform_device_register(&laguna_gpio_leds_device);
1107 } else {
1108 // Do some defaults here, not sure what yet
1109 }
1110 return 0;
1111 }
1112 late_initcall(laguna_model_setup);
1113
1114 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
1115 .smp = smp_ops(cns3xxx_smp_ops),
1116 .atag_offset = 0x100,
1117 .map_io = laguna_map_io,
1118 .init_irq = cns3xxx_init_irq,
1119 .init_time = cns3xxx_timer_init,
1120 .init_machine = laguna_init,
1121 .init_late = cns3xxx_pcie_init_late,
1122 .restart = cns3xxx_restart,
1123 MACHINE_END
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