2 * linux/arch/arm/mach-cns3xxx/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
5 * Copyright 2012 Gateworks Corporation
6 * Chris Lang <clang@gateworks.com>
7 * Tim Harvey <tharvey@gateworks.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
23 #include <asm/cacheflush.h>
24 #include <asm/smp_scu.h>
25 #include <asm/unified.h>
30 static struct fiq_handler fh
= {
51 } ____cacheline_aligned
;
53 extern unsigned int fiq_number
[2];
55 DEFINE_PER_CPU(struct fiq_req
, fiq_data
);
57 #define FIQ_ENABLED 0x80000000
58 #define FIQ_GENERATE 0x00010000
59 #define CNS3XXX_MAP_AREA 0x01000000
60 #define CNS3XXX_UNMAP_AREA 0x02000000
61 #define CNS3XXX_FLUSH_RANGE 0x03000000
63 extern void cns3xxx_secondary_startup(void);
64 extern unsigned char cns3xxx_fiq_start
, cns3xxx_fiq_end
;
66 #define SCU_CPU_STATUS 0x08
67 static void __iomem
*scu_base
;
69 static inline void __cpuinit
cns3xxx_set_fiq_regs(unsigned int cpu
)
71 struct pt_regs FIQ_regs
;
72 struct fiq_req
*fiq_req
= &per_cpu(fiq_data
, !cpu
);
75 FIQ_regs
.ARM_ip
= (unsigned int)fiq_req
;
76 FIQ_regs
.ARM_sp
= (int) MISC_FIQ_CPU(!cpu
);
77 fiq_req
->reg
= MISC_FIQ_CPU(!cpu
);
79 set_fiq_regs(&FIQ_regs
);
82 static void __init
cns3xxx_init_fiq(void)
84 void *fiqhandler_start
;
85 unsigned int fiqhandler_length
;
88 fiqhandler_start
= &cns3xxx_fiq_start
;
89 fiqhandler_length
= &cns3xxx_fiq_end
- &cns3xxx_fiq_start
;
95 set_fiq_handler(fiqhandler_start
, fiqhandler_length
);
100 * Write pen_release in a way that is guaranteed to be visible to all
101 * observers, irrespective of whether they're taking part in coherency
102 * or not. This is necessary for the hotplug code to work reliably.
104 static void __cpuinit
write_pen_release(int val
)
108 __cpuc_flush_dcache_area((void *)&pen_release
, sizeof(pen_release
));
109 outer_clean_range(__pa(&pen_release
), __pa(&pen_release
+ 1));
112 static DEFINE_SPINLOCK(boot_lock
);
114 static void __cpuinit
cns3xxx_secondary_init(unsigned int cpu
)
117 * Setup Secondary Core FIQ regs
119 cns3xxx_set_fiq_regs(1);
122 * let the primary processor know we're out of the
123 * pen, then head off into the C entry point
125 write_pen_release(-1);
128 * Synchronise with the boot thread.
130 spin_lock(&boot_lock
);
131 spin_unlock(&boot_lock
);
134 static int __cpuinit
cns3xxx_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
136 unsigned long timeout
;
139 * Set synchronisation state between this boot processor
140 * and the secondary one
142 spin_lock(&boot_lock
);
145 * The secondary processor is waiting to be released from
146 * the holding pen - release it, then wait for it to flag
147 * that it has been released by resetting pen_release.
149 * Note that "pen_release" is the hardware CPU ID, whereas
150 * "cpu" is Linux's internal ID.
152 write_pen_release(cpu
);
155 * Send the secondary CPU a soft interrupt, thereby causing
156 * the boot monitor to read the system wide flags register,
157 * and branch to the address found there.
159 arch_send_wakeup_ipi_mask(cpumask_of(cpu
));;
161 timeout
= jiffies
+ (1 * HZ
);
162 while (time_before(jiffies
, timeout
)) {
164 if (pen_release
== -1)
171 * now the secondary core is starting up let it run its
172 * calibrations, then wait for it to finish
174 spin_unlock(&boot_lock
);
176 return pen_release
!= -1 ? -ENOSYS
: 0;
180 * Initialise the CPU possible map early - this describes the CPUs
181 * which may be present or become present in the system.
183 static void __init
cns3xxx_smp_init_cpus(void)
185 unsigned int i
, ncores
;
188 scu_base
= (void __iomem
*) CNS3XXX_TC11MP_SCU_BASE_VIRT
;
190 /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
191 * used in scu_get_core_count
193 status
= __raw_readl(scu_base
+ SCU_CPU_STATUS
);
194 for (i
= 0; i
< NR_CPUS
+1; i
++) {
195 if (((status
>> (i
*2)) & 0x3) == 0)
196 set_cpu_possible(i
, true);
203 static void __init
cns3xxx_smp_prepare_cpus(unsigned int max_cpus
)
208 * Initialise the present map, which describes the set of CPUs
209 * actually populated at the present time.
211 for (i
= 0; i
< max_cpus
; i
++) {
212 set_cpu_present(i
, true);
218 scu_enable(scu_base
);
221 * Write the address of secondary startup into the
222 * system-wide flags register. The boot monitor waits
223 * until it receives a soft interrupt, and then the
224 * secondary CPU branches to this address.
226 __raw_writel(virt_to_phys(cns3xxx_secondary_startup
),
227 (void __iomem
*)(CNS3XXX_MISC_BASE_VIRT
+ 0x0600));
230 * Setup FIQ's for main cpu
233 cns3xxx_set_fiq_regs(0);
236 extern void v6_dma_map_area(const void *, size_t, int);
237 extern void v6_dma_unmap_area(const void *, size_t, int);
238 extern void v6_dma_flush_range(const void *, const void *);
239 extern void v6_flush_kern_dcache_area(void *, size_t);
241 void fiq_dma_map_area(const void *addr
, size_t size
, int dir
)
246 raw_local_irq_save(flags
);
247 /* currently, not possible to take cpu0 down, so only check cpu1 */
248 if (!cpu_online(1)) {
249 raw_local_irq_restore(flags
);
250 v6_dma_map_area(addr
, size
, dir
);
254 req
= this_cpu_ptr(&fiq_data
);
255 req
->map
.addr
= addr
;
256 req
->map
.size
= size
;
257 req
->flags
= dir
| CNS3XXX_MAP_AREA
;
260 writel_relaxed(FIQ_GENERATE
, req
->reg
);
262 v6_dma_map_area(addr
, size
, dir
);
266 raw_local_irq_restore(flags
);
269 void fiq_dma_unmap_area(const void *addr
, size_t size
, int dir
)
274 raw_local_irq_save(flags
);
275 /* currently, not possible to take cpu0 down, so only check cpu1 */
276 if (!cpu_online(1)) {
277 raw_local_irq_restore(flags
);
278 v6_dma_unmap_area(addr
, size
, dir
);
282 req
= this_cpu_ptr(&fiq_data
);
283 req
->unmap
.addr
= addr
;
284 req
->unmap
.size
= size
;
285 req
->flags
= dir
| CNS3XXX_UNMAP_AREA
;
288 writel_relaxed(FIQ_GENERATE
, req
->reg
);
290 v6_dma_unmap_area(addr
, size
, dir
);
294 raw_local_irq_restore(flags
);
297 void fiq_dma_flush_range(const void *start
, const void *end
)
302 raw_local_irq_save(flags
);
303 /* currently, not possible to take cpu0 down, so only check cpu1 */
304 if (!cpu_online(1)) {
305 raw_local_irq_restore(flags
);
306 v6_dma_flush_range(start
, end
);
310 req
= this_cpu_ptr(&fiq_data
);
312 req
->flush
.start
= start
;
313 req
->flush
.end
= end
;
314 req
->flags
= CNS3XXX_FLUSH_RANGE
;
317 writel_relaxed(FIQ_GENERATE
, req
->reg
);
319 v6_dma_flush_range(start
, end
);
324 raw_local_irq_restore(flags
);
327 void fiq_flush_kern_dcache_area(void *addr
, size_t size
)
329 fiq_dma_flush_range(addr
, addr
+ size
);
332 struct smp_operations cns3xxx_smp_ops __initdata
= {
333 .smp_init_cpus
= cns3xxx_smp_init_cpus
,
334 .smp_prepare_cpus
= cns3xxx_smp_prepare_cpus
,
335 .smp_secondary_init
= cns3xxx_secondary_init
,
336 .smp_boot_secondary
= cns3xxx_boot_secondary
,