2 * Cavium CNS3xxx Gigabit driver for Linux
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
26 #define DRV_NAME "cns3xxx_eth"
30 #define TX_DESC_RESERVE 20
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
45 #define NAPI_WEIGHT 64
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define UDP_CHECKSUM 0x00020000
60 #define TCP_CHECKSUM 0x00010000
62 /* Port Config Defines */
63 #define PORT_BP_ENABLE 0x00020000
64 #define PORT_DISABLE 0x00040000
65 #define PORT_LEARN_DIS 0x00080000
66 #define PORT_BLOCK_STATE 0x00100000
67 #define PORT_BLOCK_MODE 0x00200000
69 #define PROMISC_OFFSET 29
71 /* Global Config Defines */
72 #define UNKNOWN_VLAN_TO_CPU 0x02000000
73 #define ACCEPT_CRC_PACKET 0x00200000
74 #define CRC_STRIPPING 0x00100000
76 /* VLAN Config Defines */
77 #define NIC_MODE 0x00008000
78 #define VLAN_UNAWARE 0x00000001
80 /* DMA AUTO Poll Defines */
81 #define TS_POLL_EN 0x00000020
82 #define TS_SUSPEND 0x00000010
83 #define FS_POLL_EN 0x00000002
84 #define FS_SUSPEND 0x00000001
86 /* DMA Ring Control Defines */
87 #define QUEUE_THRESHOLD 0x000000f0
88 #define CLR_FS_STATE 0x80000000
90 /* Interrupt Status Defines */
91 #define MAC0_STATUS_CHANGE 0x00004000
92 #define MAC1_STATUS_CHANGE 0x00008000
93 #define MAC2_STATUS_CHANGE 0x00010000
94 #define MAC0_RX_ERROR 0x00100000
95 #define MAC1_RX_ERROR 0x00200000
96 #define MAC2_RX_ERROR 0x00400000
100 u32 sdp
; /* segment data pointer */
104 u32 sdl
:16; /* segment data length */
108 u32 rsv_1
:3; /* reserve */
110 u32 fp
:1; /* force priority */
150 u8 alignment
[16]; /* for 32 byte */
155 u32 sdp
; /* segment data pointer */
159 u32 sdl
:16; /* segment data length */
204 u8 alignment
[16]; /* for 32 byte alignment */
213 u32 mac_pri_ctrl
[5], __res
;
235 u32 fc_input_thrs
, __res1
[2];
237 u32 mac_glob_cfg_ext
, __res2
[2];
239 u32 dma_auto_poll_cfg
;
240 u32 delay_intr_cfg
, __res3
;
243 u32 ts_desc_base_addr0
, __res4
;
246 u32 fs_desc_base_addr0
, __res5
;
249 u32 ts_desc_base_addr1
, __res6
;
252 u32 fs_desc_base_addr1
;
254 u32 mac_counter0
[13];
258 struct tx_desc
*desc
;
259 dma_addr_t phys_addr
;
260 struct tx_desc
*cur_addr
;
261 struct sk_buff
*buff_tab
[TX_DESCS
];
262 unsigned int phys_tab
[TX_DESCS
];
272 struct rx_desc
*desc
;
273 dma_addr_t phys_addr
;
274 struct rx_desc
*cur_addr
;
275 void *buff_tab
[RX_DESCS
];
276 unsigned int phys_tab
[RX_DESCS
];
283 struct switch_regs __iomem
*regs
;
284 struct napi_struct napi
;
285 struct cns3xxx_plat_info
*plat
;
286 struct _tx_ring tx_ring
;
287 struct _rx_ring rx_ring
;
288 struct sk_buff
*frag_first
;
289 struct sk_buff
*frag_last
;
296 struct net_device
*netdev
;
297 struct phy_device
*phydev
;
299 int id
; /* logical port ID */
303 static spinlock_t mdio_lock
;
304 static DEFINE_SPINLOCK(tx_lock
);
305 static struct switch_regs __iomem
*mdio_regs
; /* mdio command and status only */
306 struct mii_bus
*mdio_bus
;
307 static int ports_open
;
308 static struct port
*switch_port_tab
[4];
309 struct net_device
*napi_dev
;
311 static int cns3xxx_mdio_cmd(struct mii_bus
*bus
, int phy_id
, int location
,
317 temp
= __raw_readl(&mdio_regs
->phy_control
);
318 temp
|= MDIO_CMD_COMPLETE
;
319 __raw_writel(temp
, &mdio_regs
->phy_control
);
323 temp
= (cmd
<< MDIO_VALUE_OFFSET
);
324 temp
|= MDIO_WRITE_COMMAND
;
326 temp
= MDIO_READ_COMMAND
;
328 temp
|= ((location
& 0x1f) << MDIO_REG_OFFSET
);
329 temp
|= (phy_id
& 0x1f);
331 __raw_writel(temp
, &mdio_regs
->phy_control
);
333 while (((__raw_readl(&mdio_regs
->phy_control
) & MDIO_CMD_COMPLETE
) == 0)
339 if (cycles
== 5000) {
340 printk(KERN_ERR
"%s #%i: MII transaction failed\n", bus
->name
,
345 temp
= __raw_readl(&mdio_regs
->phy_control
);
346 temp
|= MDIO_CMD_COMPLETE
;
347 __raw_writel(temp
, &mdio_regs
->phy_control
);
352 return ((temp
>> MDIO_VALUE_OFFSET
) & 0xFFFF);
355 static int cns3xxx_mdio_read(struct mii_bus
*bus
, int phy_id
, int location
)
360 spin_lock_irqsave(&mdio_lock
, flags
);
361 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 0, 0);
362 spin_unlock_irqrestore(&mdio_lock
, flags
);
366 static int cns3xxx_mdio_write(struct mii_bus
*bus
, int phy_id
, int location
,
372 spin_lock_irqsave(&mdio_lock
, flags
);
373 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 1, val
);
374 spin_unlock_irqrestore(&mdio_lock
, flags
);
378 static int cns3xxx_mdio_register(void __iomem
*base
)
382 if (!(mdio_bus
= mdiobus_alloc()))
387 spin_lock_init(&mdio_lock
);
388 mdio_bus
->name
= "CNS3xxx MII Bus";
389 mdio_bus
->read
= &cns3xxx_mdio_read
;
390 mdio_bus
->write
= &cns3xxx_mdio_write
;
391 strcpy(mdio_bus
->id
, "0");
393 if ((err
= mdiobus_register(mdio_bus
)))
394 mdiobus_free(mdio_bus
);
398 static void cns3xxx_mdio_remove(void)
400 mdiobus_unregister(mdio_bus
);
401 mdiobus_free(mdio_bus
);
404 static void enable_tx_dma(struct sw
*sw
)
406 __raw_writel(0x1, &sw
->regs
->ts_dma_ctrl0
);
409 static void enable_rx_dma(struct sw
*sw
)
411 __raw_writel(0x1, &sw
->regs
->fs_dma_ctrl0
);
414 static void cns3xxx_adjust_link(struct net_device
*dev
)
416 struct port
*port
= netdev_priv(dev
);
417 struct phy_device
*phydev
= port
->phydev
;
422 printk(KERN_INFO
"%s: link down\n", dev
->name
);
427 if (port
->speed
== phydev
->speed
&& port
->duplex
== phydev
->duplex
)
430 port
->speed
= phydev
->speed
;
431 port
->duplex
= phydev
->duplex
;
433 printk(KERN_INFO
"%s: link up, speed %u Mb/s, %s duplex\n",
434 dev
->name
, port
->speed
, port
->duplex
? "full" : "half");
437 static void eth_schedule_poll(struct sw
*sw
)
439 if (unlikely(!napi_schedule_prep(&sw
->napi
)))
442 disable_irq_nosync(sw
->rx_irq
);
443 __napi_schedule(&sw
->napi
);
446 irqreturn_t
eth_rx_irq(int irq
, void *pdev
)
448 struct net_device
*dev
= pdev
;
449 struct sw
*sw
= netdev_priv(dev
);
450 eth_schedule_poll(sw
);
451 return (IRQ_HANDLED
);
454 irqreturn_t
eth_stat_irq(int irq
, void *pdev
)
456 struct net_device
*dev
= pdev
;
457 struct sw
*sw
= netdev_priv(dev
);
459 u32 stat
= __raw_readl(&sw
->regs
->intr_stat
);
460 __raw_writel(0xffffffff, &sw
->regs
->intr_stat
);
462 if (stat
& MAC2_RX_ERROR
)
463 switch_port_tab
[3]->netdev
->stats
.rx_dropped
++;
464 if (stat
& MAC1_RX_ERROR
)
465 switch_port_tab
[1]->netdev
->stats
.rx_dropped
++;
466 if (stat
& MAC0_RX_ERROR
)
467 switch_port_tab
[0]->netdev
->stats
.rx_dropped
++;
469 if (stat
& MAC0_STATUS_CHANGE
) {
470 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[0]);
471 switch_port_tab
[0]->phydev
->link
= (cfg
& 0x1);
472 switch_port_tab
[0]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
473 if (((cfg
>> 2) & 0x3) == 2)
474 switch_port_tab
[0]->phydev
->speed
= 1000;
475 else if (((cfg
>> 2) & 0x3) == 1)
476 switch_port_tab
[0]->phydev
->speed
= 100;
478 switch_port_tab
[0]->phydev
->speed
= 10;
479 cns3xxx_adjust_link(switch_port_tab
[0]->netdev
);
482 if (stat
& MAC1_STATUS_CHANGE
) {
483 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[1]);
484 switch_port_tab
[1]->phydev
->link
= (cfg
& 0x1);
485 switch_port_tab
[1]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
486 if (((cfg
>> 2) & 0x3) == 2)
487 switch_port_tab
[1]->phydev
->speed
= 1000;
488 else if (((cfg
>> 2) & 0x3) == 1)
489 switch_port_tab
[1]->phydev
->speed
= 100;
491 switch_port_tab
[1]->phydev
->speed
= 10;
492 cns3xxx_adjust_link(switch_port_tab
[1]->netdev
);
495 if (stat
& MAC2_STATUS_CHANGE
) {
496 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[3]);
497 switch_port_tab
[3]->phydev
->link
= (cfg
& 0x1);
498 switch_port_tab
[3]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
499 if (((cfg
>> 2) & 0x3) == 2)
500 switch_port_tab
[3]->phydev
->speed
= 1000;
501 else if (((cfg
>> 2) & 0x3) == 1)
502 switch_port_tab
[3]->phydev
->speed
= 100;
504 switch_port_tab
[3]->phydev
->speed
= 10;
505 cns3xxx_adjust_link(switch_port_tab
[3]->netdev
);
508 return (IRQ_HANDLED
);
512 static void cns3xxx_alloc_rx_buf(struct sw
*sw
, int received
)
514 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
515 unsigned int i
= rx_ring
->alloc_index
;
516 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
520 for (received
+= rx_ring
->alloc_count
; received
> 0; received
--) {
521 buf
= napi_alloc_frag(RX_SEGMENT_ALLOC_SIZE
);
525 phys
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
526 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
527 if (dma_mapping_error(sw
->dev
, phys
)) {
532 desc
->sdl
= RX_SEGMENT_MRU
;
537 /* put the new buffer on RX-free queue */
538 rx_ring
->buff_tab
[i
] = buf
;
539 rx_ring
->phys_tab
[i
] = phys
;
540 if (i
== RX_DESCS
- 1) {
542 desc
->config0
= END_OF_RING
| FIRST_SEGMENT
|
543 LAST_SEGMENT
| RX_SEGMENT_MRU
;
544 desc
= &(rx_ring
)->desc
[i
];
546 desc
->config0
= FIRST_SEGMENT
| LAST_SEGMENT
|
553 rx_ring
->alloc_count
= received
;
554 rx_ring
->alloc_index
= i
;
557 static void eth_check_num_used(struct _tx_ring
*tx_ring
)
562 if (tx_ring
->num_used
>= TX_DESCS
- TX_DESC_RESERVE
)
565 if (tx_ring
->stopped
== stop
)
568 tx_ring
->stopped
= stop
;
569 for (i
= 0; i
< 4; i
++) {
570 struct port
*port
= switch_port_tab
[i
];
571 struct net_device
*dev
;
578 netif_stop_queue(dev
);
580 netif_wake_queue(dev
);
584 static void eth_complete_tx(struct sw
*sw
)
586 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
587 struct tx_desc
*desc
;
590 int num_used
= tx_ring
->num_used
;
593 index
= tx_ring
->free_index
;
594 desc
= &(tx_ring
)->desc
[index
];
595 for (i
= 0; i
< num_used
; i
++) {
597 skb
= tx_ring
->buff_tab
[index
];
598 tx_ring
->buff_tab
[index
] = 0;
600 dev_kfree_skb_any(skb
);
601 dma_unmap_single(sw
->dev
, tx_ring
->phys_tab
[index
],
602 desc
->sdl
, DMA_TO_DEVICE
);
603 if (++index
== TX_DESCS
) {
605 desc
= &(tx_ring
)->desc
[index
];
613 tx_ring
->free_index
= index
;
614 tx_ring
->num_used
-= i
;
615 eth_check_num_used(tx_ring
);
618 static int eth_poll(struct napi_struct
*napi
, int budget
)
620 struct sw
*sw
= container_of(napi
, struct sw
, napi
);
621 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
624 unsigned int i
= rx_ring
->cur_index
;
625 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
626 unsigned int alloc_count
= rx_ring
->alloc_count
;
628 while (desc
->cown
&& alloc_count
+ received
< RX_DESCS
- 1) {
630 int reserve
= SKB_HEAD_ALIGN
;
632 if (received
>= budget
)
635 /* process received frame */
636 dma_unmap_single(sw
->dev
, rx_ring
->phys_tab
[i
],
637 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
639 skb
= build_skb(rx_ring
->buff_tab
[i
], RX_SEGMENT_ALLOC_SIZE
);
643 skb
->dev
= switch_port_tab
[desc
->sp
]->netdev
;
646 if (desc
->fsd
&& !desc
->lsd
)
647 length
= RX_SEGMENT_MRU
;
650 reserve
-= NET_IP_ALIGN
;
652 length
+= NET_IP_ALIGN
;
655 skb_reserve(skb
, reserve
);
656 skb_put(skb
, length
);
659 sw
->frag_first
= skb
;
661 if (sw
->frag_first
== sw
->frag_last
)
662 skb_shinfo(sw
->frag_first
)->frag_list
= skb
;
664 sw
->frag_last
->next
= skb
;
665 sw
->frag_first
->len
+= skb
->len
;
666 sw
->frag_first
->data_len
+= skb
->len
;
667 sw
->frag_first
->truesize
+= skb
->truesize
;
672 struct net_device
*dev
;
674 skb
= sw
->frag_first
;
676 skb
->protocol
= eth_type_trans(skb
, dev
);
678 dev
->stats
.rx_packets
++;
679 dev
->stats
.rx_bytes
+= skb
->len
;
681 /* RX Hardware checksum offload */
682 skb
->ip_summed
= CHECKSUM_NONE
;
683 switch (desc
->prot
) {
691 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
692 napi_gro_receive(napi
, skb
);
697 netif_receive_skb(skb
);
701 sw
->frag_first
= NULL
;
702 sw
->frag_last
= NULL
;
706 if (++i
== RX_DESCS
) {
708 desc
= &(rx_ring
)->desc
[i
];
714 rx_ring
->cur_index
= i
;
716 cns3xxx_alloc_rx_buf(sw
, received
);
720 if (received
< budget
&& napi_complete_done(napi
, received
)) {
721 enable_irq(sw
->rx_irq
);
724 spin_lock_bh(&tx_lock
);
726 spin_unlock_bh(&tx_lock
);
731 static void eth_set_desc(struct sw
*sw
, struct _tx_ring
*tx_ring
, int index
,
732 int index_last
, void *data
, int len
, u32 config0
,
735 struct tx_desc
*tx_desc
= &(tx_ring
)->desc
[index
];
738 phys
= dma_map_single(sw
->dev
, data
, len
, DMA_TO_DEVICE
);
740 tx_desc
->pmap
= pmap
;
741 tx_ring
->phys_tab
[index
] = phys
;
744 if (index
== TX_DESCS
- 1)
745 config0
|= END_OF_RING
;
746 if (index
== index_last
)
747 config0
|= LAST_SEGMENT
;
750 tx_desc
->config0
= config0
;
753 static int eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
755 struct port
*port
= netdev_priv(dev
);
756 struct sw
*sw
= port
->sw
;
757 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
758 struct sk_buff
*skb1
;
759 char pmap
= (1 << port
->id
);
760 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
761 int nr_desc
= nr_frags
;
762 int index0
, index
, index_last
;
770 skb_walk_frags(skb
, skb1
)
773 eth_schedule_poll(sw
);
774 spin_lock_bh(&tx_lock
);
775 if ((tx_ring
->num_used
+ nr_desc
+ 1) >= TX_DESCS
) {
776 spin_unlock_bh(&tx_lock
);
777 return NETDEV_TX_BUSY
;
780 index
= index0
= tx_ring
->cur_index
;
781 index_last
= (index0
+ nr_desc
) % TX_DESCS
;
782 tx_ring
->cur_index
= (index_last
+ 1) % TX_DESCS
;
784 spin_unlock_bh(&tx_lock
);
786 config0
= FORCE_ROUTE
;
787 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
788 config0
|= UDP_CHECKSUM
| TCP_CHECKSUM
;
793 for (i
= 0; i
< nr_frags
; i
++) {
794 struct skb_frag_struct
*frag
;
797 index
= (index
+ 1) % TX_DESCS
;
799 frag
= &skb_shinfo(skb
)->frags
[i
];
800 addr
= page_address(skb_frag_page(frag
)) + frag
->page_offset
;
802 eth_set_desc(sw
, tx_ring
, index
, index_last
, addr
, frag
->size
,
807 len0
= skb
->len
- skb
->data_len
;
809 skb_walk_frags(skb
, skb1
) {
810 index
= (index
+ 1) % TX_DESCS
;
813 eth_set_desc(sw
, tx_ring
, index
, index_last
, skb1
->data
,
814 skb1
->len
, config0
, pmap
);
817 tx_ring
->buff_tab
[index0
] = skb
;
818 eth_set_desc(sw
, tx_ring
, index0
, index_last
, skb
->data
, len0
,
819 config0
| FIRST_SEGMENT
, pmap
);
824 tx_ring
->num_used
+= nr_desc
+ 1;
825 spin_unlock(&tx_lock
);
827 dev
->stats
.tx_packets
++;
828 dev
->stats
.tx_bytes
+= skb
->len
;
835 static int eth_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
837 struct port
*port
= netdev_priv(dev
);
839 if (!netif_running(dev
))
841 return phy_mii_ioctl(port
->phydev
, req
, cmd
);
844 /* ethtool support */
846 static void cns3xxx_get_drvinfo(struct net_device
*dev
,
847 struct ethtool_drvinfo
*info
)
849 strcpy(info
->driver
, DRV_NAME
);
850 strcpy(info
->bus_info
, "internal");
853 static int cns3xxx_nway_reset(struct net_device
*dev
)
855 struct port
*port
= netdev_priv(dev
);
856 return phy_start_aneg(port
->phydev
);
859 static struct ethtool_ops cns3xxx_ethtool_ops
= {
860 .get_drvinfo
= cns3xxx_get_drvinfo
,
861 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
862 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
863 .nway_reset
= cns3xxx_nway_reset
,
864 .get_link
= ethtool_op_get_link
,
868 static int init_rings(struct sw
*sw
)
871 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
872 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
874 __raw_writel(0, &sw
->regs
->fs_dma_ctrl0
);
875 __raw_writel(TS_SUSPEND
| FS_SUSPEND
, &sw
->regs
->dma_auto_poll_cfg
);
876 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
877 __raw_writel(CLR_FS_STATE
| QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
879 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
881 rx_ring
->desc
= dmam_alloc_coherent(sw
->dev
, RX_POOL_ALLOC_SIZE
,
882 &rx_ring
->phys_addr
, GFP_KERNEL
);
886 /* Setup RX buffers */
887 memset(rx_ring
->desc
, 0, RX_POOL_ALLOC_SIZE
);
888 for (i
= 0; i
< RX_DESCS
; i
++) {
889 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
892 buf
= netdev_alloc_frag(RX_SEGMENT_ALLOC_SIZE
);
896 desc
->sdl
= RX_SEGMENT_MRU
;
897 if (i
== (RX_DESCS
- 1))
902 desc
->sdp
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
903 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
904 if (dma_mapping_error(sw
->dev
, desc
->sdp
))
907 rx_ring
->buff_tab
[i
] = buf
;
908 rx_ring
->phys_tab
[i
] = desc
->sdp
;
911 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_ptr0
);
912 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_base_addr0
);
914 tx_ring
->desc
= dmam_alloc_coherent(sw
->dev
, TX_POOL_ALLOC_SIZE
,
915 &tx_ring
->phys_addr
, GFP_KERNEL
);
919 /* Setup TX buffers */
920 memset(tx_ring
->desc
, 0, TX_POOL_ALLOC_SIZE
);
921 for (i
= 0; i
< TX_DESCS
; i
++) {
922 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
923 tx_ring
->buff_tab
[i
] = 0;
925 if (i
== (TX_DESCS
- 1))
929 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_ptr0
);
930 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_base_addr0
);
935 static void destroy_rings(struct sw
*sw
)
939 for (i
= 0; i
< RX_DESCS
; i
++) {
940 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
941 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
942 void *buf
= sw
->rx_ring
.buff_tab
[i
];
947 dma_unmap_single(sw
->dev
, desc
->sdp
, RX_SEGMENT_MRU
,
952 for (i
= 0; i
< TX_DESCS
; i
++) {
953 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
954 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
955 struct sk_buff
*skb
= sw
->tx_ring
.buff_tab
[i
];
960 dma_unmap_single(sw
->dev
, desc
->sdp
, skb
->len
, DMA_TO_DEVICE
);
965 static int eth_open(struct net_device
*dev
)
967 struct port
*port
= netdev_priv(dev
);
968 struct sw
*sw
= port
->sw
;
971 port
->speed
= 0; /* force "link up" message */
972 phy_start(port
->phydev
);
974 netif_start_queue(dev
);
977 request_irq(sw
->rx_irq
, eth_rx_irq
, IRQF_SHARED
, "gig_switch", napi_dev
);
978 request_irq(sw
->stat_irq
, eth_stat_irq
, IRQF_SHARED
, "gig_stat", napi_dev
);
979 napi_enable(&sw
->napi
);
980 netif_start_queue(napi_dev
);
982 __raw_writel(~(MAC0_STATUS_CHANGE
| MAC1_STATUS_CHANGE
| MAC2_STATUS_CHANGE
|
983 MAC0_RX_ERROR
| MAC1_RX_ERROR
| MAC2_RX_ERROR
), &sw
->regs
->intr_mask
);
985 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
986 temp
&= ~(PORT_DISABLE
);
987 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
989 temp
= __raw_readl(&sw
->regs
->dma_auto_poll_cfg
);
990 temp
&= ~(TS_SUSPEND
| FS_SUSPEND
);
991 __raw_writel(temp
, &sw
->regs
->dma_auto_poll_cfg
);
995 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
996 temp
&= ~(PORT_DISABLE
);
997 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1000 netif_carrier_on(dev
);
1005 static int eth_close(struct net_device
*dev
)
1007 struct port
*port
= netdev_priv(dev
);
1008 struct sw
*sw
= port
->sw
;
1013 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1014 temp
|= (PORT_DISABLE
);
1015 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1017 netif_stop_queue(dev
);
1019 phy_stop(port
->phydev
);
1022 disable_irq(sw
->rx_irq
);
1023 free_irq(sw
->rx_irq
, napi_dev
);
1024 disable_irq(sw
->stat_irq
);
1025 free_irq(sw
->stat_irq
, napi_dev
);
1026 napi_disable(&sw
->napi
);
1027 netif_stop_queue(napi_dev
);
1028 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
1029 temp
|= (PORT_DISABLE
);
1030 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1032 __raw_writel(TS_SUSPEND
| FS_SUSPEND
,
1033 &sw
->regs
->dma_auto_poll_cfg
);
1036 netif_carrier_off(dev
);
1040 static void eth_rx_mode(struct net_device
*dev
)
1042 struct port
*port
= netdev_priv(dev
);
1043 struct sw
*sw
= port
->sw
;
1046 temp
= __raw_readl(&sw
->regs
->mac_glob_cfg
);
1048 if (dev
->flags
& IFF_PROMISC
) {
1050 temp
|= ((1 << 2) << PROMISC_OFFSET
);
1052 temp
|= ((1 << port
->id
) << PROMISC_OFFSET
);
1055 temp
&= ~((1 << 2) << PROMISC_OFFSET
);
1057 temp
&= ~((1 << port
->id
) << PROMISC_OFFSET
);
1059 __raw_writel(temp
, &sw
->regs
->mac_glob_cfg
);
1062 static int eth_set_mac(struct net_device
*netdev
, void *p
)
1064 struct port
*port
= netdev_priv(netdev
);
1065 struct sw
*sw
= port
->sw
;
1066 struct sockaddr
*addr
= p
;
1069 if (!is_valid_ether_addr(addr
->sa_data
))
1070 return -EADDRNOTAVAIL
;
1072 /* Invalidate old ARL Entry */
1074 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1076 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1077 __raw_writel( ((netdev
->dev_addr
[0] << 24) | (netdev
->dev_addr
[1] << 16) |
1078 (netdev
->dev_addr
[2] << 8) | (netdev
->dev_addr
[3])),
1079 &sw
->regs
->arl_ctrl
[1]);
1081 __raw_writel( ((netdev
->dev_addr
[4] << 24) | (netdev
->dev_addr
[5] << 16) |
1083 &sw
->regs
->arl_ctrl
[2]);
1084 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1086 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1093 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1096 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1098 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1099 __raw_writel( ((addr
->sa_data
[0] << 24) | (addr
->sa_data
[1] << 16) |
1100 (addr
->sa_data
[2] << 8) | (addr
->sa_data
[3])),
1101 &sw
->regs
->arl_ctrl
[1]);
1103 __raw_writel( ((addr
->sa_data
[4] << 24) | (addr
->sa_data
[5] << 16) |
1104 (7 << 4) | (1 << 1)), &sw
->regs
->arl_ctrl
[2]);
1105 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1107 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1115 static int cns3xxx_change_mtu(struct net_device
*dev
, int new_mtu
)
1117 if (new_mtu
> MAX_MTU
)
1124 static const struct net_device_ops cns3xxx_netdev_ops
= {
1125 .ndo_open
= eth_open
,
1126 .ndo_stop
= eth_close
,
1127 .ndo_start_xmit
= eth_xmit
,
1128 .ndo_set_rx_mode
= eth_rx_mode
,
1129 .ndo_do_ioctl
= eth_ioctl
,
1130 .ndo_change_mtu
= cns3xxx_change_mtu
,
1131 .ndo_set_mac_address
= eth_set_mac
,
1132 .ndo_validate_addr
= eth_validate_addr
,
1135 static int eth_init_one(struct platform_device
*pdev
)
1140 struct net_device
*dev
;
1141 struct cns3xxx_plat_info
*plat
= pdev
->dev
.platform_data
;
1142 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1145 struct resource
*res
;
1148 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1149 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1151 return PTR_ERR(regs
);
1153 err
= cns3xxx_mdio_register(regs
);
1157 if (!(napi_dev
= alloc_etherdev(sizeof(struct sw
)))) {
1159 goto err_remove_mdio
;
1162 strcpy(napi_dev
->name
, "cns3xxx_eth");
1163 napi_dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1165 SET_NETDEV_DEV(napi_dev
, &pdev
->dev
);
1166 sw
= netdev_priv(napi_dev
);
1167 memset(sw
, 0, sizeof(struct sw
));
1169 sw
->dev
= &pdev
->dev
;
1171 sw
->rx_irq
= platform_get_irq_byname(pdev
, "eth_rx");
1172 sw
->stat_irq
= platform_get_irq_byname(pdev
, "eth_stat");
1174 temp
= __raw_readl(&sw
->regs
->phy_auto_addr
);
1175 temp
|= (3 << 30); /* maximum frame length: 9600 bytes */
1176 __raw_writel(temp
, &sw
->regs
->phy_auto_addr
);
1178 for (i
= 0; i
< 4; i
++) {
1179 temp
= __raw_readl(&sw
->regs
->mac_cfg
[i
]);
1180 temp
|= (PORT_DISABLE
);
1181 __raw_writel(temp
, &sw
->regs
->mac_cfg
[i
]);
1184 temp
= PORT_DISABLE
;
1185 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1187 temp
= __raw_readl(&sw
->regs
->vlan_cfg
);
1188 temp
|= NIC_MODE
| VLAN_UNAWARE
;
1189 __raw_writel(temp
, &sw
->regs
->vlan_cfg
);
1191 __raw_writel(UNKNOWN_VLAN_TO_CPU
|
1192 CRC_STRIPPING
, &sw
->regs
->mac_glob_cfg
);
1194 if ((err
= init_rings(sw
)) != 0) {
1198 platform_set_drvdata(pdev
, napi_dev
);
1200 netif_napi_add(napi_dev
, &sw
->napi
, eth_poll
, NAPI_WEIGHT
);
1202 for (i
= 0; i
< 3; i
++) {
1203 if (!(plat
->ports
& (1 << i
))) {
1207 if (!(dev
= alloc_etherdev(sizeof(struct port
)))) {
1211 port
= netdev_priv(dev
);
1219 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1220 temp
|= (PORT_DISABLE
| PORT_BLOCK_STATE
| PORT_LEARN_DIS
);
1221 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1223 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1224 dev
->netdev_ops
= &cns3xxx_netdev_ops
;
1225 dev
->ethtool_ops
= &cns3xxx_ethtool_ops
;
1226 dev
->tx_queue_len
= 1000;
1227 dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1229 switch_port_tab
[port
->id
] = port
;
1230 memcpy(dev
->dev_addr
, &plat
->hwaddr
[i
], ETH_ALEN
);
1232 snprintf(phy_id
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, "0", plat
->phy
[i
]);
1233 port
->phydev
= phy_connect(dev
, phy_id
, &cns3xxx_adjust_link
,
1234 PHY_INTERFACE_MODE_RGMII
);
1235 if ((err
= IS_ERR(port
->phydev
))) {
1236 switch_port_tab
[port
->id
] = 0;
1241 port
->phydev
->irq
= PHY_IGNORE_INTERRUPT
;
1243 if ((err
= register_netdev(dev
))) {
1244 phy_disconnect(port
->phydev
);
1245 switch_port_tab
[port
->id
] = 0;
1250 printk(KERN_INFO
"%s: RGMII PHY %i on cns3xxx Switch\n", dev
->name
, plat
->phy
[i
]);
1251 netif_carrier_off(dev
);
1259 for (--i
; i
>= 0; i
--) {
1260 if (switch_port_tab
[i
]) {
1261 port
= switch_port_tab
[i
];
1263 unregister_netdev(dev
);
1264 phy_disconnect(port
->phydev
);
1265 switch_port_tab
[i
] = 0;
1270 free_netdev(napi_dev
);
1272 cns3xxx_mdio_remove();
1276 static int eth_remove_one(struct platform_device
*pdev
)
1278 struct net_device
*dev
= platform_get_drvdata(pdev
);
1279 struct sw
*sw
= netdev_priv(dev
);
1283 for (i
= 3; i
>= 0; i
--) {
1284 if (switch_port_tab
[i
]) {
1285 struct port
*port
= switch_port_tab
[i
];
1286 struct net_device
*dev
= port
->netdev
;
1287 unregister_netdev(dev
);
1288 phy_disconnect(port
->phydev
);
1289 switch_port_tab
[i
] = 0;
1294 free_netdev(napi_dev
);
1295 cns3xxx_mdio_remove();
1300 static struct platform_driver cns3xxx_eth_driver
= {
1301 .driver
.name
= DRV_NAME
,
1302 .probe
= eth_init_one
,
1303 .remove
= eth_remove_one
,
1306 static int __init
eth_init_module(void)
1308 return platform_driver_register(&cns3xxx_eth_driver
);
1311 static void __exit
eth_cleanup_module(void)
1313 platform_driver_unregister(&cns3xxx_eth_driver
);
1316 module_init(eth_init_module
);
1317 module_exit(eth_cleanup_module
);
1319 MODULE_AUTHOR("Chris Lang");
1320 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1321 MODULE_LICENSE("GPL v2");
1322 MODULE_ALIAS("platform:cns3xxx_eth");