2 * Cavium CNS3xxx Gigabit driver for Linux
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
26 #define DRV_NAME "cns3xxx_eth"
30 #define TX_DESC_RESERVE 20
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
45 #define NAPI_WEIGHT 64
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define UDP_CHECKSUM 0x00020000
60 #define TCP_CHECKSUM 0x00010000
62 /* Port Config Defines */
63 #define PORT_BP_ENABLE 0x00020000
64 #define PORT_DISABLE 0x00040000
65 #define PORT_LEARN_DIS 0x00080000
66 #define PORT_BLOCK_STATE 0x00100000
67 #define PORT_BLOCK_MODE 0x00200000
69 #define PROMISC_OFFSET 29
71 /* Global Config Defines */
72 #define UNKNOWN_VLAN_TO_CPU 0x02000000
73 #define ACCEPT_CRC_PACKET 0x00200000
74 #define CRC_STRIPPING 0x00100000
76 /* VLAN Config Defines */
77 #define NIC_MODE 0x00008000
78 #define VLAN_UNAWARE 0x00000001
80 /* DMA AUTO Poll Defines */
81 #define TS_POLL_EN 0x00000020
82 #define TS_SUSPEND 0x00000010
83 #define FS_POLL_EN 0x00000002
84 #define FS_SUSPEND 0x00000001
86 /* DMA Ring Control Defines */
87 #define QUEUE_THRESHOLD 0x000000f0
88 #define CLR_FS_STATE 0x80000000
90 /* Interrupt Status Defines */
91 #define MAC0_STATUS_CHANGE 0x00004000
92 #define MAC1_STATUS_CHANGE 0x00008000
93 #define MAC2_STATUS_CHANGE 0x00010000
94 #define MAC0_RX_ERROR 0x00100000
95 #define MAC1_RX_ERROR 0x00200000
96 #define MAC2_RX_ERROR 0x00400000
100 u32 sdp
; /* segment data pointer */
104 u32 sdl
:16; /* segment data length */
108 u32 rsv_1
:3; /* reserve */
110 u32 fp
:1; /* force priority */
150 u8 alignment
[16]; /* for 32 byte */
155 u32 sdp
; /* segment data pointer */
159 u32 sdl
:16; /* segment data length */
204 u8 alignment
[16]; /* for 32 byte alignment */
213 u32 mac_pri_ctrl
[5], __res
;
235 u32 fc_input_thrs
, __res1
[2];
237 u32 mac_glob_cfg_ext
, __res2
[2];
239 u32 dma_auto_poll_cfg
;
240 u32 delay_intr_cfg
, __res3
;
243 u32 ts_desc_base_addr0
, __res4
;
246 u32 fs_desc_base_addr0
, __res5
;
249 u32 ts_desc_base_addr1
, __res6
;
252 u32 fs_desc_base_addr1
;
254 u32 mac_counter0
[13];
258 struct tx_desc
*desc
;
259 dma_addr_t phys_addr
;
260 struct tx_desc
*cur_addr
;
261 struct sk_buff
*buff_tab
[TX_DESCS
];
262 unsigned int phys_tab
[TX_DESCS
];
272 struct rx_desc
*desc
;
273 dma_addr_t phys_addr
;
274 struct rx_desc
*cur_addr
;
275 void *buff_tab
[RX_DESCS
];
276 unsigned int phys_tab
[RX_DESCS
];
283 struct switch_regs __iomem
*regs
;
284 struct napi_struct napi
;
285 struct cns3xxx_plat_info
*plat
;
286 struct _tx_ring tx_ring
;
287 struct _rx_ring rx_ring
;
288 struct sk_buff
*frag_first
;
289 struct sk_buff
*frag_last
;
296 struct net_device
*netdev
;
297 struct phy_device
*phydev
;
299 int id
; /* logical port ID */
303 static spinlock_t mdio_lock
;
304 static DEFINE_SPINLOCK(tx_lock
);
305 static struct switch_regs __iomem
*mdio_regs
; /* mdio command and status only */
306 struct mii_bus
*mdio_bus
;
307 static int ports_open
;
308 static struct port
*switch_port_tab
[4];
309 struct net_device
*napi_dev
;
311 static int cns3xxx_mdio_cmd(struct mii_bus
*bus
, int phy_id
, int location
,
317 temp
= __raw_readl(&mdio_regs
->phy_control
);
318 temp
|= MDIO_CMD_COMPLETE
;
319 __raw_writel(temp
, &mdio_regs
->phy_control
);
323 temp
= (cmd
<< MDIO_VALUE_OFFSET
);
324 temp
|= MDIO_WRITE_COMMAND
;
326 temp
= MDIO_READ_COMMAND
;
329 temp
|= ((location
& 0x1f) << MDIO_REG_OFFSET
);
330 temp
|= (phy_id
& 0x1f);
332 __raw_writel(temp
, &mdio_regs
->phy_control
);
334 while (((__raw_readl(&mdio_regs
->phy_control
) & MDIO_CMD_COMPLETE
) == 0)
340 if (cycles
== 5000) {
341 printk(KERN_ERR
"%s #%i: MII transaction failed\n", bus
->name
, phy_id
);
345 temp
= __raw_readl(&mdio_regs
->phy_control
);
346 temp
|= MDIO_CMD_COMPLETE
;
347 __raw_writel(temp
, &mdio_regs
->phy_control
);
352 return ((temp
>> MDIO_VALUE_OFFSET
) & 0xFFFF);
355 static int cns3xxx_mdio_read(struct mii_bus
*bus
, int phy_id
, int location
)
360 spin_lock_irqsave(&mdio_lock
, flags
);
361 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 0, 0);
362 spin_unlock_irqrestore(&mdio_lock
, flags
);
366 static int cns3xxx_mdio_write(struct mii_bus
*bus
, int phy_id
, int location
, u16 val
)
371 spin_lock_irqsave(&mdio_lock
, flags
);
372 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 1, val
);
373 spin_unlock_irqrestore(&mdio_lock
, flags
);
377 static int cns3xxx_mdio_register(void __iomem
*base
)
381 if (!(mdio_bus
= mdiobus_alloc()))
386 spin_lock_init(&mdio_lock
);
387 mdio_bus
->name
= "CNS3xxx MII Bus";
388 mdio_bus
->read
= &cns3xxx_mdio_read
;
389 mdio_bus
->write
= &cns3xxx_mdio_write
;
390 strcpy(mdio_bus
->id
, "0");
392 if ((err
= mdiobus_register(mdio_bus
)))
393 mdiobus_free(mdio_bus
);
398 static void cns3xxx_mdio_remove(void)
400 mdiobus_unregister(mdio_bus
);
401 mdiobus_free(mdio_bus
);
404 static void enable_tx_dma(struct sw
*sw
)
406 __raw_writel(0x1, &sw
->regs
->ts_dma_ctrl0
);
409 static void enable_rx_dma(struct sw
*sw
)
411 __raw_writel(0x1, &sw
->regs
->fs_dma_ctrl0
);
414 static void cns3xxx_adjust_link(struct net_device
*dev
)
416 struct port
*port
= netdev_priv(dev
);
417 struct phy_device
*phydev
= port
->phydev
;
422 printk(KERN_INFO
"%s: link down\n", dev
->name
);
427 if (port
->speed
== phydev
->speed
&& port
->duplex
== phydev
->duplex
)
430 port
->speed
= phydev
->speed
;
431 port
->duplex
= phydev
->duplex
;
433 printk(KERN_INFO
"%s: link up, speed %u Mb/s, %s duplex\n",
434 dev
->name
, port
->speed
, port
->duplex
? "full" : "half");
437 static void eth_schedule_poll(struct sw
*sw
)
439 if (unlikely(!napi_schedule_prep(&sw
->napi
)))
442 disable_irq_nosync(sw
->rx_irq
);
443 __napi_schedule(&sw
->napi
);
446 irqreturn_t
eth_rx_irq(int irq
, void *pdev
)
448 struct net_device
*dev
= pdev
;
449 struct sw
*sw
= netdev_priv(dev
);
450 eth_schedule_poll(sw
);
451 return (IRQ_HANDLED
);
454 irqreturn_t
eth_stat_irq(int irq
, void *pdev
)
456 struct net_device
*dev
= pdev
;
457 struct sw
*sw
= netdev_priv(dev
);
459 u32 stat
= __raw_readl(&sw
->regs
->intr_stat
);
460 __raw_writel(0xffffffff, &sw
->regs
->intr_stat
);
462 if (stat
& MAC2_RX_ERROR
)
463 switch_port_tab
[3]->netdev
->stats
.rx_dropped
++;
464 if (stat
& MAC1_RX_ERROR
)
465 switch_port_tab
[1]->netdev
->stats
.rx_dropped
++;
466 if (stat
& MAC0_RX_ERROR
)
467 switch_port_tab
[0]->netdev
->stats
.rx_dropped
++;
469 if (stat
& MAC0_STATUS_CHANGE
) {
470 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[0]);
471 switch_port_tab
[0]->phydev
->link
= (cfg
& 0x1);
472 switch_port_tab
[0]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
473 if (((cfg
>> 2) & 0x3) == 2)
474 switch_port_tab
[0]->phydev
->speed
= 1000;
475 else if (((cfg
>> 2) & 0x3) == 1)
476 switch_port_tab
[0]->phydev
->speed
= 100;
478 switch_port_tab
[0]->phydev
->speed
= 10;
479 cns3xxx_adjust_link(switch_port_tab
[0]->netdev
);
482 if (stat
& MAC1_STATUS_CHANGE
) {
483 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[1]);
484 switch_port_tab
[1]->phydev
->link
= (cfg
& 0x1);
485 switch_port_tab
[1]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
486 if (((cfg
>> 2) & 0x3) == 2)
487 switch_port_tab
[1]->phydev
->speed
= 1000;
488 else if (((cfg
>> 2) & 0x3) == 1)
489 switch_port_tab
[1]->phydev
->speed
= 100;
491 switch_port_tab
[1]->phydev
->speed
= 10;
492 cns3xxx_adjust_link(switch_port_tab
[1]->netdev
);
495 if (stat
& MAC2_STATUS_CHANGE
) {
496 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[3]);
497 switch_port_tab
[3]->phydev
->link
= (cfg
& 0x1);
498 switch_port_tab
[3]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
499 if (((cfg
>> 2) & 0x3) == 2)
500 switch_port_tab
[3]->phydev
->speed
= 1000;
501 else if (((cfg
>> 2) & 0x3) == 1)
502 switch_port_tab
[3]->phydev
->speed
= 100;
504 switch_port_tab
[3]->phydev
->speed
= 10;
505 cns3xxx_adjust_link(switch_port_tab
[3]->netdev
);
508 return (IRQ_HANDLED
);
512 static void cns3xxx_alloc_rx_buf(struct sw
*sw
, int received
)
514 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
515 unsigned int i
= rx_ring
->alloc_index
;
516 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
520 for (received
+= rx_ring
->alloc_count
; received
> 0; received
--) {
521 buf
= napi_alloc_frag(RX_SEGMENT_ALLOC_SIZE
);
525 phys
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
526 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
527 if (dma_mapping_error(sw
->dev
, phys
)) {
532 desc
->sdl
= RX_SEGMENT_MRU
;
537 /* put the new buffer on RX-free queue */
538 rx_ring
->buff_tab
[i
] = buf
;
539 rx_ring
->phys_tab
[i
] = phys
;
541 if (i
== RX_DESCS
- 1) {
542 desc
->config0
= FIRST_SEGMENT
| LAST_SEGMENT
| RX_SEGMENT_MRU
| END_OF_RING
;
544 desc
= &(rx_ring
)->desc
[i
];
546 desc
->config0
= FIRST_SEGMENT
| LAST_SEGMENT
| RX_SEGMENT_MRU
;
552 rx_ring
->alloc_count
= received
;
553 rx_ring
->alloc_index
= i
;
556 static void eth_check_num_used(struct _tx_ring
*tx_ring
)
561 if (tx_ring
->num_used
>= TX_DESCS
- TX_DESC_RESERVE
)
564 if (tx_ring
->stopped
== stop
)
567 tx_ring
->stopped
= stop
;
569 for (i
= 0; i
< 4; i
++) {
570 struct port
*port
= switch_port_tab
[i
];
571 struct net_device
*dev
;
579 netif_stop_queue(dev
);
581 netif_wake_queue(dev
);
585 static void eth_complete_tx(struct sw
*sw
)
587 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
588 struct tx_desc
*desc
;
591 int num_used
= tx_ring
->num_used
;
594 index
= tx_ring
->free_index
;
595 desc
= &(tx_ring
)->desc
[index
];
597 for (i
= 0; i
< num_used
; i
++) {
601 skb
= tx_ring
->buff_tab
[index
];
602 tx_ring
->buff_tab
[index
] = 0;
605 dev_kfree_skb_any(skb
);
607 dma_unmap_single(sw
->dev
, tx_ring
->phys_tab
[index
], desc
->sdl
, DMA_TO_DEVICE
);
609 if (index
== TX_DESCS
- 1) {
611 desc
= &(tx_ring
)->desc
[index
];
618 tx_ring
->free_index
= index
;
619 tx_ring
->num_used
-= i
;
620 eth_check_num_used(tx_ring
);
623 static int eth_poll(struct napi_struct
*napi
, int budget
)
625 struct sw
*sw
= container_of(napi
, struct sw
, napi
);
626 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
629 unsigned int i
= rx_ring
->cur_index
;
630 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
631 unsigned int alloc_count
= rx_ring
->alloc_count
;
633 while (desc
->cown
&& alloc_count
+ received
< RX_DESCS
- 1) {
635 int reserve
= SKB_HEAD_ALIGN
;
637 if (received
>= budget
)
640 /* process received frame */
641 dma_unmap_single(sw
->dev
, rx_ring
->phys_tab
[i
], RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
643 skb
= build_skb(rx_ring
->buff_tab
[i
], RX_SEGMENT_ALLOC_SIZE
);
647 skb
->dev
= switch_port_tab
[desc
->sp
]->netdev
;
650 if (desc
->fsd
&& !desc
->lsd
)
651 length
= RX_SEGMENT_MRU
;
654 reserve
-= NET_IP_ALIGN
;
656 length
+= NET_IP_ALIGN
;
659 skb_reserve(skb
, reserve
);
660 skb_put(skb
, length
);
663 sw
->frag_first
= skb
;
665 if (sw
->frag_first
== sw
->frag_last
)
666 skb_shinfo(sw
->frag_first
)->frag_list
= skb
;
668 sw
->frag_last
->next
= skb
;
669 sw
->frag_first
->len
+= skb
->len
;
670 sw
->frag_first
->data_len
+= skb
->len
;
671 sw
->frag_first
->truesize
+= skb
->truesize
;
676 struct net_device
*dev
;
678 skb
= sw
->frag_first
;
680 skb
->protocol
= eth_type_trans(skb
, dev
);
682 dev
->stats
.rx_packets
++;
683 dev
->stats
.rx_bytes
+= skb
->len
;
685 /* RX Hardware checksum offload */
686 skb
->ip_summed
= CHECKSUM_NONE
;
687 switch (desc
->prot
) {
695 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
696 napi_gro_receive(napi
, skb
);
701 netif_receive_skb(skb
);
705 sw
->frag_first
= NULL
;
706 sw
->frag_last
= NULL
;
710 if (i
== RX_DESCS
- 1) {
712 desc
= &(rx_ring
)->desc
[i
];
719 rx_ring
->cur_index
= i
;
721 cns3xxx_alloc_rx_buf(sw
, received
);
725 if (received
< budget
&& napi_complete_done(napi
, received
)) {
726 enable_irq(sw
->rx_irq
);
729 spin_lock_bh(&tx_lock
);
731 spin_unlock_bh(&tx_lock
);
736 static void eth_set_desc(struct sw
*sw
, struct _tx_ring
*tx_ring
, int index
,
737 int index_last
, void *data
, int len
, u32 config0
,
740 struct tx_desc
*tx_desc
= &(tx_ring
)->desc
[index
];
743 phys
= dma_map_single(sw
->dev
, data
, len
, DMA_TO_DEVICE
);
745 tx_desc
->pmap
= pmap
;
746 tx_ring
->phys_tab
[index
] = phys
;
750 if (index
== TX_DESCS
- 1)
751 config0
|= END_OF_RING
;
753 if (index
== index_last
)
754 config0
|= LAST_SEGMENT
;
757 tx_desc
->config0
= config0
;
760 static int eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
762 struct port
*port
= netdev_priv(dev
);
763 struct sw
*sw
= port
->sw
;
764 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
765 struct sk_buff
*skb1
;
766 char pmap
= (1 << port
->id
);
767 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
768 int nr_desc
= nr_frags
;
769 int index0
, index
, index_last
;
777 skb_walk_frags(skb
, skb1
)
780 eth_schedule_poll(sw
);
781 spin_lock_bh(&tx_lock
);
783 if ((tx_ring
->num_used
+ nr_desc
+ 1) >= TX_DESCS
) {
784 spin_unlock_bh(&tx_lock
);
785 return NETDEV_TX_BUSY
;
788 index
= index0
= tx_ring
->cur_index
;
789 index_last
= (index0
+ nr_desc
) % TX_DESCS
;
790 tx_ring
->cur_index
= (index_last
+ 1) % TX_DESCS
;
792 spin_unlock_bh(&tx_lock
);
794 config0
= FORCE_ROUTE
;
795 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
796 config0
|= UDP_CHECKSUM
| TCP_CHECKSUM
;
801 for (i
= 0; i
< nr_frags
; i
++) {
802 struct skb_frag_struct
*frag
;
805 index
= (index
+ 1) % TX_DESCS
;
807 frag
= &skb_shinfo(skb
)->frags
[i
];
808 addr
= page_address(skb_frag_page(frag
)) + frag
->page_offset
;
810 eth_set_desc(sw
, tx_ring
, index
, index_last
, addr
, frag
->size
,
815 len0
= skb
->len
- skb
->data_len
;
817 skb_walk_frags(skb
, skb1
) {
818 index
= (index
+ 1) % TX_DESCS
;
821 eth_set_desc(sw
, tx_ring
, index
, index_last
, skb1
->data
,
822 skb1
->len
, config0
, pmap
);
825 tx_ring
->buff_tab
[index0
] = skb
;
826 eth_set_desc(sw
, tx_ring
, index0
, index_last
, skb
->data
, len0
,
827 config0
| FIRST_SEGMENT
, pmap
);
832 tx_ring
->num_used
+= nr_desc
+ 1;
833 spin_unlock(&tx_lock
);
835 dev
->stats
.tx_packets
++;
836 dev
->stats
.tx_bytes
+= skb
->len
;
843 static int eth_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
845 struct port
*port
= netdev_priv(dev
);
847 if (!netif_running(dev
))
849 return phy_mii_ioctl(port
->phydev
, req
, cmd
);
852 /* ethtool support */
854 static void cns3xxx_get_drvinfo(struct net_device
*dev
,
855 struct ethtool_drvinfo
*info
)
857 strcpy(info
->driver
, DRV_NAME
);
858 strcpy(info
->bus_info
, "internal");
861 static int cns3xxx_nway_reset(struct net_device
*dev
)
863 struct port
*port
= netdev_priv(dev
);
864 return phy_start_aneg(port
->phydev
);
867 static struct ethtool_ops cns3xxx_ethtool_ops
= {
868 .get_drvinfo
= cns3xxx_get_drvinfo
,
869 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
870 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
871 .nway_reset
= cns3xxx_nway_reset
,
872 .get_link
= ethtool_op_get_link
,
876 static int init_rings(struct sw
*sw
)
879 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
880 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
882 __raw_writel(0, &sw
->regs
->fs_dma_ctrl0
);
883 __raw_writel(TS_SUSPEND
| FS_SUSPEND
, &sw
->regs
->dma_auto_poll_cfg
);
884 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
885 __raw_writel(CLR_FS_STATE
| QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
886 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
888 rx_ring
->desc
= dmam_alloc_coherent(sw
->dev
, RX_POOL_ALLOC_SIZE
,
889 &rx_ring
->phys_addr
, GFP_KERNEL
);
893 /* Setup RX buffers */
894 memset(rx_ring
->desc
, 0, RX_POOL_ALLOC_SIZE
);
896 for (i
= 0; i
< RX_DESCS
; i
++) {
897 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
900 buf
= netdev_alloc_frag(RX_SEGMENT_ALLOC_SIZE
);
904 desc
->sdl
= RX_SEGMENT_MRU
;
906 if (i
== (RX_DESCS
- 1))
912 desc
->sdp
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
913 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
915 if (dma_mapping_error(sw
->dev
, desc
->sdp
))
918 rx_ring
->buff_tab
[i
] = buf
;
919 rx_ring
->phys_tab
[i
] = desc
->sdp
;
922 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_ptr0
);
923 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_base_addr0
);
925 tx_ring
->desc
= dmam_alloc_coherent(sw
->dev
, TX_POOL_ALLOC_SIZE
,
926 &tx_ring
->phys_addr
, GFP_KERNEL
);
930 /* Setup TX buffers */
931 memset(tx_ring
->desc
, 0, TX_POOL_ALLOC_SIZE
);
933 for (i
= 0; i
< TX_DESCS
; i
++) {
934 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
935 tx_ring
->buff_tab
[i
] = 0;
937 if (i
== (TX_DESCS
- 1))
942 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_ptr0
);
943 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_base_addr0
);
948 static void destroy_rings(struct sw
*sw
)
952 for (i
= 0; i
< RX_DESCS
; i
++) {
953 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
954 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
955 void *buf
= sw
->rx_ring
.buff_tab
[i
];
960 dma_unmap_single(sw
->dev
, desc
->sdp
, RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
964 for (i
= 0; i
< TX_DESCS
; i
++) {
965 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
966 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
967 struct sk_buff
*skb
= sw
->tx_ring
.buff_tab
[i
];
972 dma_unmap_single(sw
->dev
, desc
->sdp
, skb
->len
, DMA_TO_DEVICE
);
977 static int eth_open(struct net_device
*dev
)
979 struct port
*port
= netdev_priv(dev
);
980 struct sw
*sw
= port
->sw
;
983 port
->speed
= 0; /* force "link up" message */
984 phy_start(port
->phydev
);
986 netif_start_queue(dev
);
989 request_irq(sw
->rx_irq
, eth_rx_irq
, IRQF_SHARED
, "gig_switch", napi_dev
);
990 request_irq(sw
->stat_irq
, eth_stat_irq
, IRQF_SHARED
, "gig_stat", napi_dev
);
991 napi_enable(&sw
->napi
);
992 netif_start_queue(napi_dev
);
994 __raw_writel(~(MAC0_STATUS_CHANGE
| MAC1_STATUS_CHANGE
| MAC2_STATUS_CHANGE
|
995 MAC0_RX_ERROR
| MAC1_RX_ERROR
| MAC2_RX_ERROR
), &sw
->regs
->intr_mask
);
997 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
998 temp
&= ~(PORT_DISABLE
);
999 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1001 temp
= __raw_readl(&sw
->regs
->dma_auto_poll_cfg
);
1002 temp
&= ~(TS_SUSPEND
| FS_SUSPEND
);
1003 __raw_writel(temp
, &sw
->regs
->dma_auto_poll_cfg
);
1007 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1008 temp
&= ~(PORT_DISABLE
);
1009 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1012 netif_carrier_on(dev
);
1017 static int eth_close(struct net_device
*dev
)
1019 struct port
*port
= netdev_priv(dev
);
1020 struct sw
*sw
= port
->sw
;
1025 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1026 temp
|= (PORT_DISABLE
);
1027 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1029 netif_stop_queue(dev
);
1031 phy_stop(port
->phydev
);
1034 disable_irq(sw
->rx_irq
);
1035 free_irq(sw
->rx_irq
, napi_dev
);
1036 disable_irq(sw
->stat_irq
);
1037 free_irq(sw
->stat_irq
, napi_dev
);
1038 napi_disable(&sw
->napi
);
1039 netif_stop_queue(napi_dev
);
1040 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
1041 temp
|= (PORT_DISABLE
);
1042 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1044 __raw_writel(TS_SUSPEND
| FS_SUSPEND
,
1045 &sw
->regs
->dma_auto_poll_cfg
);
1048 netif_carrier_off(dev
);
1052 static void eth_rx_mode(struct net_device
*dev
)
1054 struct port
*port
= netdev_priv(dev
);
1055 struct sw
*sw
= port
->sw
;
1058 temp
= __raw_readl(&sw
->regs
->mac_glob_cfg
);
1060 if (dev
->flags
& IFF_PROMISC
) {
1062 temp
|= ((1 << 2) << PROMISC_OFFSET
);
1064 temp
|= ((1 << port
->id
) << PROMISC_OFFSET
);
1067 temp
&= ~((1 << 2) << PROMISC_OFFSET
);
1069 temp
&= ~((1 << port
->id
) << PROMISC_OFFSET
);
1071 __raw_writel(temp
, &sw
->regs
->mac_glob_cfg
);
1074 static int eth_set_mac(struct net_device
*netdev
, void *p
)
1076 struct port
*port
= netdev_priv(netdev
);
1077 struct sw
*sw
= port
->sw
;
1078 struct sockaddr
*addr
= p
;
1081 if (!is_valid_ether_addr(addr
->sa_data
))
1082 return -EADDRNOTAVAIL
;
1084 /* Invalidate old ARL Entry */
1086 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1088 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1089 __raw_writel( ((netdev
->dev_addr
[0] << 24) | (netdev
->dev_addr
[1] << 16) |
1090 (netdev
->dev_addr
[2] << 8) | (netdev
->dev_addr
[3])),
1091 &sw
->regs
->arl_ctrl
[1]);
1093 __raw_writel( ((netdev
->dev_addr
[4] << 24) | (netdev
->dev_addr
[5] << 16) |
1095 &sw
->regs
->arl_ctrl
[2]);
1096 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1098 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1105 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1108 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1110 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1111 __raw_writel( ((addr
->sa_data
[0] << 24) | (addr
->sa_data
[1] << 16) |
1112 (addr
->sa_data
[2] << 8) | (addr
->sa_data
[3])),
1113 &sw
->regs
->arl_ctrl
[1]);
1115 __raw_writel( ((addr
->sa_data
[4] << 24) | (addr
->sa_data
[5] << 16) |
1116 (7 << 4) | (1 << 1)), &sw
->regs
->arl_ctrl
[2]);
1117 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1119 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1127 static int cns3xxx_change_mtu(struct net_device
*dev
, int new_mtu
)
1129 if (new_mtu
> MAX_MTU
)
1136 static const struct net_device_ops cns3xxx_netdev_ops
= {
1137 .ndo_open
= eth_open
,
1138 .ndo_stop
= eth_close
,
1139 .ndo_start_xmit
= eth_xmit
,
1140 .ndo_set_rx_mode
= eth_rx_mode
,
1141 .ndo_do_ioctl
= eth_ioctl
,
1142 .ndo_change_mtu
= cns3xxx_change_mtu
,
1143 .ndo_set_mac_address
= eth_set_mac
,
1144 .ndo_validate_addr
= eth_validate_addr
,
1147 static int eth_init_one(struct platform_device
*pdev
)
1152 struct net_device
*dev
;
1153 struct cns3xxx_plat_info
*plat
= pdev
->dev
.platform_data
;
1154 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1157 struct resource
*res
;
1160 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1161 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1163 return PTR_ERR(regs
);
1165 err
= cns3xxx_mdio_register(regs
);
1169 if (!(napi_dev
= alloc_etherdev(sizeof(struct sw
)))) {
1171 goto err_remove_mdio
;
1174 strcpy(napi_dev
->name
, "cns3xxx_eth");
1175 napi_dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1177 SET_NETDEV_DEV(napi_dev
, &pdev
->dev
);
1178 sw
= netdev_priv(napi_dev
);
1179 memset(sw
, 0, sizeof(struct sw
));
1181 sw
->dev
= &pdev
->dev
;
1183 sw
->rx_irq
= platform_get_irq_byname(pdev
, "eth_rx");
1184 sw
->stat_irq
= platform_get_irq_byname(pdev
, "eth_stat");
1186 temp
= __raw_readl(&sw
->regs
->phy_auto_addr
);
1187 temp
|= (3 << 30); /* maximum frame length: 9600 bytes */
1188 __raw_writel(temp
, &sw
->regs
->phy_auto_addr
);
1190 for (i
= 0; i
< 4; i
++) {
1191 temp
= __raw_readl(&sw
->regs
->mac_cfg
[i
]);
1192 temp
|= (PORT_DISABLE
);
1193 __raw_writel(temp
, &sw
->regs
->mac_cfg
[i
]);
1196 temp
= PORT_DISABLE
;
1197 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1199 temp
= __raw_readl(&sw
->regs
->vlan_cfg
);
1200 temp
|= NIC_MODE
| VLAN_UNAWARE
;
1201 __raw_writel(temp
, &sw
->regs
->vlan_cfg
);
1203 __raw_writel(UNKNOWN_VLAN_TO_CPU
|
1204 CRC_STRIPPING
, &sw
->regs
->mac_glob_cfg
);
1206 if ((err
= init_rings(sw
)) != 0) {
1210 platform_set_drvdata(pdev
, napi_dev
);
1212 netif_napi_add(napi_dev
, &sw
->napi
, eth_poll
, NAPI_WEIGHT
);
1214 for (i
= 0; i
< 3; i
++) {
1215 if (!(plat
->ports
& (1 << i
))) {
1219 if (!(dev
= alloc_etherdev(sizeof(struct port
)))) {
1223 port
= netdev_priv(dev
);
1231 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1232 temp
|= (PORT_DISABLE
| PORT_BLOCK_STATE
| PORT_LEARN_DIS
);
1233 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1235 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1236 dev
->netdev_ops
= &cns3xxx_netdev_ops
;
1237 dev
->ethtool_ops
= &cns3xxx_ethtool_ops
;
1238 dev
->tx_queue_len
= 1000;
1239 dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1241 switch_port_tab
[port
->id
] = port
;
1242 memcpy(dev
->dev_addr
, &plat
->hwaddr
[i
], ETH_ALEN
);
1244 snprintf(phy_id
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, "0", plat
->phy
[i
]);
1245 port
->phydev
= phy_connect(dev
, phy_id
, &cns3xxx_adjust_link
,
1246 PHY_INTERFACE_MODE_RGMII
);
1247 if ((err
= IS_ERR(port
->phydev
))) {
1248 switch_port_tab
[port
->id
] = 0;
1253 port
->phydev
->irq
= PHY_IGNORE_INTERRUPT
;
1255 if ((err
= register_netdev(dev
))) {
1256 phy_disconnect(port
->phydev
);
1257 switch_port_tab
[port
->id
] = 0;
1262 printk(KERN_INFO
"%s: RGMII PHY %i on cns3xxx Switch\n", dev
->name
, plat
->phy
[i
]);
1263 netif_carrier_off(dev
);
1271 for (--i
; i
>= 0; i
--) {
1272 if (switch_port_tab
[i
]) {
1273 port
= switch_port_tab
[i
];
1275 unregister_netdev(dev
);
1276 phy_disconnect(port
->phydev
);
1277 switch_port_tab
[i
] = 0;
1282 free_netdev(napi_dev
);
1284 cns3xxx_mdio_remove();
1288 static int eth_remove_one(struct platform_device
*pdev
)
1290 struct net_device
*dev
= platform_get_drvdata(pdev
);
1291 struct sw
*sw
= netdev_priv(dev
);
1295 for (i
= 3; i
>= 0; i
--) {
1296 if (switch_port_tab
[i
]) {
1297 struct port
*port
= switch_port_tab
[i
];
1298 struct net_device
*dev
= port
->netdev
;
1299 unregister_netdev(dev
);
1300 phy_disconnect(port
->phydev
);
1301 switch_port_tab
[i
] = 0;
1306 free_netdev(napi_dev
);
1307 cns3xxx_mdio_remove();
1312 static struct platform_driver cns3xxx_eth_driver
= {
1313 .driver
.name
= DRV_NAME
,
1314 .probe
= eth_init_one
,
1315 .remove
= eth_remove_one
,
1318 static int __init
eth_init_module(void)
1320 return platform_driver_register(&cns3xxx_eth_driver
);
1323 static void __exit
eth_cleanup_module(void)
1325 platform_driver_unregister(&cns3xxx_eth_driver
);
1328 module_init(eth_init_module
);
1329 module_exit(eth_cleanup_module
);
1331 MODULE_AUTHOR("Chris Lang");
1332 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1333 MODULE_LICENSE("GPL v2");
1334 MODULE_ALIAS("platform:cns3xxx_eth");