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[openwrt/staging/yousong.git] / target / linux / cns3xxx / files / drivers / net / ethernet / cavium / cns3xxx_eth.c
1 /*
2 * Cavium CNS3xxx Gigabit driver for Linux
3 *
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
25
26 #define DRV_NAME "cns3xxx_eth"
27
28 #define RX_DESCS 256
29 #define TX_DESCS 128
30 #define TX_DESC_RESERVE 20
31
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
34 #define REGS_SIZE 336
35
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
38
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
43 #define MAX_MTU 9500
44
45 #define NAPI_WEIGHT 64
46
47 /* MDIO Defines */
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
53
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define IP_CHECKSUM 0x00040000
60 #define UDP_CHECKSUM 0x00020000
61 #define TCP_CHECKSUM 0x00010000
62
63 /* Port Config Defines */
64 #define PORT_BP_ENABLE 0x00020000
65 #define PORT_DISABLE 0x00040000
66 #define PORT_LEARN_DIS 0x00080000
67 #define PORT_BLOCK_STATE 0x00100000
68 #define PORT_BLOCK_MODE 0x00200000
69
70 #define PROMISC_OFFSET 29
71
72 /* Global Config Defines */
73 #define UNKNOWN_VLAN_TO_CPU 0x02000000
74 #define ACCEPT_CRC_PACKET 0x00200000
75 #define CRC_STRIPPING 0x00100000
76
77 /* VLAN Config Defines */
78 #define NIC_MODE 0x00008000
79 #define VLAN_UNAWARE 0x00000001
80
81 /* DMA AUTO Poll Defines */
82 #define TS_POLL_EN 0x00000020
83 #define TS_SUSPEND 0x00000010
84 #define FS_POLL_EN 0x00000002
85 #define FS_SUSPEND 0x00000001
86
87 /* DMA Ring Control Defines */
88 #define QUEUE_THRESHOLD 0x000000f0
89 #define CLR_FS_STATE 0x80000000
90
91 /* Interrupt Status Defines */
92 #define MAC0_STATUS_CHANGE 0x00004000
93 #define MAC1_STATUS_CHANGE 0x00008000
94 #define MAC2_STATUS_CHANGE 0x00010000
95 #define MAC0_RX_ERROR 0x00100000
96 #define MAC1_RX_ERROR 0x00200000
97 #define MAC2_RX_ERROR 0x00400000
98
99 struct tx_desc
100 {
101 u32 sdp; /* segment data pointer */
102
103 union {
104 struct {
105 u32 sdl:16; /* segment data length */
106 u32 tco:1;
107 u32 uco:1;
108 u32 ico:1;
109 u32 rsv_1:3; /* reserve */
110 u32 pri:3;
111 u32 fp:1; /* force priority */
112 u32 fr:1;
113 u32 interrupt:1;
114 u32 lsd:1;
115 u32 fsd:1;
116 u32 eor:1;
117 u32 cown:1;
118 };
119 u32 config0;
120 };
121
122 union {
123 struct {
124 u32 ctv:1;
125 u32 stv:1;
126 u32 sid:4;
127 u32 inss:1;
128 u32 dels:1;
129 u32 rsv_2:9;
130 u32 pmap:5;
131 u32 mark:3;
132 u32 ewan:1;
133 u32 fewan:1;
134 u32 rsv_3:5;
135 };
136 u32 config1;
137 };
138
139 union {
140 struct {
141 u32 c_vid:12;
142 u32 c_cfs:1;
143 u32 c_pri:3;
144 u32 s_vid:12;
145 u32 s_dei:1;
146 u32 s_pri:3;
147 };
148 u32 config2;
149 };
150
151 u8 alignment[16]; /* for 32 byte */
152 };
153
154 struct rx_desc
155 {
156 u32 sdp; /* segment data pointer */
157
158 union {
159 struct {
160 u32 sdl:16; /* segment data length */
161 u32 l4f:1;
162 u32 ipf:1;
163 u32 prot:4;
164 u32 hr:6;
165 u32 lsd:1;
166 u32 fsd:1;
167 u32 eor:1;
168 u32 cown:1;
169 };
170 u32 config0;
171 };
172
173 union {
174 struct {
175 u32 ctv:1;
176 u32 stv:1;
177 u32 unv:1;
178 u32 iwan:1;
179 u32 exdv:1;
180 u32 e_wan:1;
181 u32 rsv_1:2;
182 u32 sp:3;
183 u32 crc_err:1;
184 u32 un_eth:1;
185 u32 tc:2;
186 u32 rsv_2:1;
187 u32 ip_offset:5;
188 u32 rsv_3:11;
189 };
190 u32 config1;
191 };
192
193 union {
194 struct {
195 u32 c_vid:12;
196 u32 c_cfs:1;
197 u32 c_pri:3;
198 u32 s_vid:12;
199 u32 s_dei:1;
200 u32 s_pri:3;
201 };
202 u32 config2;
203 };
204
205 u8 alignment[16]; /* for 32 byte alignment */
206 };
207
208
209 struct switch_regs {
210 u32 phy_control;
211 u32 phy_auto_addr;
212 u32 mac_glob_cfg;
213 u32 mac_cfg[4];
214 u32 mac_pri_ctrl[5], __res;
215 u32 etype[2];
216 u32 udp_range[4];
217 u32 prio_etype_udp;
218 u32 prio_ipdscp[8];
219 u32 tc_ctrl;
220 u32 rate_ctrl;
221 u32 fc_glob_thrs;
222 u32 fc_port_thrs;
223 u32 mc_fc_glob_thrs;
224 u32 dc_glob_thrs;
225 u32 arl_vlan_cmd;
226 u32 arl_ctrl[3];
227 u32 vlan_cfg;
228 u32 pvid[2];
229 u32 vlan_ctrl[3];
230 u32 session_id[8];
231 u32 intr_stat;
232 u32 intr_mask;
233 u32 sram_test;
234 u32 mem_queue;
235 u32 farl_ctrl;
236 u32 fc_input_thrs, __res1[2];
237 u32 clk_skew_ctrl;
238 u32 mac_glob_cfg_ext, __res2[2];
239 u32 dma_ring_ctrl;
240 u32 dma_auto_poll_cfg;
241 u32 delay_intr_cfg, __res3;
242 u32 ts_dma_ctrl0;
243 u32 ts_desc_ptr0;
244 u32 ts_desc_base_addr0, __res4;
245 u32 fs_dma_ctrl0;
246 u32 fs_desc_ptr0;
247 u32 fs_desc_base_addr0, __res5;
248 u32 ts_dma_ctrl1;
249 u32 ts_desc_ptr1;
250 u32 ts_desc_base_addr1, __res6;
251 u32 fs_dma_ctrl1;
252 u32 fs_desc_ptr1;
253 u32 fs_desc_base_addr1;
254 u32 __res7[109];
255 u32 mac_counter0[13];
256 };
257
258 struct _tx_ring {
259 struct tx_desc *desc;
260 dma_addr_t phys_addr;
261 struct tx_desc *cur_addr;
262 struct sk_buff *buff_tab[TX_DESCS];
263 unsigned int phys_tab[TX_DESCS];
264 u32 free_index;
265 u32 count_index;
266 u32 cur_index;
267 int num_used;
268 int num_count;
269 bool stopped;
270 };
271
272 struct _rx_ring {
273 struct rx_desc *desc;
274 dma_addr_t phys_addr;
275 struct rx_desc *cur_addr;
276 void *buff_tab[RX_DESCS];
277 unsigned int phys_tab[RX_DESCS];
278 u32 cur_index;
279 u32 alloc_index;
280 int alloc_count;
281 };
282
283 struct sw {
284 struct switch_regs __iomem *regs;
285 struct napi_struct napi;
286 struct cns3xxx_plat_info *plat;
287 struct _tx_ring tx_ring;
288 struct _rx_ring rx_ring;
289 struct sk_buff *frag_first;
290 struct sk_buff *frag_last;
291 struct device *dev;
292 int rx_irq;
293 int stat_irq;
294 };
295
296 struct port {
297 struct net_device *netdev;
298 struct phy_device *phydev;
299 struct sw *sw;
300 int id; /* logical port ID */
301 int speed, duplex;
302 };
303
304 static spinlock_t mdio_lock;
305 static DEFINE_SPINLOCK(tx_lock);
306 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
307 struct mii_bus *mdio_bus;
308 static int ports_open;
309 static struct port *switch_port_tab[4];
310 static struct dma_pool *rx_dma_pool;
311 static struct dma_pool *tx_dma_pool;
312 struct net_device *napi_dev;
313
314 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
315 int write, u16 cmd)
316 {
317 int cycles = 0;
318 u32 temp = 0;
319
320 temp = __raw_readl(&mdio_regs->phy_control);
321 temp |= MDIO_CMD_COMPLETE;
322 __raw_writel(temp, &mdio_regs->phy_control);
323 udelay(10);
324
325 if (write) {
326 temp = (cmd << MDIO_VALUE_OFFSET);
327 temp |= MDIO_WRITE_COMMAND;
328 } else {
329 temp = MDIO_READ_COMMAND;
330 }
331 temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
332 temp |= (phy_id & 0x1f);
333
334 __raw_writel(temp, &mdio_regs->phy_control);
335
336 while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
337 && cycles < 5000) {
338 udelay(1);
339 cycles++;
340 }
341
342 if (cycles == 5000) {
343 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name,
344 phy_id);
345 return -1;
346 }
347
348 temp = __raw_readl(&mdio_regs->phy_control);
349 temp |= MDIO_CMD_COMPLETE;
350 __raw_writel(temp, &mdio_regs->phy_control);
351
352 if (write)
353 return 0;
354
355 return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
356 }
357
358 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
359 {
360 unsigned long flags;
361 int ret;
362
363 spin_lock_irqsave(&mdio_lock, flags);
364 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
365 spin_unlock_irqrestore(&mdio_lock, flags);
366 return ret;
367 }
368
369 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
370 u16 val)
371 {
372 unsigned long flags;
373 int ret;
374
375 spin_lock_irqsave(&mdio_lock, flags);
376 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
377 spin_unlock_irqrestore(&mdio_lock, flags);
378 return ret;
379 }
380
381 static int cns3xxx_mdio_register(void __iomem *base)
382 {
383 int err;
384
385 if (!(mdio_bus = mdiobus_alloc()))
386 return -ENOMEM;
387
388 mdio_regs = base;
389
390 spin_lock_init(&mdio_lock);
391 mdio_bus->name = "CNS3xxx MII Bus";
392 mdio_bus->read = &cns3xxx_mdio_read;
393 mdio_bus->write = &cns3xxx_mdio_write;
394 strcpy(mdio_bus->id, "0");
395
396 if ((err = mdiobus_register(mdio_bus)))
397 mdiobus_free(mdio_bus);
398 return err;
399 }
400
401 static void cns3xxx_mdio_remove(void)
402 {
403 mdiobus_unregister(mdio_bus);
404 mdiobus_free(mdio_bus);
405 }
406
407 static void enable_tx_dma(struct sw *sw)
408 {
409 __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
410 }
411
412 static void enable_rx_dma(struct sw *sw)
413 {
414 __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
415 }
416
417 static void cns3xxx_adjust_link(struct net_device *dev)
418 {
419 struct port *port = netdev_priv(dev);
420 struct phy_device *phydev = port->phydev;
421
422 if (!phydev->link) {
423 if (port->speed) {
424 port->speed = 0;
425 printk(KERN_INFO "%s: link down\n", dev->name);
426 }
427 return;
428 }
429
430 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
431 return;
432
433 port->speed = phydev->speed;
434 port->duplex = phydev->duplex;
435
436 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
437 dev->name, port->speed, port->duplex ? "full" : "half");
438 }
439
440 static void eth_schedule_poll(struct sw *sw)
441 {
442 if (unlikely(!napi_schedule_prep(&sw->napi)))
443 return;
444
445 disable_irq_nosync(sw->rx_irq);
446 __napi_schedule(&sw->napi);
447 }
448
449 irqreturn_t eth_rx_irq(int irq, void *pdev)
450 {
451 struct net_device *dev = pdev;
452 struct sw *sw = netdev_priv(dev);
453 eth_schedule_poll(sw);
454 return (IRQ_HANDLED);
455 }
456
457 irqreturn_t eth_stat_irq(int irq, void *pdev)
458 {
459 struct net_device *dev = pdev;
460 struct sw *sw = netdev_priv(dev);
461 u32 cfg;
462 u32 stat = __raw_readl(&sw->regs->intr_stat);
463 __raw_writel(0xffffffff, &sw->regs->intr_stat);
464
465 if (stat & MAC2_RX_ERROR)
466 switch_port_tab[3]->netdev->stats.rx_dropped++;
467 if (stat & MAC1_RX_ERROR)
468 switch_port_tab[1]->netdev->stats.rx_dropped++;
469 if (stat & MAC0_RX_ERROR)
470 switch_port_tab[0]->netdev->stats.rx_dropped++;
471
472 if (stat & MAC0_STATUS_CHANGE) {
473 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
474 switch_port_tab[0]->phydev->link = (cfg & 0x1);
475 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
476 if (((cfg >> 2) & 0x3) == 2)
477 switch_port_tab[0]->phydev->speed = 1000;
478 else if (((cfg >> 2) & 0x3) == 1)
479 switch_port_tab[0]->phydev->speed = 100;
480 else
481 switch_port_tab[0]->phydev->speed = 10;
482 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
483 }
484
485 if (stat & MAC1_STATUS_CHANGE) {
486 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
487 switch_port_tab[1]->phydev->link = (cfg & 0x1);
488 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
489 if (((cfg >> 2) & 0x3) == 2)
490 switch_port_tab[1]->phydev->speed = 1000;
491 else if (((cfg >> 2) & 0x3) == 1)
492 switch_port_tab[1]->phydev->speed = 100;
493 else
494 switch_port_tab[1]->phydev->speed = 10;
495 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
496 }
497
498 if (stat & MAC2_STATUS_CHANGE) {
499 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
500 switch_port_tab[3]->phydev->link = (cfg & 0x1);
501 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
502 if (((cfg >> 2) & 0x3) == 2)
503 switch_port_tab[3]->phydev->speed = 1000;
504 else if (((cfg >> 2) & 0x3) == 1)
505 switch_port_tab[3]->phydev->speed = 100;
506 else
507 switch_port_tab[3]->phydev->speed = 10;
508 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
509 }
510
511 return (IRQ_HANDLED);
512 }
513
514
515 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
516 {
517 struct _rx_ring *rx_ring = &sw->rx_ring;
518 unsigned int i = rx_ring->alloc_index;
519 struct rx_desc *desc = &(rx_ring)->desc[i];
520 void *buf;
521 unsigned int phys;
522
523 for (received += rx_ring->alloc_count; received > 0; received--) {
524 buf = kmalloc(RX_SEGMENT_ALLOC_SIZE, GFP_ATOMIC);
525 if (!buf)
526 break;
527
528 phys = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
529 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
530 if (dma_mapping_error(sw->dev, phys)) {
531 kfree(buf);
532 break;
533 }
534
535 desc->sdl = RX_SEGMENT_MRU;
536 desc->sdp = phys;
537
538 wmb();
539
540 /* put the new buffer on RX-free queue */
541 rx_ring->buff_tab[i] = buf;
542 rx_ring->phys_tab[i] = phys;
543 if (i == RX_DESCS - 1) {
544 i = 0;
545 desc->config0 = END_OF_RING | FIRST_SEGMENT |
546 LAST_SEGMENT | RX_SEGMENT_MRU;
547 desc = &(rx_ring)->desc[i];
548 } else {
549 desc->config0 = FIRST_SEGMENT | LAST_SEGMENT |
550 RX_SEGMENT_MRU;
551 i++;
552 desc++;
553 }
554 }
555
556 rx_ring->alloc_count = received;
557 rx_ring->alloc_index = i;
558 }
559
560 static void eth_check_num_used(struct _tx_ring *tx_ring)
561 {
562 bool stop = false;
563 int i;
564
565 if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
566 stop = true;
567
568 if (tx_ring->stopped == stop)
569 return;
570
571 tx_ring->stopped = stop;
572 for (i = 0; i < 4; i++) {
573 struct port *port = switch_port_tab[i];
574 struct net_device *dev;
575
576 if (!port)
577 continue;
578
579 dev = port->netdev;
580 if (stop)
581 netif_stop_queue(dev);
582 else
583 netif_wake_queue(dev);
584 }
585 }
586
587 static void eth_complete_tx(struct sw *sw)
588 {
589 struct _tx_ring *tx_ring = &sw->tx_ring;
590 struct tx_desc *desc;
591 int i;
592 int index;
593 int num_used = tx_ring->num_used;
594 struct sk_buff *skb;
595
596 index = tx_ring->free_index;
597 desc = &(tx_ring)->desc[index];
598 for (i = 0; i < num_used; i++) {
599 if (desc->cown) {
600 skb = tx_ring->buff_tab[index];
601 tx_ring->buff_tab[index] = 0;
602 if (skb)
603 dev_kfree_skb_any(skb);
604 dma_unmap_single(sw->dev, tx_ring->phys_tab[index],
605 desc->sdl, DMA_TO_DEVICE);
606 if (++index == TX_DESCS) {
607 index = 0;
608 desc = &(tx_ring)->desc[index];
609 } else {
610 desc++;
611 }
612 } else {
613 break;
614 }
615 }
616 tx_ring->free_index = index;
617 tx_ring->num_used -= i;
618 eth_check_num_used(tx_ring);
619 }
620
621 static int eth_poll(struct napi_struct *napi, int budget)
622 {
623 struct sw *sw = container_of(napi, struct sw, napi);
624 struct _rx_ring *rx_ring = &sw->rx_ring;
625 int received = 0;
626 unsigned int length;
627 unsigned int i = rx_ring->cur_index;
628 struct rx_desc *desc = &(rx_ring)->desc[i];
629 unsigned int alloc_count = rx_ring->alloc_count;
630
631 while (desc->cown && alloc_count + received < RX_DESCS - 1) {
632 struct sk_buff *skb;
633 int reserve = SKB_HEAD_ALIGN;
634
635 if (received >= budget)
636 break;
637
638 /* process received frame */
639 dma_unmap_single(sw->dev, rx_ring->phys_tab[i],
640 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
641
642 skb = build_skb(rx_ring->buff_tab[i], 0);
643 if (!skb)
644 break;
645
646 skb->dev = switch_port_tab[desc->sp]->netdev;
647
648 length = desc->sdl;
649 if (desc->fsd && !desc->lsd)
650 length = RX_SEGMENT_MRU;
651
652 if (!desc->fsd) {
653 reserve -= NET_IP_ALIGN;
654 if (!desc->lsd)
655 length += NET_IP_ALIGN;
656 }
657
658 skb_reserve(skb, reserve);
659 skb_put(skb, length);
660
661 if (!sw->frag_first)
662 sw->frag_first = skb;
663 else {
664 if (sw->frag_first == sw->frag_last)
665 skb_frag_add_head(sw->frag_first, skb);
666 else
667 sw->frag_last->next = skb;
668 sw->frag_first->len += skb->len;
669 sw->frag_first->data_len += skb->len;
670 sw->frag_first->truesize += skb->truesize;
671 }
672 sw->frag_last = skb;
673
674 if (desc->lsd) {
675 struct net_device *dev;
676
677 skb = sw->frag_first;
678 dev = skb->dev;
679 skb->protocol = eth_type_trans(skb, dev);
680
681 dev->stats.rx_packets++;
682 dev->stats.rx_bytes += skb->len;
683
684 /* RX Hardware checksum offload */
685 skb->ip_summed = CHECKSUM_NONE;
686 switch (desc->prot) {
687 case 1:
688 case 2:
689 case 5:
690 case 6:
691 case 13:
692 case 14:
693 if (!desc->l4f) {
694 skb->ip_summed = CHECKSUM_UNNECESSARY;
695 napi_gro_receive(napi, skb);
696 break;
697 }
698 /* fall through */
699 default:
700 netif_receive_skb(skb);
701 break;
702 }
703
704 sw->frag_first = NULL;
705 sw->frag_last = NULL;
706 }
707
708 received++;
709 if (++i == RX_DESCS) {
710 i = 0;
711 desc = &(rx_ring)->desc[i];
712 } else {
713 desc++;
714 }
715 }
716
717 rx_ring->cur_index = i;
718 if (!received) {
719 napi_complete(napi);
720 enable_irq(sw->rx_irq);
721
722 /* if rx descriptors are full schedule another poll */
723 if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
724 eth_schedule_poll(sw);
725 }
726
727 spin_lock_bh(&tx_lock);
728 eth_complete_tx(sw);
729 spin_unlock_bh(&tx_lock);
730
731 cns3xxx_alloc_rx_buf(sw, received);
732
733 wmb();
734 enable_rx_dma(sw);
735
736 return received;
737 }
738
739 static void eth_set_desc(struct sw *sw, struct _tx_ring *tx_ring, int index,
740 int index_last, void *data, int len, u32 config0,
741 u32 pmap)
742 {
743 struct tx_desc *tx_desc = &(tx_ring)->desc[index];
744 unsigned int phys;
745
746 phys = dma_map_single(sw->dev, data, len, DMA_TO_DEVICE);
747 tx_desc->sdp = phys;
748 tx_desc->pmap = pmap;
749 tx_ring->phys_tab[index] = phys;
750
751 config0 |= len;
752 if (index == TX_DESCS - 1)
753 config0 |= END_OF_RING;
754 if (index == index_last)
755 config0 |= LAST_SEGMENT;
756
757 wmb();
758 tx_desc->config0 = config0;
759 }
760
761 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
762 {
763 struct port *port = netdev_priv(dev);
764 struct sw *sw = port->sw;
765 struct _tx_ring *tx_ring = &sw->tx_ring;
766 struct sk_buff *skb1;
767 char pmap = (1 << port->id);
768 int nr_frags = skb_shinfo(skb)->nr_frags;
769 int nr_desc = nr_frags;
770 int index0, index, index_last;
771 int len0;
772 unsigned int i;
773 u32 config0;
774
775 if (pmap == 8)
776 pmap = (1 << 4);
777
778 skb_walk_frags(skb, skb1)
779 nr_desc++;
780
781 eth_schedule_poll(sw);
782 spin_lock_bh(&tx_lock);
783 if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
784 spin_unlock_bh(&tx_lock);
785 return NETDEV_TX_BUSY;
786 }
787
788 index = index0 = tx_ring->cur_index;
789 index_last = (index0 + nr_desc) % TX_DESCS;
790 tx_ring->cur_index = (index_last + 1) % TX_DESCS;
791
792 spin_unlock_bh(&tx_lock);
793
794 config0 = FORCE_ROUTE;
795 if (skb->ip_summed == CHECKSUM_PARTIAL)
796 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
797
798 len0 = skb->len;
799
800 /* fragments */
801 for (i = 0; i < nr_frags; i++) {
802 struct skb_frag_struct *frag;
803 void *addr;
804
805 index = (index + 1) % TX_DESCS;
806
807 frag = &skb_shinfo(skb)->frags[i];
808 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
809
810 eth_set_desc(sw, tx_ring, index, index_last, addr, frag->size,
811 config0, pmap);
812 }
813
814 if (nr_frags)
815 len0 = skb->len - skb->data_len;
816
817 skb_walk_frags(skb, skb1) {
818 index = (index + 1) % TX_DESCS;
819 len0 -= skb1->len;
820
821 eth_set_desc(sw, tx_ring, index, index_last, skb1->data,
822 skb1->len, config0, pmap);
823 }
824
825 tx_ring->buff_tab[index0] = skb;
826 eth_set_desc(sw, tx_ring, index0, index_last, skb->data, len0,
827 config0 | FIRST_SEGMENT, pmap);
828
829 wmb();
830
831 spin_lock(&tx_lock);
832 tx_ring->num_used += nr_desc + 1;
833 spin_unlock(&tx_lock);
834
835 dev->stats.tx_packets++;
836 dev->stats.tx_bytes += skb->len;
837
838 enable_tx_dma(sw);
839
840 return NETDEV_TX_OK;
841 }
842
843 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
844 {
845 struct port *port = netdev_priv(dev);
846
847 if (!netif_running(dev))
848 return -EINVAL;
849 return phy_mii_ioctl(port->phydev, req, cmd);
850 }
851
852 /* ethtool support */
853
854 static void cns3xxx_get_drvinfo(struct net_device *dev,
855 struct ethtool_drvinfo *info)
856 {
857 strcpy(info->driver, DRV_NAME);
858 strcpy(info->bus_info, "internal");
859 }
860
861 static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
862 {
863 struct port *port = netdev_priv(dev);
864 return phy_ethtool_gset(port->phydev, cmd);
865 }
866
867 static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
868 {
869 struct port *port = netdev_priv(dev);
870 return phy_ethtool_sset(port->phydev, cmd);
871 }
872
873 static int cns3xxx_nway_reset(struct net_device *dev)
874 {
875 struct port *port = netdev_priv(dev);
876 return phy_start_aneg(port->phydev);
877 }
878
879 static struct ethtool_ops cns3xxx_ethtool_ops = {
880 .get_drvinfo = cns3xxx_get_drvinfo,
881 .get_settings = cns3xxx_get_settings,
882 .set_settings = cns3xxx_set_settings,
883 .nway_reset = cns3xxx_nway_reset,
884 .get_link = ethtool_op_get_link,
885 };
886
887
888 static int init_rings(struct sw *sw)
889 {
890 int i;
891 struct _rx_ring *rx_ring = &sw->rx_ring;
892 struct _tx_ring *tx_ring = &sw->tx_ring;
893
894 __raw_writel(0, &sw->regs->fs_dma_ctrl0);
895 __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
896 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
897 __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
898
899 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
900
901 if (!(rx_dma_pool = dma_pool_create(DRV_NAME, sw->dev,
902 RX_POOL_ALLOC_SIZE, 32, 0)))
903 return -ENOMEM;
904
905 if (!(rx_ring->desc = dma_pool_alloc(rx_dma_pool, GFP_KERNEL,
906 &rx_ring->phys_addr)))
907 return -ENOMEM;
908 memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
909
910 /* Setup RX buffers */
911 for (i = 0; i < RX_DESCS; i++) {
912 struct rx_desc *desc = &(rx_ring)->desc[i];
913 void *buf;
914
915 buf = kzalloc(RX_SEGMENT_ALLOC_SIZE, GFP_KERNEL);
916 if (!buf)
917 return -ENOMEM;
918
919 desc->sdl = RX_SEGMENT_MRU;
920 if (i == (RX_DESCS - 1))
921 desc->eor = 1;
922 desc->fsd = 1;
923 desc->lsd = 1;
924
925 desc->sdp = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
926 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
927 if (dma_mapping_error(sw->dev, desc->sdp))
928 return -EIO;
929
930 rx_ring->buff_tab[i] = buf;
931 rx_ring->phys_tab[i] = desc->sdp;
932 desc->cown = 0;
933 }
934 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
935 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
936
937 if (!(tx_dma_pool = dma_pool_create(DRV_NAME, sw->dev,
938 TX_POOL_ALLOC_SIZE, 32, 0)))
939 return -ENOMEM;
940
941 if (!(tx_ring->desc = dma_pool_alloc(tx_dma_pool, GFP_KERNEL,
942 &tx_ring->phys_addr)))
943 return -ENOMEM;
944 memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
945
946 /* Setup TX buffers */
947 for (i = 0; i < TX_DESCS; i++) {
948 struct tx_desc *desc = &(tx_ring)->desc[i];
949 tx_ring->buff_tab[i] = 0;
950
951 if (i == (TX_DESCS - 1))
952 desc->eor = 1;
953 desc->cown = 1;
954 }
955 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
956 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
957
958 return 0;
959 }
960
961 static void destroy_rings(struct sw *sw)
962 {
963 int i;
964 if (sw->rx_ring.desc) {
965 for (i = 0; i < RX_DESCS; i++) {
966 struct _rx_ring *rx_ring = &sw->rx_ring;
967 struct rx_desc *desc = &(rx_ring)->desc[i];
968 struct sk_buff *skb = sw->rx_ring.buff_tab[i];
969
970 if (!skb)
971 continue;
972
973 dma_unmap_single(sw->dev, desc->sdp, RX_SEGMENT_MRU,
974 DMA_FROM_DEVICE);
975 dev_kfree_skb(skb);
976 }
977 dma_pool_free(rx_dma_pool, sw->rx_ring.desc, sw->rx_ring.phys_addr);
978 dma_pool_destroy(rx_dma_pool);
979 rx_dma_pool = 0;
980 sw->rx_ring.desc = 0;
981 }
982 if (sw->tx_ring.desc) {
983 for (i = 0; i < TX_DESCS; i++) {
984 struct _tx_ring *tx_ring = &sw->tx_ring;
985 struct tx_desc *desc = &(tx_ring)->desc[i];
986 struct sk_buff *skb = sw->tx_ring.buff_tab[i];
987 if (skb) {
988 dma_unmap_single(sw->dev, desc->sdp,
989 skb->len, DMA_TO_DEVICE);
990 dev_kfree_skb(skb);
991 }
992 }
993 dma_pool_free(tx_dma_pool, sw->tx_ring.desc, sw->tx_ring.phys_addr);
994 dma_pool_destroy(tx_dma_pool);
995 tx_dma_pool = 0;
996 sw->tx_ring.desc = 0;
997 }
998 }
999
1000 static int eth_open(struct net_device *dev)
1001 {
1002 struct port *port = netdev_priv(dev);
1003 struct sw *sw = port->sw;
1004 u32 temp;
1005
1006 port->speed = 0; /* force "link up" message */
1007 phy_start(port->phydev);
1008
1009 netif_start_queue(dev);
1010
1011 if (!ports_open) {
1012 request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
1013 request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
1014 napi_enable(&sw->napi);
1015 netif_start_queue(napi_dev);
1016
1017 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
1018 MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
1019
1020 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1021 temp &= ~(PORT_DISABLE);
1022 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1023
1024 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
1025 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1026 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1027
1028 enable_rx_dma(sw);
1029 }
1030 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1031 temp &= ~(PORT_DISABLE);
1032 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1033
1034 ports_open++;
1035 netif_carrier_on(dev);
1036
1037 return 0;
1038 }
1039
1040 static int eth_close(struct net_device *dev)
1041 {
1042 struct port *port = netdev_priv(dev);
1043 struct sw *sw = port->sw;
1044 u32 temp;
1045
1046 ports_open--;
1047
1048 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1049 temp |= (PORT_DISABLE);
1050 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1051
1052 netif_stop_queue(dev);
1053
1054 phy_stop(port->phydev);
1055
1056 if (!ports_open) {
1057 disable_irq(sw->rx_irq);
1058 free_irq(sw->rx_irq, napi_dev);
1059 disable_irq(sw->stat_irq);
1060 free_irq(sw->stat_irq, napi_dev);
1061 napi_disable(&sw->napi);
1062 netif_stop_queue(napi_dev);
1063 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1064 temp |= (PORT_DISABLE);
1065 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1066
1067 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1068 &sw->regs->dma_auto_poll_cfg);
1069 }
1070
1071 netif_carrier_off(dev);
1072 return 0;
1073 }
1074
1075 static void eth_rx_mode(struct net_device *dev)
1076 {
1077 struct port *port = netdev_priv(dev);
1078 struct sw *sw = port->sw;
1079 u32 temp;
1080
1081 temp = __raw_readl(&sw->regs->mac_glob_cfg);
1082
1083 if (dev->flags & IFF_PROMISC) {
1084 if (port->id == 3)
1085 temp |= ((1 << 2) << PROMISC_OFFSET);
1086 else
1087 temp |= ((1 << port->id) << PROMISC_OFFSET);
1088 } else {
1089 if (port->id == 3)
1090 temp &= ~((1 << 2) << PROMISC_OFFSET);
1091 else
1092 temp &= ~((1 << port->id) << PROMISC_OFFSET);
1093 }
1094 __raw_writel(temp, &sw->regs->mac_glob_cfg);
1095 }
1096
1097 static int eth_set_mac(struct net_device *netdev, void *p)
1098 {
1099 struct port *port = netdev_priv(netdev);
1100 struct sw *sw = port->sw;
1101 struct sockaddr *addr = p;
1102 u32 cycles = 0;
1103
1104 if (!is_valid_ether_addr(addr->sa_data))
1105 return -EADDRNOTAVAIL;
1106
1107 /* Invalidate old ARL Entry */
1108 if (port->id == 3)
1109 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1110 else
1111 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1112 __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1113 (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1114 &sw->regs->arl_ctrl[1]);
1115
1116 __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1117 (1 << 1)),
1118 &sw->regs->arl_ctrl[2]);
1119 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1120
1121 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1122 && cycles < 5000) {
1123 udelay(1);
1124 cycles++;
1125 }
1126
1127 cycles = 0;
1128 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1129
1130 if (port->id == 3)
1131 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1132 else
1133 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1134 __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1135 (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1136 &sw->regs->arl_ctrl[1]);
1137
1138 __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1139 (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1140 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1141
1142 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1143 && cycles < 5000) {
1144 udelay(1);
1145 cycles++;
1146 }
1147 return 0;
1148 }
1149
1150 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1151 {
1152 if (new_mtu > MAX_MTU)
1153 return -EINVAL;
1154
1155 dev->mtu = new_mtu;
1156 return 0;
1157 }
1158
1159 static const struct net_device_ops cns3xxx_netdev_ops = {
1160 .ndo_open = eth_open,
1161 .ndo_stop = eth_close,
1162 .ndo_start_xmit = eth_xmit,
1163 .ndo_set_rx_mode = eth_rx_mode,
1164 .ndo_do_ioctl = eth_ioctl,
1165 .ndo_change_mtu = cns3xxx_change_mtu,
1166 .ndo_set_mac_address = eth_set_mac,
1167 .ndo_validate_addr = eth_validate_addr,
1168 };
1169
1170 static int eth_init_one(struct platform_device *pdev)
1171 {
1172 int i;
1173 struct port *port;
1174 struct sw *sw;
1175 struct net_device *dev;
1176 struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1177 char phy_id[MII_BUS_ID_SIZE + 3];
1178 int err;
1179 u32 temp;
1180 struct resource *res;
1181 void __iomem *regs;
1182
1183 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184 regs = devm_ioremap_resource(&pdev->dev, res);
1185 if (IS_ERR(regs))
1186 return PTR_ERR(regs);
1187
1188 err = cns3xxx_mdio_register(regs);
1189 if (err)
1190 return err;
1191
1192 if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
1193 err = -ENOMEM;
1194 goto err_remove_mdio;
1195 }
1196
1197 strcpy(napi_dev->name, "switch%d");
1198 napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1199
1200 SET_NETDEV_DEV(napi_dev, &pdev->dev);
1201 sw = netdev_priv(napi_dev);
1202 memset(sw, 0, sizeof(struct sw));
1203 sw->regs = regs;
1204 sw->dev = &pdev->dev;
1205
1206 sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
1207 sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
1208
1209 temp = __raw_readl(&sw->regs->phy_auto_addr);
1210 temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1211 __raw_writel(temp, &sw->regs->phy_auto_addr);
1212
1213 for (i = 0; i < 4; i++) {
1214 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1215 temp |= (PORT_DISABLE);
1216 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1217 }
1218
1219 temp = PORT_DISABLE;
1220 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1221
1222 temp = __raw_readl(&sw->regs->vlan_cfg);
1223 temp |= NIC_MODE | VLAN_UNAWARE;
1224 __raw_writel(temp, &sw->regs->vlan_cfg);
1225
1226 __raw_writel(UNKNOWN_VLAN_TO_CPU |
1227 CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1228
1229 if ((err = init_rings(sw)) != 0) {
1230 destroy_rings(sw);
1231 err = -ENOMEM;
1232 goto err_free;
1233 }
1234 platform_set_drvdata(pdev, napi_dev);
1235
1236 netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1237
1238 for (i = 0; i < 3; i++) {
1239 if (!(plat->ports & (1 << i))) {
1240 continue;
1241 }
1242
1243 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1244 goto free_ports;
1245 }
1246
1247 port = netdev_priv(dev);
1248 port->netdev = dev;
1249 if (i == 2)
1250 port->id = 3;
1251 else
1252 port->id = i;
1253 port->sw = sw;
1254
1255 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1256 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1257 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1258
1259 dev->netdev_ops = &cns3xxx_netdev_ops;
1260 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1261 dev->tx_queue_len = 1000;
1262 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1263
1264 switch_port_tab[port->id] = port;
1265 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1266
1267 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1268 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
1269 PHY_INTERFACE_MODE_RGMII);
1270 if ((err = IS_ERR(port->phydev))) {
1271 switch_port_tab[port->id] = 0;
1272 free_netdev(dev);
1273 goto free_ports;
1274 }
1275
1276 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1277
1278 if ((err = register_netdev(dev))) {
1279 phy_disconnect(port->phydev);
1280 switch_port_tab[port->id] = 0;
1281 free_netdev(dev);
1282 goto free_ports;
1283 }
1284
1285 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1286 netif_carrier_off(dev);
1287 dev = 0;
1288 }
1289
1290 return 0;
1291
1292 free_ports:
1293 err = -ENOMEM;
1294 for (--i; i >= 0; i--) {
1295 if (switch_port_tab[i]) {
1296 port = switch_port_tab[i];
1297 dev = port->netdev;
1298 unregister_netdev(dev);
1299 phy_disconnect(port->phydev);
1300 switch_port_tab[i] = 0;
1301 free_netdev(dev);
1302 }
1303 }
1304 err_free:
1305 free_netdev(napi_dev);
1306 err_remove_mdio:
1307 cns3xxx_mdio_remove();
1308 return err;
1309 }
1310
1311 static int eth_remove_one(struct platform_device *pdev)
1312 {
1313 struct net_device *dev = platform_get_drvdata(pdev);
1314 struct sw *sw = netdev_priv(dev);
1315 int i;
1316 destroy_rings(sw);
1317
1318 for (i = 3; i >= 0; i--) {
1319 if (switch_port_tab[i]) {
1320 struct port *port = switch_port_tab[i];
1321 struct net_device *dev = port->netdev;
1322 unregister_netdev(dev);
1323 phy_disconnect(port->phydev);
1324 switch_port_tab[i] = 0;
1325 free_netdev(dev);
1326 }
1327 }
1328
1329 free_netdev(napi_dev);
1330 cns3xxx_mdio_remove();
1331
1332 return 0;
1333 }
1334
1335 static struct platform_driver cns3xxx_eth_driver = {
1336 .driver.name = DRV_NAME,
1337 .probe = eth_init_one,
1338 .remove = eth_remove_one,
1339 };
1340
1341 static int __init eth_init_module(void)
1342 {
1343 return platform_driver_register(&cns3xxx_eth_driver);
1344 }
1345
1346 static void __exit eth_cleanup_module(void)
1347 {
1348 platform_driver_unregister(&cns3xxx_eth_driver);
1349 }
1350
1351 module_init(eth_init_module);
1352 module_exit(eth_cleanup_module);
1353
1354 MODULE_AUTHOR("Chris Lang");
1355 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1356 MODULE_LICENSE("GPL v2");
1357 MODULE_ALIAS("platform:cns3xxx_eth");
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