2 * Cavium CNS3xxx Gigabit driver for Linux
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
26 #define DRV_NAME "cns3xxx_eth"
30 #define TX_DESC_RESERVE 20
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
45 #define NAPI_WEIGHT 64
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define UDP_CHECKSUM 0x00020000
60 #define TCP_CHECKSUM 0x00010000
62 /* Port Config Defines */
63 #define PORT_BP_ENABLE 0x00020000
64 #define PORT_DISABLE 0x00040000
65 #define PORT_LEARN_DIS 0x00080000
66 #define PORT_BLOCK_STATE 0x00100000
67 #define PORT_BLOCK_MODE 0x00200000
69 #define PROMISC_OFFSET 29
71 /* Global Config Defines */
72 #define UNKNOWN_VLAN_TO_CPU 0x02000000
73 #define ACCEPT_CRC_PACKET 0x00200000
74 #define CRC_STRIPPING 0x00100000
76 /* VLAN Config Defines */
77 #define NIC_MODE 0x00008000
78 #define VLAN_UNAWARE 0x00000001
80 /* DMA AUTO Poll Defines */
81 #define TS_POLL_EN 0x00000020
82 #define TS_SUSPEND 0x00000010
83 #define FS_POLL_EN 0x00000002
84 #define FS_SUSPEND 0x00000001
86 /* DMA Ring Control Defines */
87 #define QUEUE_THRESHOLD 0x000000f0
88 #define CLR_FS_STATE 0x80000000
90 /* Interrupt Status Defines */
91 #define MAC0_STATUS_CHANGE 0x00004000
92 #define MAC1_STATUS_CHANGE 0x00008000
93 #define MAC2_STATUS_CHANGE 0x00010000
94 #define MAC0_RX_ERROR 0x00100000
95 #define MAC1_RX_ERROR 0x00200000
96 #define MAC2_RX_ERROR 0x00400000
100 u32 sdp
; /* segment data pointer */
104 u32 sdl
:16; /* segment data length */
108 u32 rsv_1
:3; /* reserve */
110 u32 fp
:1; /* force priority */
150 u8 alignment
[16]; /* for 32 byte */
155 u32 sdp
; /* segment data pointer */
159 u32 sdl
:16; /* segment data length */
204 u8 alignment
[16]; /* for 32 byte alignment */
213 u32 mac_pri_ctrl
[5], __res
;
235 u32 fc_input_thrs
, __res1
[2];
237 u32 mac_glob_cfg_ext
, __res2
[2];
239 u32 dma_auto_poll_cfg
;
240 u32 delay_intr_cfg
, __res3
;
243 u32 ts_desc_base_addr0
, __res4
;
246 u32 fs_desc_base_addr0
, __res5
;
249 u32 ts_desc_base_addr1
, __res6
;
252 u32 fs_desc_base_addr1
;
254 u32 mac_counter0
[13];
258 struct tx_desc
*desc
;
259 dma_addr_t phys_addr
;
260 struct tx_desc
*cur_addr
;
261 struct sk_buff
*buff_tab
[TX_DESCS
];
262 unsigned int phys_tab
[TX_DESCS
];
272 struct rx_desc
*desc
;
273 dma_addr_t phys_addr
;
274 struct rx_desc
*cur_addr
;
275 void *buff_tab
[RX_DESCS
];
276 unsigned int phys_tab
[RX_DESCS
];
283 struct switch_regs __iomem
*regs
;
284 struct napi_struct napi
;
285 struct cns3xxx_plat_info
*plat
;
286 struct _tx_ring tx_ring
;
287 struct _rx_ring rx_ring
;
288 struct sk_buff
*frag_first
;
289 struct sk_buff
*frag_last
;
296 struct net_device
*netdev
;
297 struct phy_device
*phydev
;
299 int id
; /* logical port ID */
303 static spinlock_t mdio_lock
;
304 static DEFINE_SPINLOCK(tx_lock
);
305 static struct switch_regs __iomem
*mdio_regs
; /* mdio command and status only */
306 struct mii_bus
*mdio_bus
;
307 static int ports_open
;
308 static struct port
*switch_port_tab
[4];
309 static struct dma_pool
*rx_dma_pool
;
310 static struct dma_pool
*tx_dma_pool
;
311 struct net_device
*napi_dev
;
313 static int cns3xxx_mdio_cmd(struct mii_bus
*bus
, int phy_id
, int location
,
319 temp
= __raw_readl(&mdio_regs
->phy_control
);
320 temp
|= MDIO_CMD_COMPLETE
;
321 __raw_writel(temp
, &mdio_regs
->phy_control
);
325 temp
= (cmd
<< MDIO_VALUE_OFFSET
);
326 temp
|= MDIO_WRITE_COMMAND
;
328 temp
= MDIO_READ_COMMAND
;
330 temp
|= ((location
& 0x1f) << MDIO_REG_OFFSET
);
331 temp
|= (phy_id
& 0x1f);
333 __raw_writel(temp
, &mdio_regs
->phy_control
);
335 while (((__raw_readl(&mdio_regs
->phy_control
) & MDIO_CMD_COMPLETE
) == 0)
341 if (cycles
== 5000) {
342 printk(KERN_ERR
"%s #%i: MII transaction failed\n", bus
->name
,
347 temp
= __raw_readl(&mdio_regs
->phy_control
);
348 temp
|= MDIO_CMD_COMPLETE
;
349 __raw_writel(temp
, &mdio_regs
->phy_control
);
354 return ((temp
>> MDIO_VALUE_OFFSET
) & 0xFFFF);
357 static int cns3xxx_mdio_read(struct mii_bus
*bus
, int phy_id
, int location
)
362 spin_lock_irqsave(&mdio_lock
, flags
);
363 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 0, 0);
364 spin_unlock_irqrestore(&mdio_lock
, flags
);
368 static int cns3xxx_mdio_write(struct mii_bus
*bus
, int phy_id
, int location
,
374 spin_lock_irqsave(&mdio_lock
, flags
);
375 ret
= cns3xxx_mdio_cmd(bus
, phy_id
, location
, 1, val
);
376 spin_unlock_irqrestore(&mdio_lock
, flags
);
380 static int cns3xxx_mdio_register(void __iomem
*base
)
384 if (!(mdio_bus
= mdiobus_alloc()))
389 spin_lock_init(&mdio_lock
);
390 mdio_bus
->name
= "CNS3xxx MII Bus";
391 mdio_bus
->read
= &cns3xxx_mdio_read
;
392 mdio_bus
->write
= &cns3xxx_mdio_write
;
393 strcpy(mdio_bus
->id
, "0");
395 if ((err
= mdiobus_register(mdio_bus
)))
396 mdiobus_free(mdio_bus
);
400 static void cns3xxx_mdio_remove(void)
402 mdiobus_unregister(mdio_bus
);
403 mdiobus_free(mdio_bus
);
406 static void enable_tx_dma(struct sw
*sw
)
408 __raw_writel(0x1, &sw
->regs
->ts_dma_ctrl0
);
411 static void enable_rx_dma(struct sw
*sw
)
413 __raw_writel(0x1, &sw
->regs
->fs_dma_ctrl0
);
416 static void cns3xxx_adjust_link(struct net_device
*dev
)
418 struct port
*port
= netdev_priv(dev
);
419 struct phy_device
*phydev
= port
->phydev
;
424 printk(KERN_INFO
"%s: link down\n", dev
->name
);
429 if (port
->speed
== phydev
->speed
&& port
->duplex
== phydev
->duplex
)
432 port
->speed
= phydev
->speed
;
433 port
->duplex
= phydev
->duplex
;
435 printk(KERN_INFO
"%s: link up, speed %u Mb/s, %s duplex\n",
436 dev
->name
, port
->speed
, port
->duplex
? "full" : "half");
439 static void eth_schedule_poll(struct sw
*sw
)
441 if (unlikely(!napi_schedule_prep(&sw
->napi
)))
444 disable_irq_nosync(sw
->rx_irq
);
445 __napi_schedule(&sw
->napi
);
448 irqreturn_t
eth_rx_irq(int irq
, void *pdev
)
450 struct net_device
*dev
= pdev
;
451 struct sw
*sw
= netdev_priv(dev
);
452 eth_schedule_poll(sw
);
453 return (IRQ_HANDLED
);
456 irqreturn_t
eth_stat_irq(int irq
, void *pdev
)
458 struct net_device
*dev
= pdev
;
459 struct sw
*sw
= netdev_priv(dev
);
461 u32 stat
= __raw_readl(&sw
->regs
->intr_stat
);
462 __raw_writel(0xffffffff, &sw
->regs
->intr_stat
);
464 if (stat
& MAC2_RX_ERROR
)
465 switch_port_tab
[3]->netdev
->stats
.rx_dropped
++;
466 if (stat
& MAC1_RX_ERROR
)
467 switch_port_tab
[1]->netdev
->stats
.rx_dropped
++;
468 if (stat
& MAC0_RX_ERROR
)
469 switch_port_tab
[0]->netdev
->stats
.rx_dropped
++;
471 if (stat
& MAC0_STATUS_CHANGE
) {
472 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[0]);
473 switch_port_tab
[0]->phydev
->link
= (cfg
& 0x1);
474 switch_port_tab
[0]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
475 if (((cfg
>> 2) & 0x3) == 2)
476 switch_port_tab
[0]->phydev
->speed
= 1000;
477 else if (((cfg
>> 2) & 0x3) == 1)
478 switch_port_tab
[0]->phydev
->speed
= 100;
480 switch_port_tab
[0]->phydev
->speed
= 10;
481 cns3xxx_adjust_link(switch_port_tab
[0]->netdev
);
484 if (stat
& MAC1_STATUS_CHANGE
) {
485 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[1]);
486 switch_port_tab
[1]->phydev
->link
= (cfg
& 0x1);
487 switch_port_tab
[1]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
488 if (((cfg
>> 2) & 0x3) == 2)
489 switch_port_tab
[1]->phydev
->speed
= 1000;
490 else if (((cfg
>> 2) & 0x3) == 1)
491 switch_port_tab
[1]->phydev
->speed
= 100;
493 switch_port_tab
[1]->phydev
->speed
= 10;
494 cns3xxx_adjust_link(switch_port_tab
[1]->netdev
);
497 if (stat
& MAC2_STATUS_CHANGE
) {
498 cfg
= __raw_readl(&sw
->regs
->mac_cfg
[3]);
499 switch_port_tab
[3]->phydev
->link
= (cfg
& 0x1);
500 switch_port_tab
[3]->phydev
->duplex
= ((cfg
>> 4) & 0x1);
501 if (((cfg
>> 2) & 0x3) == 2)
502 switch_port_tab
[3]->phydev
->speed
= 1000;
503 else if (((cfg
>> 2) & 0x3) == 1)
504 switch_port_tab
[3]->phydev
->speed
= 100;
506 switch_port_tab
[3]->phydev
->speed
= 10;
507 cns3xxx_adjust_link(switch_port_tab
[3]->netdev
);
510 return (IRQ_HANDLED
);
514 static void cns3xxx_alloc_rx_buf(struct sw
*sw
, int received
)
516 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
517 unsigned int i
= rx_ring
->alloc_index
;
518 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
522 for (received
+= rx_ring
->alloc_count
; received
> 0; received
--) {
523 buf
= kmalloc(RX_SEGMENT_ALLOC_SIZE
, GFP_ATOMIC
);
527 phys
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
528 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
529 if (dma_mapping_error(sw
->dev
, phys
)) {
534 desc
->sdl
= RX_SEGMENT_MRU
;
539 /* put the new buffer on RX-free queue */
540 rx_ring
->buff_tab
[i
] = buf
;
541 rx_ring
->phys_tab
[i
] = phys
;
542 if (i
== RX_DESCS
- 1) {
544 desc
->config0
= END_OF_RING
| FIRST_SEGMENT
|
545 LAST_SEGMENT
| RX_SEGMENT_MRU
;
546 desc
= &(rx_ring
)->desc
[i
];
548 desc
->config0
= FIRST_SEGMENT
| LAST_SEGMENT
|
555 rx_ring
->alloc_count
= received
;
556 rx_ring
->alloc_index
= i
;
559 static void eth_check_num_used(struct _tx_ring
*tx_ring
)
564 if (tx_ring
->num_used
>= TX_DESCS
- TX_DESC_RESERVE
)
567 if (tx_ring
->stopped
== stop
)
570 tx_ring
->stopped
= stop
;
571 for (i
= 0; i
< 4; i
++) {
572 struct port
*port
= switch_port_tab
[i
];
573 struct net_device
*dev
;
580 netif_stop_queue(dev
);
582 netif_wake_queue(dev
);
586 static void eth_complete_tx(struct sw
*sw
)
588 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
589 struct tx_desc
*desc
;
592 int num_used
= tx_ring
->num_used
;
595 index
= tx_ring
->free_index
;
596 desc
= &(tx_ring
)->desc
[index
];
597 for (i
= 0; i
< num_used
; i
++) {
599 skb
= tx_ring
->buff_tab
[index
];
600 tx_ring
->buff_tab
[index
] = 0;
602 dev_kfree_skb_any(skb
);
603 dma_unmap_single(sw
->dev
, tx_ring
->phys_tab
[index
],
604 desc
->sdl
, DMA_TO_DEVICE
);
605 if (++index
== TX_DESCS
) {
607 desc
= &(tx_ring
)->desc
[index
];
615 tx_ring
->free_index
= index
;
616 tx_ring
->num_used
-= i
;
617 eth_check_num_used(tx_ring
);
620 static int eth_poll(struct napi_struct
*napi
, int budget
)
622 struct sw
*sw
= container_of(napi
, struct sw
, napi
);
623 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
626 unsigned int i
= rx_ring
->cur_index
;
627 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
628 unsigned int alloc_count
= rx_ring
->alloc_count
;
630 while (desc
->cown
&& alloc_count
+ received
< RX_DESCS
- 1) {
632 int reserve
= SKB_HEAD_ALIGN
;
634 if (received
>= budget
)
637 /* process received frame */
638 dma_unmap_single(sw
->dev
, rx_ring
->phys_tab
[i
],
639 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
641 skb
= build_skb(rx_ring
->buff_tab
[i
], 0);
645 skb
->dev
= switch_port_tab
[desc
->sp
]->netdev
;
648 if (desc
->fsd
&& !desc
->lsd
)
649 length
= RX_SEGMENT_MRU
;
652 reserve
-= NET_IP_ALIGN
;
654 length
+= NET_IP_ALIGN
;
657 skb_reserve(skb
, reserve
);
658 skb_put(skb
, length
);
661 sw
->frag_first
= skb
;
663 if (sw
->frag_first
== sw
->frag_last
)
664 skb_shinfo(sw
->frag_first
)->frag_list
= skb
;
666 sw
->frag_last
->next
= skb
;
667 sw
->frag_first
->len
+= skb
->len
;
668 sw
->frag_first
->data_len
+= skb
->len
;
669 sw
->frag_first
->truesize
+= skb
->truesize
;
674 struct net_device
*dev
;
676 skb
= sw
->frag_first
;
678 skb
->protocol
= eth_type_trans(skb
, dev
);
680 dev
->stats
.rx_packets
++;
681 dev
->stats
.rx_bytes
+= skb
->len
;
683 /* RX Hardware checksum offload */
684 skb
->ip_summed
= CHECKSUM_NONE
;
685 switch (desc
->prot
) {
693 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
694 napi_gro_receive(napi
, skb
);
699 netif_receive_skb(skb
);
703 sw
->frag_first
= NULL
;
704 sw
->frag_last
= NULL
;
708 if (++i
== RX_DESCS
) {
710 desc
= &(rx_ring
)->desc
[i
];
716 rx_ring
->cur_index
= i
;
719 enable_irq(sw
->rx_irq
);
721 /* if rx descriptors are full schedule another poll */
722 if (rx_ring
->desc
[(i
-1) & (RX_DESCS
-1)].cown
)
723 eth_schedule_poll(sw
);
726 spin_lock_bh(&tx_lock
);
728 spin_unlock_bh(&tx_lock
);
730 cns3xxx_alloc_rx_buf(sw
, received
);
738 static void eth_set_desc(struct sw
*sw
, struct _tx_ring
*tx_ring
, int index
,
739 int index_last
, void *data
, int len
, u32 config0
,
742 struct tx_desc
*tx_desc
= &(tx_ring
)->desc
[index
];
745 phys
= dma_map_single(sw
->dev
, data
, len
, DMA_TO_DEVICE
);
747 tx_desc
->pmap
= pmap
;
748 tx_ring
->phys_tab
[index
] = phys
;
751 if (index
== TX_DESCS
- 1)
752 config0
|= END_OF_RING
;
753 if (index
== index_last
)
754 config0
|= LAST_SEGMENT
;
757 tx_desc
->config0
= config0
;
760 static int eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
762 struct port
*port
= netdev_priv(dev
);
763 struct sw
*sw
= port
->sw
;
764 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
765 struct sk_buff
*skb1
;
766 char pmap
= (1 << port
->id
);
767 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
768 int nr_desc
= nr_frags
;
769 int index0
, index
, index_last
;
777 skb_walk_frags(skb
, skb1
)
780 eth_schedule_poll(sw
);
781 spin_lock_bh(&tx_lock
);
782 if ((tx_ring
->num_used
+ nr_desc
+ 1) >= TX_DESCS
) {
783 spin_unlock_bh(&tx_lock
);
784 return NETDEV_TX_BUSY
;
787 index
= index0
= tx_ring
->cur_index
;
788 index_last
= (index0
+ nr_desc
) % TX_DESCS
;
789 tx_ring
->cur_index
= (index_last
+ 1) % TX_DESCS
;
791 spin_unlock_bh(&tx_lock
);
793 config0
= FORCE_ROUTE
;
794 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
795 config0
|= UDP_CHECKSUM
| TCP_CHECKSUM
;
800 for (i
= 0; i
< nr_frags
; i
++) {
801 struct skb_frag_struct
*frag
;
804 index
= (index
+ 1) % TX_DESCS
;
806 frag
= &skb_shinfo(skb
)->frags
[i
];
807 addr
= page_address(skb_frag_page(frag
)) + frag
->page_offset
;
809 eth_set_desc(sw
, tx_ring
, index
, index_last
, addr
, frag
->size
,
814 len0
= skb
->len
- skb
->data_len
;
816 skb_walk_frags(skb
, skb1
) {
817 index
= (index
+ 1) % TX_DESCS
;
820 eth_set_desc(sw
, tx_ring
, index
, index_last
, skb1
->data
,
821 skb1
->len
, config0
, pmap
);
824 tx_ring
->buff_tab
[index0
] = skb
;
825 eth_set_desc(sw
, tx_ring
, index0
, index_last
, skb
->data
, len0
,
826 config0
| FIRST_SEGMENT
, pmap
);
831 tx_ring
->num_used
+= nr_desc
+ 1;
832 spin_unlock(&tx_lock
);
834 dev
->stats
.tx_packets
++;
835 dev
->stats
.tx_bytes
+= skb
->len
;
842 static int eth_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
844 struct port
*port
= netdev_priv(dev
);
846 if (!netif_running(dev
))
848 return phy_mii_ioctl(port
->phydev
, req
, cmd
);
851 /* ethtool support */
853 static void cns3xxx_get_drvinfo(struct net_device
*dev
,
854 struct ethtool_drvinfo
*info
)
856 strcpy(info
->driver
, DRV_NAME
);
857 strcpy(info
->bus_info
, "internal");
860 static int cns3xxx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
862 struct port
*port
= netdev_priv(dev
);
863 return phy_ethtool_gset(port
->phydev
, cmd
);
866 static int cns3xxx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
868 struct port
*port
= netdev_priv(dev
);
869 return phy_ethtool_sset(port
->phydev
, cmd
);
872 static int cns3xxx_nway_reset(struct net_device
*dev
)
874 struct port
*port
= netdev_priv(dev
);
875 return phy_start_aneg(port
->phydev
);
878 static struct ethtool_ops cns3xxx_ethtool_ops
= {
879 .get_drvinfo
= cns3xxx_get_drvinfo
,
880 .get_settings
= cns3xxx_get_settings
,
881 .set_settings
= cns3xxx_set_settings
,
882 .nway_reset
= cns3xxx_nway_reset
,
883 .get_link
= ethtool_op_get_link
,
887 static int init_rings(struct sw
*sw
)
890 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
891 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
893 __raw_writel(0, &sw
->regs
->fs_dma_ctrl0
);
894 __raw_writel(TS_SUSPEND
| FS_SUSPEND
, &sw
->regs
->dma_auto_poll_cfg
);
895 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
896 __raw_writel(CLR_FS_STATE
| QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
898 __raw_writel(QUEUE_THRESHOLD
, &sw
->regs
->dma_ring_ctrl
);
900 if (!(rx_dma_pool
= dma_pool_create(DRV_NAME
, sw
->dev
,
901 RX_POOL_ALLOC_SIZE
, 32, 0)))
904 if (!(rx_ring
->desc
= dma_pool_alloc(rx_dma_pool
, GFP_KERNEL
,
905 &rx_ring
->phys_addr
)))
907 memset(rx_ring
->desc
, 0, RX_POOL_ALLOC_SIZE
);
909 /* Setup RX buffers */
910 for (i
= 0; i
< RX_DESCS
; i
++) {
911 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
914 buf
= kzalloc(RX_SEGMENT_ALLOC_SIZE
, GFP_KERNEL
);
918 desc
->sdl
= RX_SEGMENT_MRU
;
919 if (i
== (RX_DESCS
- 1))
924 desc
->sdp
= dma_map_single(sw
->dev
, buf
+ SKB_HEAD_ALIGN
,
925 RX_SEGMENT_MRU
, DMA_FROM_DEVICE
);
926 if (dma_mapping_error(sw
->dev
, desc
->sdp
))
929 rx_ring
->buff_tab
[i
] = buf
;
930 rx_ring
->phys_tab
[i
] = desc
->sdp
;
933 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_ptr0
);
934 __raw_writel(rx_ring
->phys_addr
, &sw
->regs
->fs_desc_base_addr0
);
936 if (!(tx_dma_pool
= dma_pool_create(DRV_NAME
, sw
->dev
,
937 TX_POOL_ALLOC_SIZE
, 32, 0)))
940 if (!(tx_ring
->desc
= dma_pool_alloc(tx_dma_pool
, GFP_KERNEL
,
941 &tx_ring
->phys_addr
)))
943 memset(tx_ring
->desc
, 0, TX_POOL_ALLOC_SIZE
);
945 /* Setup TX buffers */
946 for (i
= 0; i
< TX_DESCS
; i
++) {
947 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
948 tx_ring
->buff_tab
[i
] = 0;
950 if (i
== (TX_DESCS
- 1))
954 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_ptr0
);
955 __raw_writel(tx_ring
->phys_addr
, &sw
->regs
->ts_desc_base_addr0
);
960 static void destroy_rings(struct sw
*sw
)
963 if (sw
->rx_ring
.desc
) {
964 for (i
= 0; i
< RX_DESCS
; i
++) {
965 struct _rx_ring
*rx_ring
= &sw
->rx_ring
;
966 struct rx_desc
*desc
= &(rx_ring
)->desc
[i
];
967 struct sk_buff
*skb
= sw
->rx_ring
.buff_tab
[i
];
972 dma_unmap_single(sw
->dev
, desc
->sdp
, RX_SEGMENT_MRU
,
976 dma_pool_free(rx_dma_pool
, sw
->rx_ring
.desc
, sw
->rx_ring
.phys_addr
);
977 dma_pool_destroy(rx_dma_pool
);
979 sw
->rx_ring
.desc
= 0;
981 if (sw
->tx_ring
.desc
) {
982 for (i
= 0; i
< TX_DESCS
; i
++) {
983 struct _tx_ring
*tx_ring
= &sw
->tx_ring
;
984 struct tx_desc
*desc
= &(tx_ring
)->desc
[i
];
985 struct sk_buff
*skb
= sw
->tx_ring
.buff_tab
[i
];
987 dma_unmap_single(sw
->dev
, desc
->sdp
,
988 skb
->len
, DMA_TO_DEVICE
);
992 dma_pool_free(tx_dma_pool
, sw
->tx_ring
.desc
, sw
->tx_ring
.phys_addr
);
993 dma_pool_destroy(tx_dma_pool
);
995 sw
->tx_ring
.desc
= 0;
999 static int eth_open(struct net_device
*dev
)
1001 struct port
*port
= netdev_priv(dev
);
1002 struct sw
*sw
= port
->sw
;
1005 port
->speed
= 0; /* force "link up" message */
1006 phy_start(port
->phydev
);
1008 netif_start_queue(dev
);
1011 request_irq(sw
->rx_irq
, eth_rx_irq
, IRQF_SHARED
, "gig_switch", napi_dev
);
1012 request_irq(sw
->stat_irq
, eth_stat_irq
, IRQF_SHARED
, "gig_stat", napi_dev
);
1013 napi_enable(&sw
->napi
);
1014 netif_start_queue(napi_dev
);
1016 __raw_writel(~(MAC0_STATUS_CHANGE
| MAC1_STATUS_CHANGE
| MAC2_STATUS_CHANGE
|
1017 MAC0_RX_ERROR
| MAC1_RX_ERROR
| MAC2_RX_ERROR
), &sw
->regs
->intr_mask
);
1019 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
1020 temp
&= ~(PORT_DISABLE
);
1021 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1023 temp
= __raw_readl(&sw
->regs
->dma_auto_poll_cfg
);
1024 temp
&= ~(TS_SUSPEND
| FS_SUSPEND
);
1025 __raw_writel(temp
, &sw
->regs
->dma_auto_poll_cfg
);
1029 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1030 temp
&= ~(PORT_DISABLE
);
1031 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1034 netif_carrier_on(dev
);
1039 static int eth_close(struct net_device
*dev
)
1041 struct port
*port
= netdev_priv(dev
);
1042 struct sw
*sw
= port
->sw
;
1047 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1048 temp
|= (PORT_DISABLE
);
1049 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1051 netif_stop_queue(dev
);
1053 phy_stop(port
->phydev
);
1056 disable_irq(sw
->rx_irq
);
1057 free_irq(sw
->rx_irq
, napi_dev
);
1058 disable_irq(sw
->stat_irq
);
1059 free_irq(sw
->stat_irq
, napi_dev
);
1060 napi_disable(&sw
->napi
);
1061 netif_stop_queue(napi_dev
);
1062 temp
= __raw_readl(&sw
->regs
->mac_cfg
[2]);
1063 temp
|= (PORT_DISABLE
);
1064 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1066 __raw_writel(TS_SUSPEND
| FS_SUSPEND
,
1067 &sw
->regs
->dma_auto_poll_cfg
);
1070 netif_carrier_off(dev
);
1074 static void eth_rx_mode(struct net_device
*dev
)
1076 struct port
*port
= netdev_priv(dev
);
1077 struct sw
*sw
= port
->sw
;
1080 temp
= __raw_readl(&sw
->regs
->mac_glob_cfg
);
1082 if (dev
->flags
& IFF_PROMISC
) {
1084 temp
|= ((1 << 2) << PROMISC_OFFSET
);
1086 temp
|= ((1 << port
->id
) << PROMISC_OFFSET
);
1089 temp
&= ~((1 << 2) << PROMISC_OFFSET
);
1091 temp
&= ~((1 << port
->id
) << PROMISC_OFFSET
);
1093 __raw_writel(temp
, &sw
->regs
->mac_glob_cfg
);
1096 static int eth_set_mac(struct net_device
*netdev
, void *p
)
1098 struct port
*port
= netdev_priv(netdev
);
1099 struct sw
*sw
= port
->sw
;
1100 struct sockaddr
*addr
= p
;
1103 if (!is_valid_ether_addr(addr
->sa_data
))
1104 return -EADDRNOTAVAIL
;
1106 /* Invalidate old ARL Entry */
1108 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1110 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1111 __raw_writel( ((netdev
->dev_addr
[0] << 24) | (netdev
->dev_addr
[1] << 16) |
1112 (netdev
->dev_addr
[2] << 8) | (netdev
->dev_addr
[3])),
1113 &sw
->regs
->arl_ctrl
[1]);
1115 __raw_writel( ((netdev
->dev_addr
[4] << 24) | (netdev
->dev_addr
[5] << 16) |
1117 &sw
->regs
->arl_ctrl
[2]);
1118 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1120 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1127 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1130 __raw_writel((port
->id
<< 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1132 __raw_writel(((port
->id
+ 1) << 16) | (0x4 << 9), &sw
->regs
->arl_ctrl
[0]);
1133 __raw_writel( ((addr
->sa_data
[0] << 24) | (addr
->sa_data
[1] << 16) |
1134 (addr
->sa_data
[2] << 8) | (addr
->sa_data
[3])),
1135 &sw
->regs
->arl_ctrl
[1]);
1137 __raw_writel( ((addr
->sa_data
[4] << 24) | (addr
->sa_data
[5] << 16) |
1138 (7 << 4) | (1 << 1)), &sw
->regs
->arl_ctrl
[2]);
1139 __raw_writel((1 << 19), &sw
->regs
->arl_vlan_cmd
);
1141 while (((__raw_readl(&sw
->regs
->arl_vlan_cmd
) & (1 << 21)) == 0)
1149 static int cns3xxx_change_mtu(struct net_device
*dev
, int new_mtu
)
1151 if (new_mtu
> MAX_MTU
)
1158 static const struct net_device_ops cns3xxx_netdev_ops
= {
1159 .ndo_open
= eth_open
,
1160 .ndo_stop
= eth_close
,
1161 .ndo_start_xmit
= eth_xmit
,
1162 .ndo_set_rx_mode
= eth_rx_mode
,
1163 .ndo_do_ioctl
= eth_ioctl
,
1164 .ndo_change_mtu
= cns3xxx_change_mtu
,
1165 .ndo_set_mac_address
= eth_set_mac
,
1166 .ndo_validate_addr
= eth_validate_addr
,
1169 static int eth_init_one(struct platform_device
*pdev
)
1174 struct net_device
*dev
;
1175 struct cns3xxx_plat_info
*plat
= pdev
->dev
.platform_data
;
1176 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1179 struct resource
*res
;
1182 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1183 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1185 return PTR_ERR(regs
);
1187 err
= cns3xxx_mdio_register(regs
);
1191 if (!(napi_dev
= alloc_etherdev(sizeof(struct sw
)))) {
1193 goto err_remove_mdio
;
1196 strcpy(napi_dev
->name
, "switch%d");
1197 napi_dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1199 SET_NETDEV_DEV(napi_dev
, &pdev
->dev
);
1200 sw
= netdev_priv(napi_dev
);
1201 memset(sw
, 0, sizeof(struct sw
));
1203 sw
->dev
= &pdev
->dev
;
1205 sw
->rx_irq
= platform_get_irq_byname(pdev
, "eth_rx");
1206 sw
->stat_irq
= platform_get_irq_byname(pdev
, "eth_stat");
1208 temp
= __raw_readl(&sw
->regs
->phy_auto_addr
);
1209 temp
|= (3 << 30); /* maximum frame length: 9600 bytes */
1210 __raw_writel(temp
, &sw
->regs
->phy_auto_addr
);
1212 for (i
= 0; i
< 4; i
++) {
1213 temp
= __raw_readl(&sw
->regs
->mac_cfg
[i
]);
1214 temp
|= (PORT_DISABLE
);
1215 __raw_writel(temp
, &sw
->regs
->mac_cfg
[i
]);
1218 temp
= PORT_DISABLE
;
1219 __raw_writel(temp
, &sw
->regs
->mac_cfg
[2]);
1221 temp
= __raw_readl(&sw
->regs
->vlan_cfg
);
1222 temp
|= NIC_MODE
| VLAN_UNAWARE
;
1223 __raw_writel(temp
, &sw
->regs
->vlan_cfg
);
1225 __raw_writel(UNKNOWN_VLAN_TO_CPU
|
1226 CRC_STRIPPING
, &sw
->regs
->mac_glob_cfg
);
1228 if ((err
= init_rings(sw
)) != 0) {
1233 platform_set_drvdata(pdev
, napi_dev
);
1235 netif_napi_add(napi_dev
, &sw
->napi
, eth_poll
, NAPI_WEIGHT
);
1237 for (i
= 0; i
< 3; i
++) {
1238 if (!(plat
->ports
& (1 << i
))) {
1242 if (!(dev
= alloc_etherdev(sizeof(struct port
)))) {
1246 port
= netdev_priv(dev
);
1254 temp
= __raw_readl(&sw
->regs
->mac_cfg
[port
->id
]);
1255 temp
|= (PORT_DISABLE
| PORT_BLOCK_STATE
| PORT_LEARN_DIS
);
1256 __raw_writel(temp
, &sw
->regs
->mac_cfg
[port
->id
]);
1258 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1259 dev
->netdev_ops
= &cns3xxx_netdev_ops
;
1260 dev
->ethtool_ops
= &cns3xxx_ethtool_ops
;
1261 dev
->tx_queue_len
= 1000;
1262 dev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_FRAGLIST
;
1264 switch_port_tab
[port
->id
] = port
;
1265 memcpy(dev
->dev_addr
, &plat
->hwaddr
[i
], ETH_ALEN
);
1267 snprintf(phy_id
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, "0", plat
->phy
[i
]);
1268 port
->phydev
= phy_connect(dev
, phy_id
, &cns3xxx_adjust_link
,
1269 PHY_INTERFACE_MODE_RGMII
);
1270 if ((err
= IS_ERR(port
->phydev
))) {
1271 switch_port_tab
[port
->id
] = 0;
1276 port
->phydev
->irq
= PHY_IGNORE_INTERRUPT
;
1278 if ((err
= register_netdev(dev
))) {
1279 phy_disconnect(port
->phydev
);
1280 switch_port_tab
[port
->id
] = 0;
1285 printk(KERN_INFO
"%s: RGMII PHY %i on cns3xxx Switch\n", dev
->name
, plat
->phy
[i
]);
1286 netif_carrier_off(dev
);
1294 for (--i
; i
>= 0; i
--) {
1295 if (switch_port_tab
[i
]) {
1296 port
= switch_port_tab
[i
];
1298 unregister_netdev(dev
);
1299 phy_disconnect(port
->phydev
);
1300 switch_port_tab
[i
] = 0;
1305 free_netdev(napi_dev
);
1307 cns3xxx_mdio_remove();
1311 static int eth_remove_one(struct platform_device
*pdev
)
1313 struct net_device
*dev
= platform_get_drvdata(pdev
);
1314 struct sw
*sw
= netdev_priv(dev
);
1318 for (i
= 3; i
>= 0; i
--) {
1319 if (switch_port_tab
[i
]) {
1320 struct port
*port
= switch_port_tab
[i
];
1321 struct net_device
*dev
= port
->netdev
;
1322 unregister_netdev(dev
);
1323 phy_disconnect(port
->phydev
);
1324 switch_port_tab
[i
] = 0;
1329 free_netdev(napi_dev
);
1330 cns3xxx_mdio_remove();
1335 static struct platform_driver cns3xxx_eth_driver
= {
1336 .driver
.name
= DRV_NAME
,
1337 .probe
= eth_init_one
,
1338 .remove
= eth_remove_one
,
1341 static int __init
eth_init_module(void)
1343 return platform_driver_register(&cns3xxx_eth_driver
);
1346 static void __exit
eth_cleanup_module(void)
1348 platform_driver_unregister(&cns3xxx_eth_driver
);
1351 module_init(eth_init_module
);
1352 module_exit(eth_cleanup_module
);
1354 MODULE_AUTHOR("Chris Lang");
1355 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1356 MODULE_LICENSE("GPL v2");
1357 MODULE_ALIAS("platform:cns3xxx_eth");