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[openwrt/svn-archive/archive.git] / target / linux / cns3xxx / files / drivers / net / ethernet / cavium / cns3xxx_eth.c
1 /*
2 * Cavium CNS3xxx Gigabit driver for Linux
3 *
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
25
26 #define DRV_NAME "cns3xxx_eth"
27
28 #define RX_DESCS 256
29 #define TX_DESCS 128
30 #define TX_DESC_RESERVE 20
31
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
34 #define REGS_SIZE 336
35
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
38
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
43 #define MAX_MTU 9500
44
45 #define NAPI_WEIGHT 64
46
47 /* MDIO Defines */
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
53
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define UDP_CHECKSUM 0x00020000
60 #define TCP_CHECKSUM 0x00010000
61
62 /* Port Config Defines */
63 #define PORT_BP_ENABLE 0x00020000
64 #define PORT_DISABLE 0x00040000
65 #define PORT_LEARN_DIS 0x00080000
66 #define PORT_BLOCK_STATE 0x00100000
67 #define PORT_BLOCK_MODE 0x00200000
68
69 #define PROMISC_OFFSET 29
70
71 /* Global Config Defines */
72 #define UNKNOWN_VLAN_TO_CPU 0x02000000
73 #define ACCEPT_CRC_PACKET 0x00200000
74 #define CRC_STRIPPING 0x00100000
75
76 /* VLAN Config Defines */
77 #define NIC_MODE 0x00008000
78 #define VLAN_UNAWARE 0x00000001
79
80 /* DMA AUTO Poll Defines */
81 #define TS_POLL_EN 0x00000020
82 #define TS_SUSPEND 0x00000010
83 #define FS_POLL_EN 0x00000002
84 #define FS_SUSPEND 0x00000001
85
86 /* DMA Ring Control Defines */
87 #define QUEUE_THRESHOLD 0x000000f0
88 #define CLR_FS_STATE 0x80000000
89
90 /* Interrupt Status Defines */
91 #define MAC0_STATUS_CHANGE 0x00004000
92 #define MAC1_STATUS_CHANGE 0x00008000
93 #define MAC2_STATUS_CHANGE 0x00010000
94 #define MAC0_RX_ERROR 0x00100000
95 #define MAC1_RX_ERROR 0x00200000
96 #define MAC2_RX_ERROR 0x00400000
97
98 struct tx_desc
99 {
100 u32 sdp; /* segment data pointer */
101
102 union {
103 struct {
104 u32 sdl:16; /* segment data length */
105 u32 tco:1;
106 u32 uco:1;
107 u32 ico:1;
108 u32 rsv_1:3; /* reserve */
109 u32 pri:3;
110 u32 fp:1; /* force priority */
111 u32 fr:1;
112 u32 interrupt:1;
113 u32 lsd:1;
114 u32 fsd:1;
115 u32 eor:1;
116 u32 cown:1;
117 };
118 u32 config0;
119 };
120
121 union {
122 struct {
123 u32 ctv:1;
124 u32 stv:1;
125 u32 sid:4;
126 u32 inss:1;
127 u32 dels:1;
128 u32 rsv_2:9;
129 u32 pmap:5;
130 u32 mark:3;
131 u32 ewan:1;
132 u32 fewan:1;
133 u32 rsv_3:5;
134 };
135 u32 config1;
136 };
137
138 union {
139 struct {
140 u32 c_vid:12;
141 u32 c_cfs:1;
142 u32 c_pri:3;
143 u32 s_vid:12;
144 u32 s_dei:1;
145 u32 s_pri:3;
146 };
147 u32 config2;
148 };
149
150 u8 alignment[16]; /* for 32 byte */
151 };
152
153 struct rx_desc
154 {
155 u32 sdp; /* segment data pointer */
156
157 union {
158 struct {
159 u32 sdl:16; /* segment data length */
160 u32 l4f:1;
161 u32 ipf:1;
162 u32 prot:4;
163 u32 hr:6;
164 u32 lsd:1;
165 u32 fsd:1;
166 u32 eor:1;
167 u32 cown:1;
168 };
169 u32 config0;
170 };
171
172 union {
173 struct {
174 u32 ctv:1;
175 u32 stv:1;
176 u32 unv:1;
177 u32 iwan:1;
178 u32 exdv:1;
179 u32 e_wan:1;
180 u32 rsv_1:2;
181 u32 sp:3;
182 u32 crc_err:1;
183 u32 un_eth:1;
184 u32 tc:2;
185 u32 rsv_2:1;
186 u32 ip_offset:5;
187 u32 rsv_3:11;
188 };
189 u32 config1;
190 };
191
192 union {
193 struct {
194 u32 c_vid:12;
195 u32 c_cfs:1;
196 u32 c_pri:3;
197 u32 s_vid:12;
198 u32 s_dei:1;
199 u32 s_pri:3;
200 };
201 u32 config2;
202 };
203
204 u8 alignment[16]; /* for 32 byte alignment */
205 };
206
207
208 struct switch_regs {
209 u32 phy_control;
210 u32 phy_auto_addr;
211 u32 mac_glob_cfg;
212 u32 mac_cfg[4];
213 u32 mac_pri_ctrl[5], __res;
214 u32 etype[2];
215 u32 udp_range[4];
216 u32 prio_etype_udp;
217 u32 prio_ipdscp[8];
218 u32 tc_ctrl;
219 u32 rate_ctrl;
220 u32 fc_glob_thrs;
221 u32 fc_port_thrs;
222 u32 mc_fc_glob_thrs;
223 u32 dc_glob_thrs;
224 u32 arl_vlan_cmd;
225 u32 arl_ctrl[3];
226 u32 vlan_cfg;
227 u32 pvid[2];
228 u32 vlan_ctrl[3];
229 u32 session_id[8];
230 u32 intr_stat;
231 u32 intr_mask;
232 u32 sram_test;
233 u32 mem_queue;
234 u32 farl_ctrl;
235 u32 fc_input_thrs, __res1[2];
236 u32 clk_skew_ctrl;
237 u32 mac_glob_cfg_ext, __res2[2];
238 u32 dma_ring_ctrl;
239 u32 dma_auto_poll_cfg;
240 u32 delay_intr_cfg, __res3;
241 u32 ts_dma_ctrl0;
242 u32 ts_desc_ptr0;
243 u32 ts_desc_base_addr0, __res4;
244 u32 fs_dma_ctrl0;
245 u32 fs_desc_ptr0;
246 u32 fs_desc_base_addr0, __res5;
247 u32 ts_dma_ctrl1;
248 u32 ts_desc_ptr1;
249 u32 ts_desc_base_addr1, __res6;
250 u32 fs_dma_ctrl1;
251 u32 fs_desc_ptr1;
252 u32 fs_desc_base_addr1;
253 u32 __res7[109];
254 u32 mac_counter0[13];
255 };
256
257 struct _tx_ring {
258 struct tx_desc *desc;
259 dma_addr_t phys_addr;
260 struct tx_desc *cur_addr;
261 struct sk_buff *buff_tab[TX_DESCS];
262 unsigned int phys_tab[TX_DESCS];
263 u32 free_index;
264 u32 count_index;
265 u32 cur_index;
266 int num_used;
267 int num_count;
268 bool stopped;
269 };
270
271 struct _rx_ring {
272 struct rx_desc *desc;
273 dma_addr_t phys_addr;
274 struct rx_desc *cur_addr;
275 void *buff_tab[RX_DESCS];
276 unsigned int phys_tab[RX_DESCS];
277 u32 cur_index;
278 u32 alloc_index;
279 int alloc_count;
280 };
281
282 struct sw {
283 struct switch_regs __iomem *regs;
284 struct napi_struct napi;
285 struct cns3xxx_plat_info *plat;
286 struct _tx_ring tx_ring;
287 struct _rx_ring rx_ring;
288 struct sk_buff *frag_first;
289 struct sk_buff *frag_last;
290 struct device *dev;
291 int rx_irq;
292 int stat_irq;
293 };
294
295 struct port {
296 struct net_device *netdev;
297 struct phy_device *phydev;
298 struct sw *sw;
299 int id; /* logical port ID */
300 int speed, duplex;
301 };
302
303 static spinlock_t mdio_lock;
304 static DEFINE_SPINLOCK(tx_lock);
305 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
306 struct mii_bus *mdio_bus;
307 static int ports_open;
308 static struct port *switch_port_tab[4];
309 static struct dma_pool *rx_dma_pool;
310 static struct dma_pool *tx_dma_pool;
311 struct net_device *napi_dev;
312
313 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
314 int write, u16 cmd)
315 {
316 int cycles = 0;
317 u32 temp = 0;
318
319 temp = __raw_readl(&mdio_regs->phy_control);
320 temp |= MDIO_CMD_COMPLETE;
321 __raw_writel(temp, &mdio_regs->phy_control);
322 udelay(10);
323
324 if (write) {
325 temp = (cmd << MDIO_VALUE_OFFSET);
326 temp |= MDIO_WRITE_COMMAND;
327 } else {
328 temp = MDIO_READ_COMMAND;
329 }
330 temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
331 temp |= (phy_id & 0x1f);
332
333 __raw_writel(temp, &mdio_regs->phy_control);
334
335 while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
336 && cycles < 5000) {
337 udelay(1);
338 cycles++;
339 }
340
341 if (cycles == 5000) {
342 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name,
343 phy_id);
344 return -1;
345 }
346
347 temp = __raw_readl(&mdio_regs->phy_control);
348 temp |= MDIO_CMD_COMPLETE;
349 __raw_writel(temp, &mdio_regs->phy_control);
350
351 if (write)
352 return 0;
353
354 return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
355 }
356
357 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
358 {
359 unsigned long flags;
360 int ret;
361
362 spin_lock_irqsave(&mdio_lock, flags);
363 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
364 spin_unlock_irqrestore(&mdio_lock, flags);
365 return ret;
366 }
367
368 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
369 u16 val)
370 {
371 unsigned long flags;
372 int ret;
373
374 spin_lock_irqsave(&mdio_lock, flags);
375 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
376 spin_unlock_irqrestore(&mdio_lock, flags);
377 return ret;
378 }
379
380 static int cns3xxx_mdio_register(void __iomem *base)
381 {
382 int err;
383
384 if (!(mdio_bus = mdiobus_alloc()))
385 return -ENOMEM;
386
387 mdio_regs = base;
388
389 spin_lock_init(&mdio_lock);
390 mdio_bus->name = "CNS3xxx MII Bus";
391 mdio_bus->read = &cns3xxx_mdio_read;
392 mdio_bus->write = &cns3xxx_mdio_write;
393 strcpy(mdio_bus->id, "0");
394
395 if ((err = mdiobus_register(mdio_bus)))
396 mdiobus_free(mdio_bus);
397 return err;
398 }
399
400 static void cns3xxx_mdio_remove(void)
401 {
402 mdiobus_unregister(mdio_bus);
403 mdiobus_free(mdio_bus);
404 }
405
406 static void enable_tx_dma(struct sw *sw)
407 {
408 __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
409 }
410
411 static void enable_rx_dma(struct sw *sw)
412 {
413 __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
414 }
415
416 static void cns3xxx_adjust_link(struct net_device *dev)
417 {
418 struct port *port = netdev_priv(dev);
419 struct phy_device *phydev = port->phydev;
420
421 if (!phydev->link) {
422 if (port->speed) {
423 port->speed = 0;
424 printk(KERN_INFO "%s: link down\n", dev->name);
425 }
426 return;
427 }
428
429 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
430 return;
431
432 port->speed = phydev->speed;
433 port->duplex = phydev->duplex;
434
435 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
436 dev->name, port->speed, port->duplex ? "full" : "half");
437 }
438
439 static void eth_schedule_poll(struct sw *sw)
440 {
441 if (unlikely(!napi_schedule_prep(&sw->napi)))
442 return;
443
444 disable_irq_nosync(sw->rx_irq);
445 __napi_schedule(&sw->napi);
446 }
447
448 irqreturn_t eth_rx_irq(int irq, void *pdev)
449 {
450 struct net_device *dev = pdev;
451 struct sw *sw = netdev_priv(dev);
452 eth_schedule_poll(sw);
453 return (IRQ_HANDLED);
454 }
455
456 irqreturn_t eth_stat_irq(int irq, void *pdev)
457 {
458 struct net_device *dev = pdev;
459 struct sw *sw = netdev_priv(dev);
460 u32 cfg;
461 u32 stat = __raw_readl(&sw->regs->intr_stat);
462 __raw_writel(0xffffffff, &sw->regs->intr_stat);
463
464 if (stat & MAC2_RX_ERROR)
465 switch_port_tab[3]->netdev->stats.rx_dropped++;
466 if (stat & MAC1_RX_ERROR)
467 switch_port_tab[1]->netdev->stats.rx_dropped++;
468 if (stat & MAC0_RX_ERROR)
469 switch_port_tab[0]->netdev->stats.rx_dropped++;
470
471 if (stat & MAC0_STATUS_CHANGE) {
472 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
473 switch_port_tab[0]->phydev->link = (cfg & 0x1);
474 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
475 if (((cfg >> 2) & 0x3) == 2)
476 switch_port_tab[0]->phydev->speed = 1000;
477 else if (((cfg >> 2) & 0x3) == 1)
478 switch_port_tab[0]->phydev->speed = 100;
479 else
480 switch_port_tab[0]->phydev->speed = 10;
481 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
482 }
483
484 if (stat & MAC1_STATUS_CHANGE) {
485 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
486 switch_port_tab[1]->phydev->link = (cfg & 0x1);
487 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
488 if (((cfg >> 2) & 0x3) == 2)
489 switch_port_tab[1]->phydev->speed = 1000;
490 else if (((cfg >> 2) & 0x3) == 1)
491 switch_port_tab[1]->phydev->speed = 100;
492 else
493 switch_port_tab[1]->phydev->speed = 10;
494 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
495 }
496
497 if (stat & MAC2_STATUS_CHANGE) {
498 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
499 switch_port_tab[3]->phydev->link = (cfg & 0x1);
500 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
501 if (((cfg >> 2) & 0x3) == 2)
502 switch_port_tab[3]->phydev->speed = 1000;
503 else if (((cfg >> 2) & 0x3) == 1)
504 switch_port_tab[3]->phydev->speed = 100;
505 else
506 switch_port_tab[3]->phydev->speed = 10;
507 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
508 }
509
510 return (IRQ_HANDLED);
511 }
512
513
514 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
515 {
516 struct _rx_ring *rx_ring = &sw->rx_ring;
517 unsigned int i = rx_ring->alloc_index;
518 struct rx_desc *desc = &(rx_ring)->desc[i];
519 void *buf;
520 unsigned int phys;
521
522 for (received += rx_ring->alloc_count; received > 0; received--) {
523 buf = kmalloc(RX_SEGMENT_ALLOC_SIZE, GFP_ATOMIC);
524 if (!buf)
525 break;
526
527 phys = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
528 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
529 if (dma_mapping_error(sw->dev, phys)) {
530 kfree(buf);
531 break;
532 }
533
534 desc->sdl = RX_SEGMENT_MRU;
535 desc->sdp = phys;
536
537 wmb();
538
539 /* put the new buffer on RX-free queue */
540 rx_ring->buff_tab[i] = buf;
541 rx_ring->phys_tab[i] = phys;
542 if (i == RX_DESCS - 1) {
543 i = 0;
544 desc->config0 = END_OF_RING | FIRST_SEGMENT |
545 LAST_SEGMENT | RX_SEGMENT_MRU;
546 desc = &(rx_ring)->desc[i];
547 } else {
548 desc->config0 = FIRST_SEGMENT | LAST_SEGMENT |
549 RX_SEGMENT_MRU;
550 i++;
551 desc++;
552 }
553 }
554
555 rx_ring->alloc_count = received;
556 rx_ring->alloc_index = i;
557 }
558
559 static void eth_check_num_used(struct _tx_ring *tx_ring)
560 {
561 bool stop = false;
562 int i;
563
564 if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
565 stop = true;
566
567 if (tx_ring->stopped == stop)
568 return;
569
570 tx_ring->stopped = stop;
571 for (i = 0; i < 4; i++) {
572 struct port *port = switch_port_tab[i];
573 struct net_device *dev;
574
575 if (!port)
576 continue;
577
578 dev = port->netdev;
579 if (stop)
580 netif_stop_queue(dev);
581 else
582 netif_wake_queue(dev);
583 }
584 }
585
586 static void eth_complete_tx(struct sw *sw)
587 {
588 struct _tx_ring *tx_ring = &sw->tx_ring;
589 struct tx_desc *desc;
590 int i;
591 int index;
592 int num_used = tx_ring->num_used;
593 struct sk_buff *skb;
594
595 index = tx_ring->free_index;
596 desc = &(tx_ring)->desc[index];
597 for (i = 0; i < num_used; i++) {
598 if (desc->cown) {
599 skb = tx_ring->buff_tab[index];
600 tx_ring->buff_tab[index] = 0;
601 if (skb)
602 dev_kfree_skb_any(skb);
603 dma_unmap_single(sw->dev, tx_ring->phys_tab[index],
604 desc->sdl, DMA_TO_DEVICE);
605 if (++index == TX_DESCS) {
606 index = 0;
607 desc = &(tx_ring)->desc[index];
608 } else {
609 desc++;
610 }
611 } else {
612 break;
613 }
614 }
615 tx_ring->free_index = index;
616 tx_ring->num_used -= i;
617 eth_check_num_used(tx_ring);
618 }
619
620 static int eth_poll(struct napi_struct *napi, int budget)
621 {
622 struct sw *sw = container_of(napi, struct sw, napi);
623 struct _rx_ring *rx_ring = &sw->rx_ring;
624 int received = 0;
625 unsigned int length;
626 unsigned int i = rx_ring->cur_index;
627 struct rx_desc *desc = &(rx_ring)->desc[i];
628 unsigned int alloc_count = rx_ring->alloc_count;
629
630 while (desc->cown && alloc_count + received < RX_DESCS - 1) {
631 struct sk_buff *skb;
632 int reserve = SKB_HEAD_ALIGN;
633
634 if (received >= budget)
635 break;
636
637 /* process received frame */
638 dma_unmap_single(sw->dev, rx_ring->phys_tab[i],
639 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
640
641 skb = build_skb(rx_ring->buff_tab[i], 0);
642 if (!skb)
643 break;
644
645 skb->dev = switch_port_tab[desc->sp]->netdev;
646
647 length = desc->sdl;
648 if (desc->fsd && !desc->lsd)
649 length = RX_SEGMENT_MRU;
650
651 if (!desc->fsd) {
652 reserve -= NET_IP_ALIGN;
653 if (!desc->lsd)
654 length += NET_IP_ALIGN;
655 }
656
657 skb_reserve(skb, reserve);
658 skb_put(skb, length);
659
660 if (!sw->frag_first)
661 sw->frag_first = skb;
662 else {
663 if (sw->frag_first == sw->frag_last)
664 skb_shinfo(sw->frag_first)->frag_list = skb;
665 else
666 sw->frag_last->next = skb;
667 sw->frag_first->len += skb->len;
668 sw->frag_first->data_len += skb->len;
669 sw->frag_first->truesize += skb->truesize;
670 }
671 sw->frag_last = skb;
672
673 if (desc->lsd) {
674 struct net_device *dev;
675
676 skb = sw->frag_first;
677 dev = skb->dev;
678 skb->protocol = eth_type_trans(skb, dev);
679
680 dev->stats.rx_packets++;
681 dev->stats.rx_bytes += skb->len;
682
683 /* RX Hardware checksum offload */
684 skb->ip_summed = CHECKSUM_NONE;
685 switch (desc->prot) {
686 case 1:
687 case 2:
688 case 5:
689 case 6:
690 case 13:
691 case 14:
692 if (!desc->l4f) {
693 skb->ip_summed = CHECKSUM_UNNECESSARY;
694 napi_gro_receive(napi, skb);
695 break;
696 }
697 /* fall through */
698 default:
699 netif_receive_skb(skb);
700 break;
701 }
702
703 sw->frag_first = NULL;
704 sw->frag_last = NULL;
705 }
706
707 received++;
708 if (++i == RX_DESCS) {
709 i = 0;
710 desc = &(rx_ring)->desc[i];
711 } else {
712 desc++;
713 }
714 }
715
716 rx_ring->cur_index = i;
717 if (!received) {
718 napi_complete(napi);
719 enable_irq(sw->rx_irq);
720
721 /* if rx descriptors are full schedule another poll */
722 if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
723 eth_schedule_poll(sw);
724 }
725
726 spin_lock_bh(&tx_lock);
727 eth_complete_tx(sw);
728 spin_unlock_bh(&tx_lock);
729
730 cns3xxx_alloc_rx_buf(sw, received);
731
732 wmb();
733 enable_rx_dma(sw);
734
735 return received;
736 }
737
738 static void eth_set_desc(struct sw *sw, struct _tx_ring *tx_ring, int index,
739 int index_last, void *data, int len, u32 config0,
740 u32 pmap)
741 {
742 struct tx_desc *tx_desc = &(tx_ring)->desc[index];
743 unsigned int phys;
744
745 phys = dma_map_single(sw->dev, data, len, DMA_TO_DEVICE);
746 tx_desc->sdp = phys;
747 tx_desc->pmap = pmap;
748 tx_ring->phys_tab[index] = phys;
749
750 config0 |= len;
751 if (index == TX_DESCS - 1)
752 config0 |= END_OF_RING;
753 if (index == index_last)
754 config0 |= LAST_SEGMENT;
755
756 wmb();
757 tx_desc->config0 = config0;
758 }
759
760 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
761 {
762 struct port *port = netdev_priv(dev);
763 struct sw *sw = port->sw;
764 struct _tx_ring *tx_ring = &sw->tx_ring;
765 struct sk_buff *skb1;
766 char pmap = (1 << port->id);
767 int nr_frags = skb_shinfo(skb)->nr_frags;
768 int nr_desc = nr_frags;
769 int index0, index, index_last;
770 int len0;
771 unsigned int i;
772 u32 config0;
773
774 if (pmap == 8)
775 pmap = (1 << 4);
776
777 skb_walk_frags(skb, skb1)
778 nr_desc++;
779
780 eth_schedule_poll(sw);
781 spin_lock_bh(&tx_lock);
782 if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
783 spin_unlock_bh(&tx_lock);
784 return NETDEV_TX_BUSY;
785 }
786
787 index = index0 = tx_ring->cur_index;
788 index_last = (index0 + nr_desc) % TX_DESCS;
789 tx_ring->cur_index = (index_last + 1) % TX_DESCS;
790
791 spin_unlock_bh(&tx_lock);
792
793 config0 = FORCE_ROUTE;
794 if (skb->ip_summed == CHECKSUM_PARTIAL)
795 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
796
797 len0 = skb->len;
798
799 /* fragments */
800 for (i = 0; i < nr_frags; i++) {
801 struct skb_frag_struct *frag;
802 void *addr;
803
804 index = (index + 1) % TX_DESCS;
805
806 frag = &skb_shinfo(skb)->frags[i];
807 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
808
809 eth_set_desc(sw, tx_ring, index, index_last, addr, frag->size,
810 config0, pmap);
811 }
812
813 if (nr_frags)
814 len0 = skb->len - skb->data_len;
815
816 skb_walk_frags(skb, skb1) {
817 index = (index + 1) % TX_DESCS;
818 len0 -= skb1->len;
819
820 eth_set_desc(sw, tx_ring, index, index_last, skb1->data,
821 skb1->len, config0, pmap);
822 }
823
824 tx_ring->buff_tab[index0] = skb;
825 eth_set_desc(sw, tx_ring, index0, index_last, skb->data, len0,
826 config0 | FIRST_SEGMENT, pmap);
827
828 wmb();
829
830 spin_lock(&tx_lock);
831 tx_ring->num_used += nr_desc + 1;
832 spin_unlock(&tx_lock);
833
834 dev->stats.tx_packets++;
835 dev->stats.tx_bytes += skb->len;
836
837 enable_tx_dma(sw);
838
839 return NETDEV_TX_OK;
840 }
841
842 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
843 {
844 struct port *port = netdev_priv(dev);
845
846 if (!netif_running(dev))
847 return -EINVAL;
848 return phy_mii_ioctl(port->phydev, req, cmd);
849 }
850
851 /* ethtool support */
852
853 static void cns3xxx_get_drvinfo(struct net_device *dev,
854 struct ethtool_drvinfo *info)
855 {
856 strcpy(info->driver, DRV_NAME);
857 strcpy(info->bus_info, "internal");
858 }
859
860 static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
861 {
862 struct port *port = netdev_priv(dev);
863 return phy_ethtool_gset(port->phydev, cmd);
864 }
865
866 static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
867 {
868 struct port *port = netdev_priv(dev);
869 return phy_ethtool_sset(port->phydev, cmd);
870 }
871
872 static int cns3xxx_nway_reset(struct net_device *dev)
873 {
874 struct port *port = netdev_priv(dev);
875 return phy_start_aneg(port->phydev);
876 }
877
878 static struct ethtool_ops cns3xxx_ethtool_ops = {
879 .get_drvinfo = cns3xxx_get_drvinfo,
880 .get_settings = cns3xxx_get_settings,
881 .set_settings = cns3xxx_set_settings,
882 .nway_reset = cns3xxx_nway_reset,
883 .get_link = ethtool_op_get_link,
884 };
885
886
887 static int init_rings(struct sw *sw)
888 {
889 int i;
890 struct _rx_ring *rx_ring = &sw->rx_ring;
891 struct _tx_ring *tx_ring = &sw->tx_ring;
892
893 __raw_writel(0, &sw->regs->fs_dma_ctrl0);
894 __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
895 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
896 __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
897
898 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
899
900 if (!(rx_dma_pool = dma_pool_create(DRV_NAME, sw->dev,
901 RX_POOL_ALLOC_SIZE, 32, 0)))
902 return -ENOMEM;
903
904 if (!(rx_ring->desc = dma_pool_alloc(rx_dma_pool, GFP_KERNEL,
905 &rx_ring->phys_addr)))
906 return -ENOMEM;
907 memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
908
909 /* Setup RX buffers */
910 for (i = 0; i < RX_DESCS; i++) {
911 struct rx_desc *desc = &(rx_ring)->desc[i];
912 void *buf;
913
914 buf = kzalloc(RX_SEGMENT_ALLOC_SIZE, GFP_KERNEL);
915 if (!buf)
916 return -ENOMEM;
917
918 desc->sdl = RX_SEGMENT_MRU;
919 if (i == (RX_DESCS - 1))
920 desc->eor = 1;
921 desc->fsd = 1;
922 desc->lsd = 1;
923
924 desc->sdp = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
925 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
926 if (dma_mapping_error(sw->dev, desc->sdp))
927 return -EIO;
928
929 rx_ring->buff_tab[i] = buf;
930 rx_ring->phys_tab[i] = desc->sdp;
931 desc->cown = 0;
932 }
933 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
934 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
935
936 if (!(tx_dma_pool = dma_pool_create(DRV_NAME, sw->dev,
937 TX_POOL_ALLOC_SIZE, 32, 0)))
938 return -ENOMEM;
939
940 if (!(tx_ring->desc = dma_pool_alloc(tx_dma_pool, GFP_KERNEL,
941 &tx_ring->phys_addr)))
942 return -ENOMEM;
943 memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
944
945 /* Setup TX buffers */
946 for (i = 0; i < TX_DESCS; i++) {
947 struct tx_desc *desc = &(tx_ring)->desc[i];
948 tx_ring->buff_tab[i] = 0;
949
950 if (i == (TX_DESCS - 1))
951 desc->eor = 1;
952 desc->cown = 1;
953 }
954 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
955 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
956
957 return 0;
958 }
959
960 static void destroy_rings(struct sw *sw)
961 {
962 int i;
963 if (sw->rx_ring.desc) {
964 for (i = 0; i < RX_DESCS; i++) {
965 struct _rx_ring *rx_ring = &sw->rx_ring;
966 struct rx_desc *desc = &(rx_ring)->desc[i];
967 struct sk_buff *skb = sw->rx_ring.buff_tab[i];
968
969 if (!skb)
970 continue;
971
972 dma_unmap_single(sw->dev, desc->sdp, RX_SEGMENT_MRU,
973 DMA_FROM_DEVICE);
974 dev_kfree_skb(skb);
975 }
976 dma_pool_free(rx_dma_pool, sw->rx_ring.desc, sw->rx_ring.phys_addr);
977 dma_pool_destroy(rx_dma_pool);
978 rx_dma_pool = 0;
979 sw->rx_ring.desc = 0;
980 }
981 if (sw->tx_ring.desc) {
982 for (i = 0; i < TX_DESCS; i++) {
983 struct _tx_ring *tx_ring = &sw->tx_ring;
984 struct tx_desc *desc = &(tx_ring)->desc[i];
985 struct sk_buff *skb = sw->tx_ring.buff_tab[i];
986 if (skb) {
987 dma_unmap_single(sw->dev, desc->sdp,
988 skb->len, DMA_TO_DEVICE);
989 dev_kfree_skb(skb);
990 }
991 }
992 dma_pool_free(tx_dma_pool, sw->tx_ring.desc, sw->tx_ring.phys_addr);
993 dma_pool_destroy(tx_dma_pool);
994 tx_dma_pool = 0;
995 sw->tx_ring.desc = 0;
996 }
997 }
998
999 static int eth_open(struct net_device *dev)
1000 {
1001 struct port *port = netdev_priv(dev);
1002 struct sw *sw = port->sw;
1003 u32 temp;
1004
1005 port->speed = 0; /* force "link up" message */
1006 phy_start(port->phydev);
1007
1008 netif_start_queue(dev);
1009
1010 if (!ports_open) {
1011 request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
1012 request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
1013 napi_enable(&sw->napi);
1014 netif_start_queue(napi_dev);
1015
1016 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
1017 MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
1018
1019 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1020 temp &= ~(PORT_DISABLE);
1021 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1022
1023 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
1024 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1025 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1026
1027 enable_rx_dma(sw);
1028 }
1029 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1030 temp &= ~(PORT_DISABLE);
1031 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1032
1033 ports_open++;
1034 netif_carrier_on(dev);
1035
1036 return 0;
1037 }
1038
1039 static int eth_close(struct net_device *dev)
1040 {
1041 struct port *port = netdev_priv(dev);
1042 struct sw *sw = port->sw;
1043 u32 temp;
1044
1045 ports_open--;
1046
1047 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1048 temp |= (PORT_DISABLE);
1049 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1050
1051 netif_stop_queue(dev);
1052
1053 phy_stop(port->phydev);
1054
1055 if (!ports_open) {
1056 disable_irq(sw->rx_irq);
1057 free_irq(sw->rx_irq, napi_dev);
1058 disable_irq(sw->stat_irq);
1059 free_irq(sw->stat_irq, napi_dev);
1060 napi_disable(&sw->napi);
1061 netif_stop_queue(napi_dev);
1062 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1063 temp |= (PORT_DISABLE);
1064 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1065
1066 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1067 &sw->regs->dma_auto_poll_cfg);
1068 }
1069
1070 netif_carrier_off(dev);
1071 return 0;
1072 }
1073
1074 static void eth_rx_mode(struct net_device *dev)
1075 {
1076 struct port *port = netdev_priv(dev);
1077 struct sw *sw = port->sw;
1078 u32 temp;
1079
1080 temp = __raw_readl(&sw->regs->mac_glob_cfg);
1081
1082 if (dev->flags & IFF_PROMISC) {
1083 if (port->id == 3)
1084 temp |= ((1 << 2) << PROMISC_OFFSET);
1085 else
1086 temp |= ((1 << port->id) << PROMISC_OFFSET);
1087 } else {
1088 if (port->id == 3)
1089 temp &= ~((1 << 2) << PROMISC_OFFSET);
1090 else
1091 temp &= ~((1 << port->id) << PROMISC_OFFSET);
1092 }
1093 __raw_writel(temp, &sw->regs->mac_glob_cfg);
1094 }
1095
1096 static int eth_set_mac(struct net_device *netdev, void *p)
1097 {
1098 struct port *port = netdev_priv(netdev);
1099 struct sw *sw = port->sw;
1100 struct sockaddr *addr = p;
1101 u32 cycles = 0;
1102
1103 if (!is_valid_ether_addr(addr->sa_data))
1104 return -EADDRNOTAVAIL;
1105
1106 /* Invalidate old ARL Entry */
1107 if (port->id == 3)
1108 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1109 else
1110 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1111 __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1112 (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1113 &sw->regs->arl_ctrl[1]);
1114
1115 __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1116 (1 << 1)),
1117 &sw->regs->arl_ctrl[2]);
1118 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1119
1120 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1121 && cycles < 5000) {
1122 udelay(1);
1123 cycles++;
1124 }
1125
1126 cycles = 0;
1127 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1128
1129 if (port->id == 3)
1130 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1131 else
1132 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1133 __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1134 (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1135 &sw->regs->arl_ctrl[1]);
1136
1137 __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1138 (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1139 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1140
1141 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1142 && cycles < 5000) {
1143 udelay(1);
1144 cycles++;
1145 }
1146 return 0;
1147 }
1148
1149 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1150 {
1151 if (new_mtu > MAX_MTU)
1152 return -EINVAL;
1153
1154 dev->mtu = new_mtu;
1155 return 0;
1156 }
1157
1158 static const struct net_device_ops cns3xxx_netdev_ops = {
1159 .ndo_open = eth_open,
1160 .ndo_stop = eth_close,
1161 .ndo_start_xmit = eth_xmit,
1162 .ndo_set_rx_mode = eth_rx_mode,
1163 .ndo_do_ioctl = eth_ioctl,
1164 .ndo_change_mtu = cns3xxx_change_mtu,
1165 .ndo_set_mac_address = eth_set_mac,
1166 .ndo_validate_addr = eth_validate_addr,
1167 };
1168
1169 static int eth_init_one(struct platform_device *pdev)
1170 {
1171 int i;
1172 struct port *port;
1173 struct sw *sw;
1174 struct net_device *dev;
1175 struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1176 char phy_id[MII_BUS_ID_SIZE + 3];
1177 int err;
1178 u32 temp;
1179 struct resource *res;
1180 void __iomem *regs;
1181
1182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 regs = devm_ioremap_resource(&pdev->dev, res);
1184 if (IS_ERR(regs))
1185 return PTR_ERR(regs);
1186
1187 err = cns3xxx_mdio_register(regs);
1188 if (err)
1189 return err;
1190
1191 if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
1192 err = -ENOMEM;
1193 goto err_remove_mdio;
1194 }
1195
1196 strcpy(napi_dev->name, "switch%d");
1197 napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1198
1199 SET_NETDEV_DEV(napi_dev, &pdev->dev);
1200 sw = netdev_priv(napi_dev);
1201 memset(sw, 0, sizeof(struct sw));
1202 sw->regs = regs;
1203 sw->dev = &pdev->dev;
1204
1205 sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
1206 sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
1207
1208 temp = __raw_readl(&sw->regs->phy_auto_addr);
1209 temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1210 __raw_writel(temp, &sw->regs->phy_auto_addr);
1211
1212 for (i = 0; i < 4; i++) {
1213 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1214 temp |= (PORT_DISABLE);
1215 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1216 }
1217
1218 temp = PORT_DISABLE;
1219 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1220
1221 temp = __raw_readl(&sw->regs->vlan_cfg);
1222 temp |= NIC_MODE | VLAN_UNAWARE;
1223 __raw_writel(temp, &sw->regs->vlan_cfg);
1224
1225 __raw_writel(UNKNOWN_VLAN_TO_CPU |
1226 CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1227
1228 if ((err = init_rings(sw)) != 0) {
1229 destroy_rings(sw);
1230 err = -ENOMEM;
1231 goto err_free;
1232 }
1233 platform_set_drvdata(pdev, napi_dev);
1234
1235 netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1236
1237 for (i = 0; i < 3; i++) {
1238 if (!(plat->ports & (1 << i))) {
1239 continue;
1240 }
1241
1242 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1243 goto free_ports;
1244 }
1245
1246 port = netdev_priv(dev);
1247 port->netdev = dev;
1248 if (i == 2)
1249 port->id = 3;
1250 else
1251 port->id = i;
1252 port->sw = sw;
1253
1254 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1255 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1256 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1257
1258 SET_NETDEV_DEV(dev, &pdev->dev);
1259 dev->netdev_ops = &cns3xxx_netdev_ops;
1260 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1261 dev->tx_queue_len = 1000;
1262 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1263
1264 switch_port_tab[port->id] = port;
1265 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1266
1267 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1268 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
1269 PHY_INTERFACE_MODE_RGMII);
1270 if ((err = IS_ERR(port->phydev))) {
1271 switch_port_tab[port->id] = 0;
1272 free_netdev(dev);
1273 goto free_ports;
1274 }
1275
1276 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1277
1278 if ((err = register_netdev(dev))) {
1279 phy_disconnect(port->phydev);
1280 switch_port_tab[port->id] = 0;
1281 free_netdev(dev);
1282 goto free_ports;
1283 }
1284
1285 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1286 netif_carrier_off(dev);
1287 dev = 0;
1288 }
1289
1290 return 0;
1291
1292 free_ports:
1293 err = -ENOMEM;
1294 for (--i; i >= 0; i--) {
1295 if (switch_port_tab[i]) {
1296 port = switch_port_tab[i];
1297 dev = port->netdev;
1298 unregister_netdev(dev);
1299 phy_disconnect(port->phydev);
1300 switch_port_tab[i] = 0;
1301 free_netdev(dev);
1302 }
1303 }
1304 err_free:
1305 free_netdev(napi_dev);
1306 err_remove_mdio:
1307 cns3xxx_mdio_remove();
1308 return err;
1309 }
1310
1311 static int eth_remove_one(struct platform_device *pdev)
1312 {
1313 struct net_device *dev = platform_get_drvdata(pdev);
1314 struct sw *sw = netdev_priv(dev);
1315 int i;
1316 destroy_rings(sw);
1317
1318 for (i = 3; i >= 0; i--) {
1319 if (switch_port_tab[i]) {
1320 struct port *port = switch_port_tab[i];
1321 struct net_device *dev = port->netdev;
1322 unregister_netdev(dev);
1323 phy_disconnect(port->phydev);
1324 switch_port_tab[i] = 0;
1325 free_netdev(dev);
1326 }
1327 }
1328
1329 free_netdev(napi_dev);
1330 cns3xxx_mdio_remove();
1331
1332 return 0;
1333 }
1334
1335 static struct platform_driver cns3xxx_eth_driver = {
1336 .driver.name = DRV_NAME,
1337 .probe = eth_init_one,
1338 .remove = eth_remove_one,
1339 };
1340
1341 static int __init eth_init_module(void)
1342 {
1343 return platform_driver_register(&cns3xxx_eth_driver);
1344 }
1345
1346 static void __exit eth_cleanup_module(void)
1347 {
1348 platform_driver_unregister(&cns3xxx_eth_driver);
1349 }
1350
1351 module_init(eth_init_module);
1352 module_exit(eth_cleanup_module);
1353
1354 MODULE_AUTHOR("Chris Lang");
1355 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1356 MODULE_LICENSE("GPL v2");
1357 MODULE_ALIAS("platform:cns3xxx_eth");
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