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cns3xxx: ethernet: cleanup code
[openwrt/staging/dedeckeh.git] / target / linux / cns3xxx / files / drivers / net / ethernet / cavium / cns3xxx_eth.c
1 /*
2 * Cavium CNS3xxx Gigabit driver for Linux
3 *
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
25
26 #define DRV_NAME "cns3xxx_eth"
27
28 #define RX_DESCS 256
29 #define TX_DESCS 128
30 #define TX_DESC_RESERVE 20
31
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
34 #define REGS_SIZE 336
35
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
38
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
43 #define MAX_MTU 9500
44
45 #define NAPI_WEIGHT 64
46
47 /* MDIO Defines */
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
53
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define UDP_CHECKSUM 0x00020000
60 #define TCP_CHECKSUM 0x00010000
61
62 /* Port Config Defines */
63 #define PORT_BP_ENABLE 0x00020000
64 #define PORT_DISABLE 0x00040000
65 #define PORT_LEARN_DIS 0x00080000
66 #define PORT_BLOCK_STATE 0x00100000
67 #define PORT_BLOCK_MODE 0x00200000
68
69 #define PROMISC_OFFSET 29
70
71 /* Global Config Defines */
72 #define UNKNOWN_VLAN_TO_CPU 0x02000000
73 #define ACCEPT_CRC_PACKET 0x00200000
74 #define CRC_STRIPPING 0x00100000
75
76 /* VLAN Config Defines */
77 #define NIC_MODE 0x00008000
78 #define VLAN_UNAWARE 0x00000001
79
80 /* DMA AUTO Poll Defines */
81 #define TS_POLL_EN 0x00000020
82 #define TS_SUSPEND 0x00000010
83 #define FS_POLL_EN 0x00000002
84 #define FS_SUSPEND 0x00000001
85
86 /* DMA Ring Control Defines */
87 #define QUEUE_THRESHOLD 0x000000f0
88 #define CLR_FS_STATE 0x80000000
89
90 /* Interrupt Status Defines */
91 #define MAC0_STATUS_CHANGE 0x00004000
92 #define MAC1_STATUS_CHANGE 0x00008000
93 #define MAC2_STATUS_CHANGE 0x00010000
94 #define MAC0_RX_ERROR 0x00100000
95 #define MAC1_RX_ERROR 0x00200000
96 #define MAC2_RX_ERROR 0x00400000
97
98 struct tx_desc
99 {
100 u32 sdp; /* segment data pointer */
101
102 union {
103 struct {
104 u32 sdl:16; /* segment data length */
105 u32 tco:1;
106 u32 uco:1;
107 u32 ico:1;
108 u32 rsv_1:3; /* reserve */
109 u32 pri:3;
110 u32 fp:1; /* force priority */
111 u32 fr:1;
112 u32 interrupt:1;
113 u32 lsd:1;
114 u32 fsd:1;
115 u32 eor:1;
116 u32 cown:1;
117 };
118 u32 config0;
119 };
120
121 union {
122 struct {
123 u32 ctv:1;
124 u32 stv:1;
125 u32 sid:4;
126 u32 inss:1;
127 u32 dels:1;
128 u32 rsv_2:9;
129 u32 pmap:5;
130 u32 mark:3;
131 u32 ewan:1;
132 u32 fewan:1;
133 u32 rsv_3:5;
134 };
135 u32 config1;
136 };
137
138 union {
139 struct {
140 u32 c_vid:12;
141 u32 c_cfs:1;
142 u32 c_pri:3;
143 u32 s_vid:12;
144 u32 s_dei:1;
145 u32 s_pri:3;
146 };
147 u32 config2;
148 };
149
150 u8 alignment[16]; /* for 32 byte */
151 };
152
153 struct rx_desc
154 {
155 u32 sdp; /* segment data pointer */
156
157 union {
158 struct {
159 u32 sdl:16; /* segment data length */
160 u32 l4f:1;
161 u32 ipf:1;
162 u32 prot:4;
163 u32 hr:6;
164 u32 lsd:1;
165 u32 fsd:1;
166 u32 eor:1;
167 u32 cown:1;
168 };
169 u32 config0;
170 };
171
172 union {
173 struct {
174 u32 ctv:1;
175 u32 stv:1;
176 u32 unv:1;
177 u32 iwan:1;
178 u32 exdv:1;
179 u32 e_wan:1;
180 u32 rsv_1:2;
181 u32 sp:3;
182 u32 crc_err:1;
183 u32 un_eth:1;
184 u32 tc:2;
185 u32 rsv_2:1;
186 u32 ip_offset:5;
187 u32 rsv_3:11;
188 };
189 u32 config1;
190 };
191
192 union {
193 struct {
194 u32 c_vid:12;
195 u32 c_cfs:1;
196 u32 c_pri:3;
197 u32 s_vid:12;
198 u32 s_dei:1;
199 u32 s_pri:3;
200 };
201 u32 config2;
202 };
203
204 u8 alignment[16]; /* for 32 byte alignment */
205 };
206
207
208 struct switch_regs {
209 u32 phy_control;
210 u32 phy_auto_addr;
211 u32 mac_glob_cfg;
212 u32 mac_cfg[4];
213 u32 mac_pri_ctrl[5], __res;
214 u32 etype[2];
215 u32 udp_range[4];
216 u32 prio_etype_udp;
217 u32 prio_ipdscp[8];
218 u32 tc_ctrl;
219 u32 rate_ctrl;
220 u32 fc_glob_thrs;
221 u32 fc_port_thrs;
222 u32 mc_fc_glob_thrs;
223 u32 dc_glob_thrs;
224 u32 arl_vlan_cmd;
225 u32 arl_ctrl[3];
226 u32 vlan_cfg;
227 u32 pvid[2];
228 u32 vlan_ctrl[3];
229 u32 session_id[8];
230 u32 intr_stat;
231 u32 intr_mask;
232 u32 sram_test;
233 u32 mem_queue;
234 u32 farl_ctrl;
235 u32 fc_input_thrs, __res1[2];
236 u32 clk_skew_ctrl;
237 u32 mac_glob_cfg_ext, __res2[2];
238 u32 dma_ring_ctrl;
239 u32 dma_auto_poll_cfg;
240 u32 delay_intr_cfg, __res3;
241 u32 ts_dma_ctrl0;
242 u32 ts_desc_ptr0;
243 u32 ts_desc_base_addr0, __res4;
244 u32 fs_dma_ctrl0;
245 u32 fs_desc_ptr0;
246 u32 fs_desc_base_addr0, __res5;
247 u32 ts_dma_ctrl1;
248 u32 ts_desc_ptr1;
249 u32 ts_desc_base_addr1, __res6;
250 u32 fs_dma_ctrl1;
251 u32 fs_desc_ptr1;
252 u32 fs_desc_base_addr1;
253 u32 __res7[109];
254 u32 mac_counter0[13];
255 };
256
257 struct _tx_ring {
258 struct tx_desc *desc;
259 dma_addr_t phys_addr;
260 struct tx_desc *cur_addr;
261 struct sk_buff *buff_tab[TX_DESCS];
262 unsigned int phys_tab[TX_DESCS];
263 u32 free_index;
264 u32 count_index;
265 u32 cur_index;
266 int num_used;
267 int num_count;
268 bool stopped;
269 };
270
271 struct _rx_ring {
272 struct rx_desc *desc;
273 dma_addr_t phys_addr;
274 struct rx_desc *cur_addr;
275 void *buff_tab[RX_DESCS];
276 unsigned int phys_tab[RX_DESCS];
277 u32 cur_index;
278 u32 alloc_index;
279 int alloc_count;
280 };
281
282 struct sw {
283 struct switch_regs __iomem *regs;
284 struct napi_struct napi;
285 struct cns3xxx_plat_info *plat;
286 struct _tx_ring tx_ring;
287 struct _rx_ring rx_ring;
288 struct sk_buff *frag_first;
289 struct sk_buff *frag_last;
290 struct device *dev;
291 int rx_irq;
292 int stat_irq;
293 };
294
295 struct port {
296 struct net_device *netdev;
297 struct phy_device *phydev;
298 struct sw *sw;
299 int id; /* logical port ID */
300 int speed, duplex;
301 };
302
303 static spinlock_t mdio_lock;
304 static DEFINE_SPINLOCK(tx_lock);
305 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
306 struct mii_bus *mdio_bus;
307 static int ports_open;
308 static struct port *switch_port_tab[4];
309 struct net_device *napi_dev;
310
311 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
312 int write, u16 cmd)
313 {
314 int cycles = 0;
315 u32 temp = 0;
316
317 temp = __raw_readl(&mdio_regs->phy_control);
318 temp |= MDIO_CMD_COMPLETE;
319 __raw_writel(temp, &mdio_regs->phy_control);
320 udelay(10);
321
322 if (write) {
323 temp = (cmd << MDIO_VALUE_OFFSET);
324 temp |= MDIO_WRITE_COMMAND;
325 } else {
326 temp = MDIO_READ_COMMAND;
327 }
328
329 temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
330 temp |= (phy_id & 0x1f);
331
332 __raw_writel(temp, &mdio_regs->phy_control);
333
334 while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
335 && cycles < 5000) {
336 udelay(1);
337 cycles++;
338 }
339
340 if (cycles == 5000) {
341 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name, phy_id);
342 return -1;
343 }
344
345 temp = __raw_readl(&mdio_regs->phy_control);
346 temp |= MDIO_CMD_COMPLETE;
347 __raw_writel(temp, &mdio_regs->phy_control);
348
349 if (write)
350 return 0;
351
352 return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
353 }
354
355 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
356 {
357 unsigned long flags;
358 int ret;
359
360 spin_lock_irqsave(&mdio_lock, flags);
361 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
362 spin_unlock_irqrestore(&mdio_lock, flags);
363 return ret;
364 }
365
366 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location, u16 val)
367 {
368 unsigned long flags;
369 int ret;
370
371 spin_lock_irqsave(&mdio_lock, flags);
372 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
373 spin_unlock_irqrestore(&mdio_lock, flags);
374 return ret;
375 }
376
377 static int cns3xxx_mdio_register(void __iomem *base)
378 {
379 int err;
380
381 if (!(mdio_bus = mdiobus_alloc()))
382 return -ENOMEM;
383
384 mdio_regs = base;
385
386 spin_lock_init(&mdio_lock);
387 mdio_bus->name = "CNS3xxx MII Bus";
388 mdio_bus->read = &cns3xxx_mdio_read;
389 mdio_bus->write = &cns3xxx_mdio_write;
390 strcpy(mdio_bus->id, "0");
391
392 if ((err = mdiobus_register(mdio_bus)))
393 mdiobus_free(mdio_bus);
394
395 return err;
396 }
397
398 static void cns3xxx_mdio_remove(void)
399 {
400 mdiobus_unregister(mdio_bus);
401 mdiobus_free(mdio_bus);
402 }
403
404 static void enable_tx_dma(struct sw *sw)
405 {
406 __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
407 }
408
409 static void enable_rx_dma(struct sw *sw)
410 {
411 __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
412 }
413
414 static void cns3xxx_adjust_link(struct net_device *dev)
415 {
416 struct port *port = netdev_priv(dev);
417 struct phy_device *phydev = port->phydev;
418
419 if (!phydev->link) {
420 if (port->speed) {
421 port->speed = 0;
422 printk(KERN_INFO "%s: link down\n", dev->name);
423 }
424 return;
425 }
426
427 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
428 return;
429
430 port->speed = phydev->speed;
431 port->duplex = phydev->duplex;
432
433 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
434 dev->name, port->speed, port->duplex ? "full" : "half");
435 }
436
437 static void eth_schedule_poll(struct sw *sw)
438 {
439 if (unlikely(!napi_schedule_prep(&sw->napi)))
440 return;
441
442 disable_irq_nosync(sw->rx_irq);
443 __napi_schedule(&sw->napi);
444 }
445
446 irqreturn_t eth_rx_irq(int irq, void *pdev)
447 {
448 struct net_device *dev = pdev;
449 struct sw *sw = netdev_priv(dev);
450 eth_schedule_poll(sw);
451 return (IRQ_HANDLED);
452 }
453
454 irqreturn_t eth_stat_irq(int irq, void *pdev)
455 {
456 struct net_device *dev = pdev;
457 struct sw *sw = netdev_priv(dev);
458 u32 cfg;
459 u32 stat = __raw_readl(&sw->regs->intr_stat);
460 __raw_writel(0xffffffff, &sw->regs->intr_stat);
461
462 if (stat & MAC2_RX_ERROR)
463 switch_port_tab[3]->netdev->stats.rx_dropped++;
464 if (stat & MAC1_RX_ERROR)
465 switch_port_tab[1]->netdev->stats.rx_dropped++;
466 if (stat & MAC0_RX_ERROR)
467 switch_port_tab[0]->netdev->stats.rx_dropped++;
468
469 if (stat & MAC0_STATUS_CHANGE) {
470 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
471 switch_port_tab[0]->phydev->link = (cfg & 0x1);
472 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
473 if (((cfg >> 2) & 0x3) == 2)
474 switch_port_tab[0]->phydev->speed = 1000;
475 else if (((cfg >> 2) & 0x3) == 1)
476 switch_port_tab[0]->phydev->speed = 100;
477 else
478 switch_port_tab[0]->phydev->speed = 10;
479 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
480 }
481
482 if (stat & MAC1_STATUS_CHANGE) {
483 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
484 switch_port_tab[1]->phydev->link = (cfg & 0x1);
485 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
486 if (((cfg >> 2) & 0x3) == 2)
487 switch_port_tab[1]->phydev->speed = 1000;
488 else if (((cfg >> 2) & 0x3) == 1)
489 switch_port_tab[1]->phydev->speed = 100;
490 else
491 switch_port_tab[1]->phydev->speed = 10;
492 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
493 }
494
495 if (stat & MAC2_STATUS_CHANGE) {
496 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
497 switch_port_tab[3]->phydev->link = (cfg & 0x1);
498 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
499 if (((cfg >> 2) & 0x3) == 2)
500 switch_port_tab[3]->phydev->speed = 1000;
501 else if (((cfg >> 2) & 0x3) == 1)
502 switch_port_tab[3]->phydev->speed = 100;
503 else
504 switch_port_tab[3]->phydev->speed = 10;
505 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
506 }
507
508 return (IRQ_HANDLED);
509 }
510
511
512 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
513 {
514 struct _rx_ring *rx_ring = &sw->rx_ring;
515 unsigned int i = rx_ring->alloc_index;
516 struct rx_desc *desc = &(rx_ring)->desc[i];
517 void *buf;
518 unsigned int phys;
519
520 for (received += rx_ring->alloc_count; received > 0; received--) {
521 buf = napi_alloc_frag(RX_SEGMENT_ALLOC_SIZE);
522 if (!buf)
523 break;
524
525 phys = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
526 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
527 if (dma_mapping_error(sw->dev, phys)) {
528 skb_free_frag(buf);
529 break;
530 }
531
532 desc->sdl = RX_SEGMENT_MRU;
533 desc->sdp = phys;
534
535 wmb();
536
537 /* put the new buffer on RX-free queue */
538 rx_ring->buff_tab[i] = buf;
539 rx_ring->phys_tab[i] = phys;
540
541 if (i == RX_DESCS - 1) {
542 desc->config0 = FIRST_SEGMENT | LAST_SEGMENT | RX_SEGMENT_MRU | END_OF_RING;
543 i = 0;
544 desc = &(rx_ring)->desc[i];
545 } else {
546 desc->config0 = FIRST_SEGMENT | LAST_SEGMENT | RX_SEGMENT_MRU;
547 i++;
548 desc++;
549 }
550 }
551
552 rx_ring->alloc_count = received;
553 rx_ring->alloc_index = i;
554 }
555
556 static void eth_check_num_used(struct _tx_ring *tx_ring)
557 {
558 bool stop = false;
559 int i;
560
561 if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
562 stop = true;
563
564 if (tx_ring->stopped == stop)
565 return;
566
567 tx_ring->stopped = stop;
568
569 for (i = 0; i < 4; i++) {
570 struct port *port = switch_port_tab[i];
571 struct net_device *dev;
572
573 if (!port)
574 continue;
575
576 dev = port->netdev;
577
578 if (stop)
579 netif_stop_queue(dev);
580 else
581 netif_wake_queue(dev);
582 }
583 }
584
585 static void eth_complete_tx(struct sw *sw)
586 {
587 struct _tx_ring *tx_ring = &sw->tx_ring;
588 struct tx_desc *desc;
589 int i;
590 int index;
591 int num_used = tx_ring->num_used;
592 struct sk_buff *skb;
593
594 index = tx_ring->free_index;
595 desc = &(tx_ring)->desc[index];
596
597 for (i = 0; i < num_used; i++) {
598 if (desc->cown) {
599 skb = tx_ring->buff_tab[index];
600 tx_ring->buff_tab[index] = 0;
601 if (skb)
602 dev_kfree_skb_any(skb);
603 dma_unmap_single(sw->dev, tx_ring->phys_tab[index],
604 desc->sdl, DMA_TO_DEVICE);
605 if (++index == TX_DESCS) {
606 index = 0;
607 desc = &(tx_ring)->desc[index];
608 } else {
609 desc++;
610 }
611 } else {
612 break;
613 }
614 }
615
616 tx_ring->free_index = index;
617 tx_ring->num_used -= i;
618 eth_check_num_used(tx_ring);
619 }
620
621 static int eth_poll(struct napi_struct *napi, int budget)
622 {
623 struct sw *sw = container_of(napi, struct sw, napi);
624 struct _rx_ring *rx_ring = &sw->rx_ring;
625 int received = 0;
626 unsigned int length;
627 unsigned int i = rx_ring->cur_index;
628 struct rx_desc *desc = &(rx_ring)->desc[i];
629 unsigned int alloc_count = rx_ring->alloc_count;
630
631 while (desc->cown && alloc_count + received < RX_DESCS - 1) {
632 struct sk_buff *skb;
633 int reserve = SKB_HEAD_ALIGN;
634
635 if (received >= budget)
636 break;
637
638 /* process received frame */
639 dma_unmap_single(sw->dev, rx_ring->phys_tab[i], RX_SEGMENT_MRU, DMA_FROM_DEVICE);
640
641 skb = build_skb(rx_ring->buff_tab[i], RX_SEGMENT_ALLOC_SIZE);
642 if (!skb)
643 break;
644
645 skb->dev = switch_port_tab[desc->sp]->netdev;
646
647 length = desc->sdl;
648 if (desc->fsd && !desc->lsd)
649 length = RX_SEGMENT_MRU;
650
651 if (!desc->fsd) {
652 reserve -= NET_IP_ALIGN;
653 if (!desc->lsd)
654 length += NET_IP_ALIGN;
655 }
656
657 skb_reserve(skb, reserve);
658 skb_put(skb, length);
659
660 if (!sw->frag_first)
661 sw->frag_first = skb;
662 else {
663 if (sw->frag_first == sw->frag_last)
664 skb_shinfo(sw->frag_first)->frag_list = skb;
665 else
666 sw->frag_last->next = skb;
667 sw->frag_first->len += skb->len;
668 sw->frag_first->data_len += skb->len;
669 sw->frag_first->truesize += skb->truesize;
670 }
671 sw->frag_last = skb;
672
673 if (desc->lsd) {
674 struct net_device *dev;
675
676 skb = sw->frag_first;
677 dev = skb->dev;
678 skb->protocol = eth_type_trans(skb, dev);
679
680 dev->stats.rx_packets++;
681 dev->stats.rx_bytes += skb->len;
682
683 /* RX Hardware checksum offload */
684 skb->ip_summed = CHECKSUM_NONE;
685 switch (desc->prot) {
686 case 1:
687 case 2:
688 case 5:
689 case 6:
690 case 13:
691 case 14:
692 if (!desc->l4f) {
693 skb->ip_summed = CHECKSUM_UNNECESSARY;
694 napi_gro_receive(napi, skb);
695 break;
696 }
697 /* fall through */
698 default:
699 netif_receive_skb(skb);
700 break;
701 }
702
703 sw->frag_first = NULL;
704 sw->frag_last = NULL;
705 }
706
707 received++;
708 if (++i == RX_DESCS) {
709 i = 0;
710 desc = &(rx_ring)->desc[i];
711 } else {
712 desc++;
713 }
714 }
715
716 rx_ring->cur_index = i;
717
718 cns3xxx_alloc_rx_buf(sw, received);
719 wmb();
720 enable_rx_dma(sw);
721
722 if (received < budget && napi_complete_done(napi, received)) {
723 enable_irq(sw->rx_irq);
724 }
725
726 spin_lock_bh(&tx_lock);
727 eth_complete_tx(sw);
728 spin_unlock_bh(&tx_lock);
729
730 return received;
731 }
732
733 static void eth_set_desc(struct sw *sw, struct _tx_ring *tx_ring, int index,
734 int index_last, void *data, int len, u32 config0,
735 u32 pmap)
736 {
737 struct tx_desc *tx_desc = &(tx_ring)->desc[index];
738 unsigned int phys;
739
740 phys = dma_map_single(sw->dev, data, len, DMA_TO_DEVICE);
741 tx_desc->sdp = phys;
742 tx_desc->pmap = pmap;
743 tx_ring->phys_tab[index] = phys;
744
745 config0 |= len;
746
747 if (index == TX_DESCS - 1)
748 config0 |= END_OF_RING;
749
750 if (index == index_last)
751 config0 |= LAST_SEGMENT;
752
753 wmb();
754 tx_desc->config0 = config0;
755 }
756
757 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
758 {
759 struct port *port = netdev_priv(dev);
760 struct sw *sw = port->sw;
761 struct _tx_ring *tx_ring = &sw->tx_ring;
762 struct sk_buff *skb1;
763 char pmap = (1 << port->id);
764 int nr_frags = skb_shinfo(skb)->nr_frags;
765 int nr_desc = nr_frags;
766 int index0, index, index_last;
767 int len0;
768 int i;
769 u32 config0;
770
771 if (pmap == 8)
772 pmap = (1 << 4);
773
774 skb_walk_frags(skb, skb1)
775 nr_desc++;
776
777 eth_schedule_poll(sw);
778 spin_lock_bh(&tx_lock);
779
780 if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
781 spin_unlock_bh(&tx_lock);
782 return NETDEV_TX_BUSY;
783 }
784
785 index = index0 = tx_ring->cur_index;
786 index_last = (index0 + nr_desc) % TX_DESCS;
787 tx_ring->cur_index = (index_last + 1) % TX_DESCS;
788
789 spin_unlock_bh(&tx_lock);
790
791 config0 = FORCE_ROUTE;
792 if (skb->ip_summed == CHECKSUM_PARTIAL)
793 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
794
795 len0 = skb->len;
796
797 /* fragments */
798 for (i = 0; i < nr_frags; i++) {
799 struct skb_frag_struct *frag;
800 void *addr;
801
802 index = (index + 1) % TX_DESCS;
803
804 frag = &skb_shinfo(skb)->frags[i];
805 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
806
807 eth_set_desc(sw, tx_ring, index, index_last, addr, frag->size,
808 config0, pmap);
809 }
810
811 if (nr_frags)
812 len0 = skb->len - skb->data_len;
813
814 skb_walk_frags(skb, skb1) {
815 index = (index + 1) % TX_DESCS;
816 len0 -= skb1->len;
817
818 eth_set_desc(sw, tx_ring, index, index_last, skb1->data,
819 skb1->len, config0, pmap);
820 }
821
822 tx_ring->buff_tab[index0] = skb;
823 eth_set_desc(sw, tx_ring, index0, index_last, skb->data, len0,
824 config0 | FIRST_SEGMENT, pmap);
825
826 wmb();
827
828 spin_lock(&tx_lock);
829 tx_ring->num_used += nr_desc + 1;
830 spin_unlock(&tx_lock);
831
832 dev->stats.tx_packets++;
833 dev->stats.tx_bytes += skb->len;
834
835 enable_tx_dma(sw);
836
837 return NETDEV_TX_OK;
838 }
839
840 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
841 {
842 struct port *port = netdev_priv(dev);
843
844 if (!netif_running(dev))
845 return -EINVAL;
846 return phy_mii_ioctl(port->phydev, req, cmd);
847 }
848
849 /* ethtool support */
850
851 static void cns3xxx_get_drvinfo(struct net_device *dev,
852 struct ethtool_drvinfo *info)
853 {
854 strcpy(info->driver, DRV_NAME);
855 strcpy(info->bus_info, "internal");
856 }
857
858 static int cns3xxx_nway_reset(struct net_device *dev)
859 {
860 struct port *port = netdev_priv(dev);
861 return phy_start_aneg(port->phydev);
862 }
863
864 static struct ethtool_ops cns3xxx_ethtool_ops = {
865 .get_drvinfo = cns3xxx_get_drvinfo,
866 .get_link_ksettings = phy_ethtool_get_link_ksettings,
867 .set_link_ksettings = phy_ethtool_set_link_ksettings,
868 .nway_reset = cns3xxx_nway_reset,
869 .get_link = ethtool_op_get_link,
870 };
871
872
873 static int init_rings(struct sw *sw)
874 {
875 int i;
876 struct _rx_ring *rx_ring = &sw->rx_ring;
877 struct _tx_ring *tx_ring = &sw->tx_ring;
878
879 __raw_writel(0, &sw->regs->fs_dma_ctrl0);
880 __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
881 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
882 __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
883 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
884
885 rx_ring->desc = dmam_alloc_coherent(sw->dev, RX_POOL_ALLOC_SIZE,
886 &rx_ring->phys_addr, GFP_KERNEL);
887 if (!rx_ring->desc)
888 return -ENOMEM;
889
890 /* Setup RX buffers */
891 memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
892
893 for (i = 0; i < RX_DESCS; i++) {
894 struct rx_desc *desc = &(rx_ring)->desc[i];
895 void *buf;
896
897 buf = netdev_alloc_frag(RX_SEGMENT_ALLOC_SIZE);
898 if (!buf)
899 return -ENOMEM;
900
901 desc->sdl = RX_SEGMENT_MRU;
902
903 if (i == (RX_DESCS - 1))
904 desc->eor = 1;
905
906 desc->fsd = 1;
907 desc->lsd = 1;
908
909 desc->sdp = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
910 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
911
912 if (dma_mapping_error(sw->dev, desc->sdp))
913 return -EIO;
914
915 rx_ring->buff_tab[i] = buf;
916 rx_ring->phys_tab[i] = desc->sdp;
917 desc->cown = 0;
918 }
919 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
920 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
921
922 tx_ring->desc = dmam_alloc_coherent(sw->dev, TX_POOL_ALLOC_SIZE,
923 &tx_ring->phys_addr, GFP_KERNEL);
924 if (!tx_ring->desc)
925 return -ENOMEM;
926
927 /* Setup TX buffers */
928 memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
929
930 for (i = 0; i < TX_DESCS; i++) {
931 struct tx_desc *desc = &(tx_ring)->desc[i];
932 tx_ring->buff_tab[i] = 0;
933
934 if (i == (TX_DESCS - 1))
935 desc->eor = 1;
936
937 desc->cown = 1;
938 }
939 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
940 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
941
942 return 0;
943 }
944
945 static void destroy_rings(struct sw *sw)
946 {
947 int i;
948
949 for (i = 0; i < RX_DESCS; i++) {
950 struct _rx_ring *rx_ring = &sw->rx_ring;
951 struct rx_desc *desc = &(rx_ring)->desc[i];
952 void *buf = sw->rx_ring.buff_tab[i];
953
954 if (!buf)
955 continue;
956
957 dma_unmap_single(sw->dev, desc->sdp, RX_SEGMENT_MRU, DMA_FROM_DEVICE);
958 skb_free_frag(buf);
959 }
960
961 for (i = 0; i < TX_DESCS; i++) {
962 struct _tx_ring *tx_ring = &sw->tx_ring;
963 struct tx_desc *desc = &(tx_ring)->desc[i];
964 struct sk_buff *skb = sw->tx_ring.buff_tab[i];
965
966 if (!skb)
967 continue;
968
969 dma_unmap_single(sw->dev, desc->sdp, skb->len, DMA_TO_DEVICE);
970 dev_kfree_skb(skb);
971 }
972 }
973
974 static int eth_open(struct net_device *dev)
975 {
976 struct port *port = netdev_priv(dev);
977 struct sw *sw = port->sw;
978 u32 temp;
979
980 port->speed = 0; /* force "link up" message */
981 phy_start(port->phydev);
982
983 netif_start_queue(dev);
984
985 if (!ports_open) {
986 request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
987 request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
988 napi_enable(&sw->napi);
989 netif_start_queue(napi_dev);
990
991 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
992 MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
993
994 temp = __raw_readl(&sw->regs->mac_cfg[2]);
995 temp &= ~(PORT_DISABLE);
996 __raw_writel(temp, &sw->regs->mac_cfg[2]);
997
998 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
999 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1000 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1001
1002 enable_rx_dma(sw);
1003 }
1004 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1005 temp &= ~(PORT_DISABLE);
1006 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1007
1008 ports_open++;
1009 netif_carrier_on(dev);
1010
1011 return 0;
1012 }
1013
1014 static int eth_close(struct net_device *dev)
1015 {
1016 struct port *port = netdev_priv(dev);
1017 struct sw *sw = port->sw;
1018 u32 temp;
1019
1020 ports_open--;
1021
1022 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1023 temp |= (PORT_DISABLE);
1024 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1025
1026 netif_stop_queue(dev);
1027
1028 phy_stop(port->phydev);
1029
1030 if (!ports_open) {
1031 disable_irq(sw->rx_irq);
1032 free_irq(sw->rx_irq, napi_dev);
1033 disable_irq(sw->stat_irq);
1034 free_irq(sw->stat_irq, napi_dev);
1035 napi_disable(&sw->napi);
1036 netif_stop_queue(napi_dev);
1037 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1038 temp |= (PORT_DISABLE);
1039 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1040
1041 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1042 &sw->regs->dma_auto_poll_cfg);
1043 }
1044
1045 netif_carrier_off(dev);
1046 return 0;
1047 }
1048
1049 static void eth_rx_mode(struct net_device *dev)
1050 {
1051 struct port *port = netdev_priv(dev);
1052 struct sw *sw = port->sw;
1053 u32 temp;
1054
1055 temp = __raw_readl(&sw->regs->mac_glob_cfg);
1056
1057 if (dev->flags & IFF_PROMISC) {
1058 if (port->id == 3)
1059 temp |= ((1 << 2) << PROMISC_OFFSET);
1060 else
1061 temp |= ((1 << port->id) << PROMISC_OFFSET);
1062 } else {
1063 if (port->id == 3)
1064 temp &= ~((1 << 2) << PROMISC_OFFSET);
1065 else
1066 temp &= ~((1 << port->id) << PROMISC_OFFSET);
1067 }
1068 __raw_writel(temp, &sw->regs->mac_glob_cfg);
1069 }
1070
1071 static int eth_set_mac(struct net_device *netdev, void *p)
1072 {
1073 struct port *port = netdev_priv(netdev);
1074 struct sw *sw = port->sw;
1075 struct sockaddr *addr = p;
1076 u32 cycles = 0;
1077
1078 if (!is_valid_ether_addr(addr->sa_data))
1079 return -EADDRNOTAVAIL;
1080
1081 /* Invalidate old ARL Entry */
1082 if (port->id == 3)
1083 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1084 else
1085 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1086 __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1087 (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1088 &sw->regs->arl_ctrl[1]);
1089
1090 __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1091 (1 << 1)),
1092 &sw->regs->arl_ctrl[2]);
1093 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1094
1095 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1096 && cycles < 5000) {
1097 udelay(1);
1098 cycles++;
1099 }
1100
1101 cycles = 0;
1102 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1103
1104 if (port->id == 3)
1105 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1106 else
1107 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1108 __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1109 (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1110 &sw->regs->arl_ctrl[1]);
1111
1112 __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1113 (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1114 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1115
1116 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1117 && cycles < 5000) {
1118 udelay(1);
1119 cycles++;
1120 }
1121 return 0;
1122 }
1123
1124 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1125 {
1126 if (new_mtu > MAX_MTU)
1127 return -EINVAL;
1128
1129 dev->mtu = new_mtu;
1130 return 0;
1131 }
1132
1133 static const struct net_device_ops cns3xxx_netdev_ops = {
1134 .ndo_open = eth_open,
1135 .ndo_stop = eth_close,
1136 .ndo_start_xmit = eth_xmit,
1137 .ndo_set_rx_mode = eth_rx_mode,
1138 .ndo_do_ioctl = eth_ioctl,
1139 .ndo_change_mtu = cns3xxx_change_mtu,
1140 .ndo_set_mac_address = eth_set_mac,
1141 .ndo_validate_addr = eth_validate_addr,
1142 };
1143
1144 static int eth_init_one(struct platform_device *pdev)
1145 {
1146 int i;
1147 struct port *port;
1148 struct sw *sw;
1149 struct net_device *dev;
1150 struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1151 char phy_id[MII_BUS_ID_SIZE + 3];
1152 int err;
1153 u32 temp;
1154 struct resource *res;
1155 void __iomem *regs;
1156
1157 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1158 regs = devm_ioremap_resource(&pdev->dev, res);
1159 if (IS_ERR(regs))
1160 return PTR_ERR(regs);
1161
1162 err = cns3xxx_mdio_register(regs);
1163 if (err)
1164 return err;
1165
1166 if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
1167 err = -ENOMEM;
1168 goto err_remove_mdio;
1169 }
1170
1171 strcpy(napi_dev->name, "cns3xxx_eth");
1172 napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1173
1174 SET_NETDEV_DEV(napi_dev, &pdev->dev);
1175 sw = netdev_priv(napi_dev);
1176 memset(sw, 0, sizeof(struct sw));
1177 sw->regs = regs;
1178 sw->dev = &pdev->dev;
1179
1180 sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
1181 sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
1182
1183 temp = __raw_readl(&sw->regs->phy_auto_addr);
1184 temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1185 __raw_writel(temp, &sw->regs->phy_auto_addr);
1186
1187 for (i = 0; i < 4; i++) {
1188 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1189 temp |= (PORT_DISABLE);
1190 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1191 }
1192
1193 temp = PORT_DISABLE;
1194 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1195
1196 temp = __raw_readl(&sw->regs->vlan_cfg);
1197 temp |= NIC_MODE | VLAN_UNAWARE;
1198 __raw_writel(temp, &sw->regs->vlan_cfg);
1199
1200 __raw_writel(UNKNOWN_VLAN_TO_CPU |
1201 CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1202
1203 if ((err = init_rings(sw)) != 0) {
1204 err = -ENOMEM;
1205 goto err_free;
1206 }
1207 platform_set_drvdata(pdev, napi_dev);
1208
1209 netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1210
1211 for (i = 0; i < 3; i++) {
1212 if (!(plat->ports & (1 << i))) {
1213 continue;
1214 }
1215
1216 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1217 goto free_ports;
1218 }
1219
1220 port = netdev_priv(dev);
1221 port->netdev = dev;
1222 if (i == 2)
1223 port->id = 3;
1224 else
1225 port->id = i;
1226 port->sw = sw;
1227
1228 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1229 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1230 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1231
1232 SET_NETDEV_DEV(dev, &pdev->dev);
1233 dev->netdev_ops = &cns3xxx_netdev_ops;
1234 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1235 dev->tx_queue_len = 1000;
1236 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1237
1238 switch_port_tab[port->id] = port;
1239 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1240
1241 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1242 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
1243 PHY_INTERFACE_MODE_RGMII);
1244 if ((err = IS_ERR(port->phydev))) {
1245 switch_port_tab[port->id] = 0;
1246 free_netdev(dev);
1247 goto free_ports;
1248 }
1249
1250 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1251
1252 if ((err = register_netdev(dev))) {
1253 phy_disconnect(port->phydev);
1254 switch_port_tab[port->id] = 0;
1255 free_netdev(dev);
1256 goto free_ports;
1257 }
1258
1259 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1260 netif_carrier_off(dev);
1261 dev = 0;
1262 }
1263
1264 return 0;
1265
1266 free_ports:
1267 err = -ENOMEM;
1268 for (--i; i >= 0; i--) {
1269 if (switch_port_tab[i]) {
1270 port = switch_port_tab[i];
1271 dev = port->netdev;
1272 unregister_netdev(dev);
1273 phy_disconnect(port->phydev);
1274 switch_port_tab[i] = 0;
1275 free_netdev(dev);
1276 }
1277 }
1278 err_free:
1279 free_netdev(napi_dev);
1280 err_remove_mdio:
1281 cns3xxx_mdio_remove();
1282 return err;
1283 }
1284
1285 static int eth_remove_one(struct platform_device *pdev)
1286 {
1287 struct net_device *dev = platform_get_drvdata(pdev);
1288 struct sw *sw = netdev_priv(dev);
1289 int i;
1290
1291 destroy_rings(sw);
1292 for (i = 3; i >= 0; i--) {
1293 if (switch_port_tab[i]) {
1294 struct port *port = switch_port_tab[i];
1295 struct net_device *dev = port->netdev;
1296 unregister_netdev(dev);
1297 phy_disconnect(port->phydev);
1298 switch_port_tab[i] = 0;
1299 free_netdev(dev);
1300 }
1301 }
1302
1303 free_netdev(napi_dev);
1304 cns3xxx_mdio_remove();
1305
1306 return 0;
1307 }
1308
1309 static struct platform_driver cns3xxx_eth_driver = {
1310 .driver.name = DRV_NAME,
1311 .probe = eth_init_one,
1312 .remove = eth_remove_one,
1313 };
1314
1315 static int __init eth_init_module(void)
1316 {
1317 return platform_driver_register(&cns3xxx_eth_driver);
1318 }
1319
1320 static void __exit eth_cleanup_module(void)
1321 {
1322 platform_driver_unregister(&cns3xxx_eth_driver);
1323 }
1324
1325 module_init(eth_init_module);
1326 module_exit(eth_cleanup_module);
1327
1328 MODULE_AUTHOR("Chris Lang");
1329 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1330 MODULE_LICENSE("GPL v2");
1331 MODULE_ALIAS("platform:cns3xxx_eth");
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