1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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19 * below, then you are not authorized to use the Software.
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22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
34 #if !defined(__DWC_CIL_H__)
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39 #include <asm/param.h>
40 //#include <asm/arch/regs-irq.h>
45 #include "linux/timer.h"
50 * This file contains the interface to the Core Interface Layer.
54 /** Macros defined for DWC OTG HW Release verison */
55 #define OTG_CORE_REV_2_00 0x4F542000
56 #define OTG_CORE_REV_2_60a 0x4F54260A
57 #define OTG_CORE_REV_2_71a 0x4F54271A
58 #define OTG_CORE_REV_2_72a 0x4F54272A
62 typedef struct iso_pkt_info
69 * The <code>dwc_ep</code> structure represents the state of a single
70 * endpoint when acting in device mode. It contains the data items
71 * needed for an endpoint to be activated and transfer packets.
75 /** EP number used for register address lookup */
77 /** EP direction 0 = OUT */
82 /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
83 If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
84 unsigned tx_fifo_num
: 4;
85 /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
87 #define DWC_OTG_EP_TYPE_CONTROL 0
88 #define DWC_OTG_EP_TYPE_ISOC 1
89 #define DWC_OTG_EP_TYPE_BULK 2
90 #define DWC_OTG_EP_TYPE_INTR 3
92 /** DATA start PID for INTR and BULK EP */
93 unsigned data_pid_start
: 1;
94 /** Frame (even/odd) for ISOC EP */
95 unsigned even_odd_frame
: 1;
96 /** Max Packet bytes */
97 unsigned maxpacket
: 11;
99 /** Max Transfer size */
100 unsigned maxxfer
: 16;
102 /** @name Transfer state */
106 * Pointer to the beginning of the transfer buffer -- do not modify
112 uint32_t dma_desc_addr
;
113 dwc_otg_dma_desc_t
* desc_addr
;
116 uint8_t *start_xfer_buff
;
117 /** pointer to the transfer buffer */
119 /** Number of bytes to transfer */
120 unsigned xfer_len
: 19;
121 /** Number of bytes transferred. */
122 unsigned xfer_count
: 19;
124 unsigned sent_zlp
: 1;
125 /** Total len for control transfer */
126 unsigned total_len
: 19;
128 /** stall clear flag */
129 unsigned stall_clear_flag
: 1;
131 /** Allocated DMA Desc count */
134 uint32_t aligned_dma_addr
;
135 uint32_t aligned_buf_size
;
136 uint8_t *aligned_buf
;
141 * Variables specific for ISOC EPs
144 /** DMA addresses of ISOC buffers */
148 uint32_t iso_dma_desc_addr
;
149 dwc_otg_dma_desc_t
* iso_desc_addr
;
151 /** pointer to the transfer buffers */
155 /** number of ISOC Buffer is processing */
156 uint32_t proc_buf_num
;
157 /** Interval of ISOC Buffer processing */
158 uint32_t buf_proc_intrvl
;
159 /** Data size for regular frame */
160 uint32_t data_per_frame
;
162 /* todo - pattern data support is to be implemented in the future */
163 /** Data size for pattern frame */
164 uint32_t data_pattern_frame
;
165 /** Frame number of pattern data */
170 /** ISO Packet number per frame */
171 uint32_t pkt_per_frm
;
172 /** Next frame num for which will be setup DMA Desc */
174 /** Number of packets per buffer processing */
176 /** Info for all isoc packets */
177 iso_pkt_info_t
*pkt_info
;
178 /** current pkt number */
180 /** current pkt number */
181 uint8_t *cur_pkt_addr
;
182 /** current pkt number */
183 uint32_t cur_pkt_dma_addr
;
189 * Reasons for halting a host channel.
191 typedef enum dwc_otg_halt_status
193 DWC_OTG_HC_XFER_NO_HALT_STATUS
,
194 DWC_OTG_HC_XFER_COMPLETE
,
195 DWC_OTG_HC_XFER_URB_COMPLETE
,
198 DWC_OTG_HC_XFER_NYET
,
199 DWC_OTG_HC_XFER_STALL
,
200 DWC_OTG_HC_XFER_XACT_ERR
,
201 DWC_OTG_HC_XFER_FRAME_OVERRUN
,
202 DWC_OTG_HC_XFER_BABBLE_ERR
,
203 DWC_OTG_HC_XFER_DATA_TOGGLE_ERR
,
204 DWC_OTG_HC_XFER_AHB_ERR
,
205 DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE
,
206 DWC_OTG_HC_XFER_URB_DEQUEUE
207 } dwc_otg_halt_status_e
;
210 * Host channel descriptor. This structure represents the state of a single
211 * host channel when acting in host mode. It contains the data items needed to
212 * transfer packets to an endpoint via a host channel.
214 typedef struct dwc_hc
216 /** Host channel number used for register address lookup */
219 /** Device to access */
220 unsigned dev_addr
: 7;
225 /** EP direction. 0: OUT, 1: IN */
226 unsigned ep_is_in
: 1;
230 * One of the following values:
231 * - DWC_OTG_EP_SPEED_LOW
232 * - DWC_OTG_EP_SPEED_FULL
233 * - DWC_OTG_EP_SPEED_HIGH
236 #define DWC_OTG_EP_SPEED_LOW 0
237 #define DWC_OTG_EP_SPEED_FULL 1
238 #define DWC_OTG_EP_SPEED_HIGH 2
242 * One of the following values:
243 * - DWC_OTG_EP_TYPE_CONTROL: 0
244 * - DWC_OTG_EP_TYPE_ISOC: 1
245 * - DWC_OTG_EP_TYPE_BULK: 2
246 * - DWC_OTG_EP_TYPE_INTR: 3
248 unsigned ep_type
: 2;
250 /** Max packet size in bytes */
251 unsigned max_packet
: 11;
254 * PID for initial transaction.
258 * 3: MDATA (non-Control EP),
261 unsigned data_pid_start
: 2;
262 #define DWC_OTG_HC_PID_DATA0 0
263 #define DWC_OTG_HC_PID_DATA2 1
264 #define DWC_OTG_HC_PID_DATA1 2
265 #define DWC_OTG_HC_PID_MDATA 3
266 #define DWC_OTG_HC_PID_SETUP 3
268 /** Number of periodic transactions per (micro)frame */
269 unsigned multi_count
: 2;
271 /** @name Transfer State */
274 /** Pointer to the current transfer buffer position. */
276 /** Total number of bytes to transfer. */
278 /** Number of bytes transferred so far. */
280 /** Packet count at start of transfer.*/
281 uint16_t start_pkt_count
;
284 * Flag to indicate whether the transfer has been started. Set to 1 if
285 * it has been started, 0 otherwise.
287 uint8_t xfer_started
;
290 * Set to 1 to indicate that a PING request should be issued on this
291 * channel. If 0, process normally.
296 * Set to 1 to indicate that the error count for this transaction is
297 * non-zero. Set to 0 if the error count is 0.
302 * Set to 1 to indicate that this channel should be halted the next
303 * time a request is queued for the channel. This is necessary in
304 * slave mode if no request queue space is available when an attempt
305 * is made to halt the channel.
307 uint8_t halt_on_queue
;
310 * Set to 1 if the host channel has been halted, but the core is not
311 * finished flushing queued requests. Otherwise 0.
313 uint8_t halt_pending
;
316 * Reason for halting the host channel.
318 dwc_otg_halt_status_e halt_status
;
321 * Split settings for the host channel
323 uint8_t do_split
; /**< Enable split for the channel */
324 uint8_t complete_split
; /**< Enable complete split */
325 uint8_t hub_addr
; /**< Address of high speed hub */
327 uint8_t port_addr
; /**< Port of the low/full speed device */
328 /** Split transaction position
329 * One of the following values:
330 * - DWC_HCSPLIT_XACTPOS_MID
331 * - DWC_HCSPLIT_XACTPOS_BEGIN
332 * - DWC_HCSPLIT_XACTPOS_END
333 * - DWC_HCSPLIT_XACTPOS_ALL */
336 /** Set when the host channel does a short read. */
340 * Number of requests issued for this channel since it was assigned to
341 * the current transfer (not counting PINGs).
346 * Queue Head for the transfer being processed by this channel.
348 struct dwc_otg_qh
*qh
;
352 /** Entry in list of host channels. */
353 struct list_head hc_list_entry
;
357 * The following parameters may be specified when starting the module. These
358 * parameters define how the DWC_otg controller should be configured.
359 * Parameter values are passed to the CIL initialization function
362 typedef struct dwc_otg_core_params
365 #define dwc_param_opt_default 1
368 * Specifies the OTG capabilities. The driver will automatically
369 * detect the value for this parameter if none is specified.
370 * 0 - HNP and SRP capable (default)
371 * 1 - SRP Only capable
372 * 2 - No HNP/SRP capable
375 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
376 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
377 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
378 //#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
379 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
382 * Specifies whether to use slave or DMA mode for accessing the data
383 * FIFOs. The driver will automatically detect the value for this
384 * parameter if none is specified.
386 * 1 - DMA (default, if available)
389 #define dwc_param_dma_enable_default 1
392 * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
393 * FIFOs in device mode. The driver will automatically detect the value for this
394 * parameter if none is specified.
396 * 1 - DMA Descriptor(default, if available)
398 int32_t dma_desc_enable
;
399 #define dwc_param_dma_desc_enable_default 0
400 /** The DMA Burst size (applicable only for External DMA
401 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
403 int32_t dma_burst_size
; /* Translate this to GAHBCFG values */
404 //#define dwc_param_dma_burst_size_default 32
405 #define dwc_param_dma_burst_size_default 1
408 * Specifies the maximum speed of operation in host and device mode.
409 * The actual speed depends on the speed of the attached device and
410 * the value of phy_type. The actual speed depends on the speed of the
412 * 0 - High Speed (default)
416 #define dwc_param_speed_default 0
417 #define DWC_SPEED_PARAM_HIGH 0
418 #define DWC_SPEED_PARAM_FULL 1
420 /** Specifies whether low power mode is supported when attached
421 * to a Full Speed or Low Speed device in host mode.
422 * 0 - Don't support low power mode (default)
423 * 1 - Support low power mode
425 int32_t host_support_fs_ls_low_power
;
426 #define dwc_param_host_support_fs_ls_low_power_default 0
428 /** Specifies the PHY clock rate in low power mode when connected to a
429 * Low Speed device in host mode. This parameter is applicable only if
430 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
431 * then defaults to 6 MHZ otherwise 48 MHZ.
436 int32_t host_ls_low_power_phy_clk
;
437 #define dwc_param_host_ls_low_power_phy_clk_default 0
438 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
439 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
442 * 0 - Use cC FIFO size parameters
443 * 1 - Allow dynamic FIFO sizing (default)
445 int32_t enable_dynamic_fifo
;
446 #define dwc_param_enable_dynamic_fifo_default 1
448 /** Total number of 4-byte words in the data FIFO memory. This
449 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
451 * 32 to 32768 (default 8192)
452 * Note: The total FIFO memory depth in the FPGA configuration is 8192.
454 int32_t data_fifo_size
;
455 #define dwc_param_data_fifo_size_default 8192
457 /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
458 * FIFO sizing is enabled.
459 * 16 to 32768 (default 1064)
461 int32_t dev_rx_fifo_size
;
462 //#define dwc_param_dev_rx_fifo_size_default 1064
463 #define dwc_param_dev_rx_fifo_size_default 0x100
466 * Specifies whether dedicated transmit FIFOs are
467 * enabled for non periodic IN endpoints in device mode
471 int32_t en_multiple_tx_fifo
;
472 #define dwc_param_en_multiple_tx_fifo_default 1
474 /** Number of 4-byte words in each of the Tx FIFOs in device
475 * mode when dynamic FIFO sizing is enabled.
476 * 4 to 768 (default 256)
478 uint32_t dev_tx_fifo_size
[MAX_TX_FIFOS
];
479 //#define dwc_param_dev_tx_fifo_size_default 256
480 #define dwc_param_dev_tx_fifo_size_default 0x80
482 /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
483 * when dynamic FIFO sizing is enabled.
484 * 16 to 32768 (default 1024)
486 int32_t dev_nperio_tx_fifo_size
;
487 //#define dwc_param_dev_nperio_tx_fifo_size_default 1024
488 #define dwc_param_dev_nperio_tx_fifo_size_default 0x80
490 /** Number of 4-byte words in each of the periodic Tx FIFOs in device
491 * mode when dynamic FIFO sizing is enabled.
492 * 4 to 768 (default 256)
494 uint32_t dev_perio_tx_fifo_size
[MAX_PERIO_FIFOS
];
495 //#define dwc_param_dev_perio_tx_fifo_size_default 256
496 #define dwc_param_dev_perio_tx_fifo_size_default 0x80
498 /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
499 * FIFO sizing is enabled.
500 * 16 to 32768 (default 1024)
502 int32_t host_rx_fifo_size
;
503 //#define dwc_param_host_rx_fifo_size_default 1024
504 #define dwc_param_host_rx_fifo_size_default 0x292
506 /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
507 * when Dynamic FIFO sizing is enabled in the core.
508 * 16 to 32768 (default 1024)
510 int32_t host_nperio_tx_fifo_size
;
511 //#define dwc_param_host_nperio_tx_fifo_size_default 1024
512 //#define dwc_param_host_nperio_tx_fifo_size_default 0x292
513 #define dwc_param_host_nperio_tx_fifo_size_default 0x80
515 /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
516 * FIFO sizing is enabled.
517 * 16 to 32768 (default 1024)
519 int32_t host_perio_tx_fifo_size
;
520 //#define dwc_param_host_perio_tx_fifo_size_default 1024
521 #define dwc_param_host_perio_tx_fifo_size_default 0x292
523 /** The maximum transfer size supported in bytes.
524 * 2047 to 65,535 (default 65,535)
526 int32_t max_transfer_size
;
527 #define dwc_param_max_transfer_size_default 65535
529 /** The maximum number of packets in a transfer.
530 * 15 to 511 (default 511)
532 int32_t max_packet_count
;
533 #define dwc_param_max_packet_count_default 511
535 /** The number of host channel registers to use.
536 * 1 to 16 (default 12)
537 * Note: The FPGA configuration supports a maximum of 12 host channels.
539 int32_t host_channels
;
540 //#define dwc_param_host_channels_default 12
541 #define dwc_param_host_channels_default 16
543 /** The number of endpoints in addition to EP0 available for device
545 * 1 to 15 (default 6 IN and OUT)
546 * Note: The FPGA configuration supports a maximum of 6 IN and OUT
547 * endpoints in addition to EP0.
549 int32_t dev_endpoints
;
550 //#define dwc_param_dev_endpoints_default 6
551 #define dwc_param_dev_endpoints_default 8
554 * Specifies the type of PHY interface to use. By default, the driver
555 * will automatically detect the phy_type.
558 * 1 - UTMI+ (default)
562 #define DWC_PHY_TYPE_PARAM_FS 0
563 #define DWC_PHY_TYPE_PARAM_UTMI 1
564 #define DWC_PHY_TYPE_PARAM_ULPI 2
565 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
568 * Specifies the UTMI+ Data Width. This parameter is
569 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
570 * PHY_TYPE, this parameter indicates the data width between
571 * the MAC and the ULPI Wrapper.) Also, this parameter is
572 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
573 * to "8 and 16 bits", meaning that the core has been
574 * configured to work at either data path width.
576 * 8 or 16 bits (default 16)
578 int32_t phy_utmi_width
;
579 #define dwc_param_phy_utmi_width_default 16
582 * Specifies whether the ULPI operates at double or single
583 * data rate. This parameter is only applicable if PHY_TYPE is
586 * 0 - single data rate ULPI interface with 8 bit wide data
588 * 1 - double data rate ULPI interface with 4 bit wide data
591 int32_t phy_ulpi_ddr
;
592 #define dwc_param_phy_ulpi_ddr_default 0
595 * Specifies whether to use the internal or external supply to
596 * drive the vbus with a ULPI phy.
598 int32_t phy_ulpi_ext_vbus
;
599 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
600 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
601 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
604 * Specifies whether to use the I2Cinterface for full speed PHY. This
605 * parameter is only applicable if PHY_TYPE is FS.
610 #define dwc_param_i2c_enable_default 0
613 #define dwc_param_ulpi_fs_ls_default 0
616 #define dwc_param_ts_dline_default 0
618 /** Thresholding enable flag-
619 * bit 0 - enable non-ISO Tx thresholding
620 * bit 1 - enable ISO Tx thresholding
621 * bit 2 - enable Rx thresholding
624 #define dwc_param_thr_ctl_default 0
626 /** Thresholding length for Tx
627 * FIFOs in 32 bit DWORDs
629 uint32_t tx_thr_length
;
630 #define dwc_param_tx_thr_length_default 64
632 /** Thresholding length for Rx
633 * FIFOs in 32 bit DWORDs
635 uint32_t rx_thr_length
;
636 #define dwc_param_rx_thr_length_default 64
638 /** Per Transfer Interrupt
644 #define dwc_param_pti_enable_default 0
646 /** Molti Processor Interrupt
652 #define dwc_param_mpi_enable_default 0
654 } dwc_otg_core_params_t
;
657 struct dwc_otg_core_if
;
658 typedef struct hc_xfer_info
660 struct dwc_otg_core_if
*core_if
;
666 * The <code>dwc_otg_core_if</code> structure contains information needed to manage
667 * the DWC_otg controller acting in either host or device mode. It
668 * represents the programming view of the controller as a whole.
670 typedef struct dwc_otg_core_if
672 /** Parameters that define how the core should be configured.*/
673 dwc_otg_core_params_t
*core_params
;
675 /** Core Global registers starting at offset 000h. */
676 dwc_otg_core_global_regs_t
*core_global_regs
;
678 /** Device-specific information */
679 dwc_otg_dev_if_t
*dev_if
;
680 /** Host-specific information */
681 dwc_otg_host_if_t
*host_if
;
683 /** Value from SNPSID register */
687 * Set to 1 if the core PHY interface bits in USBCFG have been
690 uint8_t phy_init_done
;
693 * SRP Success flag, set by srp success interrupt in FS I2C mode
696 uint8_t srp_timer_started
;
698 /* Common configuration information */
699 /** Power and Clock Gating Control Register */
700 volatile uint32_t *pcgcctl
;
701 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
703 /** Push/pop addresses for endpoints or host channels.*/
704 uint32_t *data_fifo
[MAX_EPS_CHANNELS
];
705 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
706 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
708 /** Total RAM for FIFOs (Bytes) */
709 uint16_t total_fifo_size
;
710 /** Size of Rx FIFO (Bytes) */
711 uint16_t rx_fifo_size
;
712 /** Size of Non-periodic Tx FIFO (Bytes) */
713 uint16_t nperio_tx_fifo_size
;
716 /** 1 if DMA is enabled, 0 otherwise. */
719 /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
720 uint8_t dma_desc_enable
;
722 /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
723 uint8_t pti_enh_enable
;
725 /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
726 uint8_t multiproc_int_enable
;
728 /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
729 uint8_t en_multiple_tx_fifo
;
731 /** Set to 1 if multiple packets of a high-bandwidth transfer is in
732 * process of being queued */
733 uint8_t queuing_high_bandwidth
;
735 /** Hardware Configuration -- stored here for convenience.*/
736 hwcfg1_data_t hwcfg1
;
737 hwcfg2_data_t hwcfg2
;
738 hwcfg3_data_t hwcfg3
;
739 hwcfg4_data_t hwcfg4
;
741 /** Host and Device Configuration -- stored here for convenience.*/
745 /** The operational State, during transations
746 * (a_host>>a_peripherial and b_device=>b_host) this may not
747 * match the core but allows the software to determine
753 * Set to 1 if the HCD needs to be restarted on a session request
754 * interrupt. This is required if no connector ID status change has
755 * occurred since the HCD was last disconnected.
757 uint8_t restart_hcd_on_session_req
;
760 /** A-Device is a_host */
762 /** A-Device is a_suspend */
763 #define A_SUSPEND (2)
764 /** A-Device is a_peripherial */
765 #define A_PERIPHERAL (3)
766 /** B-Device is operating as a Peripheral. */
767 #define B_PERIPHERAL (4)
768 /** B-Device is operating as a Host. */
772 struct dwc_otg_cil_callbacks
*hcd_cb
;
774 struct dwc_otg_cil_callbacks
*pcd_cb
;
776 /** Device mode Periodic Tx FIFO Mask */
778 /** Device mode Periodic Tx FIFO Mask */
781 /** Workqueue object used for handling several interrupts */
782 struct workqueue_struct
*wq_otg
;
784 /** Work object used for handling "Connector ID Status Change" Interrupt */
785 struct work_struct w_conn_id
;
787 /** Work object used for handling "Wakeup Detected" Interrupt */
788 struct delayed_work w_wkp
;
791 uint32_t start_hcchar_val
[MAX_EPS_CHANNELS
];
793 hc_xfer_info_t hc_xfer_info
[MAX_EPS_CHANNELS
];
794 struct timer_list hc_xfer_timer
[MAX_EPS_CHANNELS
];
796 uint32_t hfnum_7_samples
;
797 uint64_t hfnum_7_frrem_accum
;
798 uint32_t hfnum_0_samples
;
799 uint64_t hfnum_0_frrem_accum
;
800 uint32_t hfnum_other_samples
;
801 uint64_t hfnum_other_frrem_accum
;
807 /*We must clear S3C24XX_EINTPEND external interrupt register
808 * because after clearing in this register trigerred IRQ from
809 * H/W core in kernel interrupt can be occured again before OTG
810 * handlers clear all IRQ sources of Core registers because of
811 * timing latencies and Low Level IRQ Type.
814 #ifdef CONFIG_MACH_IPMATE
815 #define S3C2410X_CLEAR_EINTPEND() \
817 if (!dwc_otg_read_core_intr(core_if)) { \
818 __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
822 #define S3C2410X_CLEAR_EINTPEND() do { } while (0)
826 * The following functions are functions for works
827 * using during handling some interrupts
829 extern void w_conn_id_status_change(struct work_struct
*p
);
830 extern void w_wakeup_detected(struct work_struct
*p
);
834 * The following functions support initialization of the CIL driver component
835 * and the DWC_otg controller.
837 extern dwc_otg_core_if_t
*dwc_otg_cil_init(const uint32_t *_reg_base_addr
,
838 dwc_otg_core_params_t
*_core_params
);
839 extern void dwc_otg_cil_remove(dwc_otg_core_if_t
*_core_if
);
840 extern void dwc_otg_core_init(dwc_otg_core_if_t
*_core_if
);
841 extern void dwc_otg_core_host_init(dwc_otg_core_if_t
*_core_if
);
842 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t
*_core_if
);
843 extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t
*_core_if
);
844 extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t
*_core_if
);
846 /** @name Device CIL Functions
847 * The following functions support managing the DWC_otg controller in device
851 extern void dwc_otg_wakeup(dwc_otg_core_if_t
*_core_if
);
852 extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t
*_core_if
, uint32_t *_dest
);
853 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t
*_core_if
);
854 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
855 extern void dwc_otg_ep_activate(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
856 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
857 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
858 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
859 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
860 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
861 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
, int _dma
);
862 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
863 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
864 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t
*_core_if
);
865 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t
*_core_if
);
866 extern void dwc_otg_dump_spram(dwc_otg_core_if_t
*_core_if
);
868 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
);
869 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
);
873 /** @name Host CIL Functions
874 * The following functions support managing the DWC_otg controller in host
878 extern void dwc_otg_hc_init(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
879 extern void dwc_otg_hc_halt(dwc_otg_core_if_t
*_core_if
,
881 dwc_otg_halt_status_e _halt_status
);
882 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
883 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
884 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
885 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
886 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
887 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t
*_core_if
);
888 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t
*_core_if
);
891 * This function Reads HPRT0 in preparation to modify. It keeps the
892 * WC bits 0 so that if they are read as 1, they won't clear when you
895 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t
*_core_if
)
898 hprt0
.d32
= dwc_read_reg32(_core_if
->host_if
->hprt0
);
900 hprt0
.b
.prtconndet
= 0;
901 hprt0
.b
.prtenchng
= 0;
902 hprt0
.b
.prtovrcurrchng
= 0;
906 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t
*_core_if
);
909 /** @name Common CIL Functions
910 * The following functions support managing the DWC_otg controller in either
911 * device or host mode.
915 extern void dwc_otg_read_packet(dwc_otg_core_if_t
*core_if
,
919 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t
*_core_if
);
921 extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t
*_core_if
,
923 extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t
*_core_if
);
924 extern void dwc_otg_core_reset( dwc_otg_core_if_t
*_core_if
);
926 extern dwc_otg_dma_desc_t
* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr
, uint32_t count
);
927 extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t
* desc_addr
, uint32_t dma_desc_addr
, uint32_t count
);
930 * This function returns the Core Interrupt register.
932 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t
*_core_if
)
934 return (dwc_read_reg32(&_core_if
->core_global_regs
->gintsts
) &
935 dwc_read_reg32(&_core_if
->core_global_regs
->gintmsk
));
939 * This function returns the OTG Interrupt register.
941 static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t
*_core_if
)
943 return (dwc_read_reg32 (&_core_if
->core_global_regs
->gotgint
));
947 * This function reads the Device All Endpoints Interrupt register and
948 * returns the IN endpoint interrupt bits.
950 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t
*core_if
)
954 if(core_if
->multiproc_int_enable
) {
955 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachint
) &
956 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachintmsk
);
958 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daint
) &
959 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daintmsk
);
966 * This function reads the Device All Endpoints Interrupt register and
967 * returns the OUT endpoint interrupt bits.
969 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t
*core_if
)
973 if(core_if
->multiproc_int_enable
) {
974 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachint
) &
975 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachintmsk
);
977 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daint
) &
978 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daintmsk
);
981 return ((v
& 0xffff0000) >> 16);
985 * This function returns the Device IN EP Interrupt register
987 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t
*core_if
,
990 dwc_otg_dev_if_t
*dev_if
= core_if
->dev_if
;
991 uint32_t v
, msk
, emp
;
993 if(core_if
->multiproc_int_enable
) {
994 msk
= dwc_read_reg32(&dev_if
->dev_global_regs
->diepeachintmsk
[ep
->num
]);
995 emp
= dwc_read_reg32(&dev_if
->dev_global_regs
->dtknqr4_fifoemptymsk
);
996 msk
|= ((emp
>> ep
->num
) & 0x1) << 7;
997 v
= dwc_read_reg32(&dev_if
->in_ep_regs
[ep
->num
]->diepint
) & msk
;
999 msk
= dwc_read_reg32(&dev_if
->dev_global_regs
->diepmsk
);
1000 emp
= dwc_read_reg32(&dev_if
->dev_global_regs
->dtknqr4_fifoemptymsk
);
1001 msk
|= ((emp
>> ep
->num
) & 0x1) << 7;
1002 v
= dwc_read_reg32(&dev_if
->in_ep_regs
[ep
->num
]->diepint
) & msk
;
1009 * This function returns the Device OUT EP Interrupt register
1011 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t
*_core_if
,
1014 dwc_otg_dev_if_t
*dev_if
= _core_if
->dev_if
;
1016 doepmsk_data_t msk
= { .d32
= 0 };
1018 if(_core_if
->multiproc_int_enable
) {
1019 msk
.d32
= dwc_read_reg32(&dev_if
->dev_global_regs
->doepeachintmsk
[_ep
->num
]);
1020 if(_core_if
->pti_enh_enable
) {
1021 msk
.b
.pktdrpsts
= 1;
1023 v
= dwc_read_reg32( &dev_if
->out_ep_regs
[_ep
->num
]->doepint
) & msk
.d32
;
1025 msk
.d32
= dwc_read_reg32(&dev_if
->dev_global_regs
->doepmsk
);
1026 if(_core_if
->pti_enh_enable
) {
1027 msk
.b
.pktdrpsts
= 1;
1029 v
= dwc_read_reg32( &dev_if
->out_ep_regs
[_ep
->num
]->doepint
) & msk
.d32
;
1035 * This function returns the Host All Channel Interrupt register
1037 static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t
*_core_if
)
1039 return (dwc_read_reg32 (&_core_if
->host_if
->host_global_regs
->haint
));
1042 static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
)
1044 return (dwc_read_reg32 (&_core_if
->host_if
->hc_regs
[_hc
->hc_num
]->hcint
));
1049 * This function returns the mode of the operation, host or device.
1051 * @return 0 - Device Mode, 1 - Host Mode
1053 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t
*_core_if
)
1055 return (dwc_read_reg32( &_core_if
->core_global_regs
->gintsts
) & 0x1);
1058 static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t
*_core_if
)
1060 return (dwc_otg_mode(_core_if
) != DWC_HOST_MODE
);
1062 static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t
*_core_if
)
1064 return (dwc_otg_mode(_core_if
) == DWC_HOST_MODE
);
1067 extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t
*_core_if
);
1073 * DWC_otg CIL callback structure. This structure allows the HCD and
1074 * PCD to register functions used for starting and stopping the PCD
1075 * and HCD for role change on for a DRD.
1077 typedef struct dwc_otg_cil_callbacks
1079 /** Start function for role change */
1080 int (*start
) (void *_p
);
1081 /** Stop Function for role change */
1082 int (*stop
) (void *_p
);
1083 /** Disconnect Function for role change */
1084 int (*disconnect
) (void *_p
);
1085 /** Resume/Remote wakeup Function */
1086 int (*resume_wakeup
) (void *_p
);
1087 /** Suspend function */
1088 int (*suspend
) (void *_p
);
1089 /** Session Start (SRP) */
1090 int (*session_start
) (void *_p
);
1091 /** Pointer passed to start() and stop() */
1093 } dwc_otg_cil_callbacks_t
;
1095 extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t
*_core_if
,
1096 dwc_otg_cil_callbacks_t
*_cb
,
1098 extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t
*_core_if
,
1099 dwc_otg_cil_callbacks_t
*_cb
,