1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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19 * below, then you are not authorized to use the Software.
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22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
34 #if !defined(__DWC_CIL_H__)
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39 #include <asm/param.h>
40 //#include <asm/arch/regs-irq.h>
45 #include "linux/timer.h"
52 * This file contains the interface to the Core Interface Layer.
56 /** Macros defined for DWC OTG HW Release verison */
57 #define OTG_CORE_REV_2_00 0x4F542000
58 #define OTG_CORE_REV_2_60a 0x4F54260A
59 #define OTG_CORE_REV_2_71a 0x4F54271A
60 #define OTG_CORE_REV_2_72a 0x4F54272A
64 typedef struct iso_pkt_info
71 * The <code>dwc_ep</code> structure represents the state of a single
72 * endpoint when acting in device mode. It contains the data items
73 * needed for an endpoint to be activated and transfer packets.
77 /** EP number used for register address lookup */
79 /** EP direction 0 = OUT */
84 /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
85 If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
86 unsigned tx_fifo_num
: 4;
87 /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
89 #define DWC_OTG_EP_TYPE_CONTROL 0
90 #define DWC_OTG_EP_TYPE_ISOC 1
91 #define DWC_OTG_EP_TYPE_BULK 2
92 #define DWC_OTG_EP_TYPE_INTR 3
94 /** DATA start PID for INTR and BULK EP */
95 unsigned data_pid_start
: 1;
96 /** Frame (even/odd) for ISOC EP */
97 unsigned even_odd_frame
: 1;
98 /** Max Packet bytes */
99 unsigned maxpacket
: 11;
101 /** Max Transfer size */
102 unsigned maxxfer
: 16;
104 /** @name Transfer state */
108 * Pointer to the beginning of the transfer buffer -- do not modify
114 uint32_t dma_desc_addr
;
115 dwc_otg_dma_desc_t
* desc_addr
;
118 uint8_t *start_xfer_buff
;
119 /** pointer to the transfer buffer */
121 /** Number of bytes to transfer */
122 unsigned xfer_len
: 19;
123 /** Number of bytes transferred. */
124 unsigned xfer_count
: 19;
126 unsigned sent_zlp
: 1;
127 /** Total len for control transfer */
128 unsigned total_len
: 19;
130 /** stall clear flag */
131 unsigned stall_clear_flag
: 1;
133 /** Allocated DMA Desc count */
136 uint32_t aligned_dma_addr
;
137 uint32_t aligned_buf_size
;
138 uint8_t *aligned_buf
;
143 * Variables specific for ISOC EPs
146 /** DMA addresses of ISOC buffers */
150 uint32_t iso_dma_desc_addr
;
151 dwc_otg_dma_desc_t
* iso_desc_addr
;
153 /** pointer to the transfer buffers */
157 /** number of ISOC Buffer is processing */
158 uint32_t proc_buf_num
;
159 /** Interval of ISOC Buffer processing */
160 uint32_t buf_proc_intrvl
;
161 /** Data size for regular frame */
162 uint32_t data_per_frame
;
164 /* todo - pattern data support is to be implemented in the future */
165 /** Data size for pattern frame */
166 uint32_t data_pattern_frame
;
167 /** Frame number of pattern data */
172 /** ISO Packet number per frame */
173 uint32_t pkt_per_frm
;
174 /** Next frame num for which will be setup DMA Desc */
176 /** Number of packets per buffer processing */
178 /** Info for all isoc packets */
179 iso_pkt_info_t
*pkt_info
;
180 /** current pkt number */
182 /** current pkt number */
183 uint8_t *cur_pkt_addr
;
184 /** current pkt number */
185 uint32_t cur_pkt_dma_addr
;
191 * Reasons for halting a host channel.
193 typedef enum dwc_otg_halt_status
195 DWC_OTG_HC_XFER_NO_HALT_STATUS
,
196 DWC_OTG_HC_XFER_COMPLETE
,
197 DWC_OTG_HC_XFER_URB_COMPLETE
,
200 DWC_OTG_HC_XFER_NYET
,
201 DWC_OTG_HC_XFER_STALL
,
202 DWC_OTG_HC_XFER_XACT_ERR
,
203 DWC_OTG_HC_XFER_FRAME_OVERRUN
,
204 DWC_OTG_HC_XFER_BABBLE_ERR
,
205 DWC_OTG_HC_XFER_DATA_TOGGLE_ERR
,
206 DWC_OTG_HC_XFER_AHB_ERR
,
207 DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE
,
208 DWC_OTG_HC_XFER_URB_DEQUEUE
209 } dwc_otg_halt_status_e
;
212 * Host channel descriptor. This structure represents the state of a single
213 * host channel when acting in host mode. It contains the data items needed to
214 * transfer packets to an endpoint via a host channel.
216 typedef struct dwc_hc
218 /** Host channel number used for register address lookup */
221 /** Device to access */
222 unsigned dev_addr
: 7;
227 /** EP direction. 0: OUT, 1: IN */
228 unsigned ep_is_in
: 1;
232 * One of the following values:
233 * - DWC_OTG_EP_SPEED_LOW
234 * - DWC_OTG_EP_SPEED_FULL
235 * - DWC_OTG_EP_SPEED_HIGH
238 #define DWC_OTG_EP_SPEED_LOW 0
239 #define DWC_OTG_EP_SPEED_FULL 1
240 #define DWC_OTG_EP_SPEED_HIGH 2
244 * One of the following values:
245 * - DWC_OTG_EP_TYPE_CONTROL: 0
246 * - DWC_OTG_EP_TYPE_ISOC: 1
247 * - DWC_OTG_EP_TYPE_BULK: 2
248 * - DWC_OTG_EP_TYPE_INTR: 3
250 unsigned ep_type
: 2;
252 /** Max packet size in bytes */
253 unsigned max_packet
: 11;
256 * PID for initial transaction.
260 * 3: MDATA (non-Control EP),
263 unsigned data_pid_start
: 2;
264 #define DWC_OTG_HC_PID_DATA0 0
265 #define DWC_OTG_HC_PID_DATA2 1
266 #define DWC_OTG_HC_PID_DATA1 2
267 #define DWC_OTG_HC_PID_MDATA 3
268 #define DWC_OTG_HC_PID_SETUP 3
270 /** Number of periodic transactions per (micro)frame */
271 unsigned multi_count
: 2;
273 /** @name Transfer State */
276 /** Pointer to the current transfer buffer position. */
278 /** Total number of bytes to transfer. */
280 /** Number of bytes transferred so far. */
282 /** Packet count at start of transfer.*/
283 uint16_t start_pkt_count
;
286 * Flag to indicate whether the transfer has been started. Set to 1 if
287 * it has been started, 0 otherwise.
289 uint8_t xfer_started
;
292 * Set to 1 to indicate that a PING request should be issued on this
293 * channel. If 0, process normally.
298 * Set to 1 to indicate that the error count for this transaction is
299 * non-zero. Set to 0 if the error count is 0.
304 * Set to 1 to indicate that this channel should be halted the next
305 * time a request is queued for the channel. This is necessary in
306 * slave mode if no request queue space is available when an attempt
307 * is made to halt the channel.
309 uint8_t halt_on_queue
;
312 * Set to 1 if the host channel has been halted, but the core is not
313 * finished flushing queued requests. Otherwise 0.
315 uint8_t halt_pending
;
318 * Reason for halting the host channel.
320 dwc_otg_halt_status_e halt_status
;
323 * Split settings for the host channel
325 uint8_t do_split
; /**< Enable split for the channel */
326 uint8_t complete_split
; /**< Enable complete split */
327 uint8_t hub_addr
; /**< Address of high speed hub */
329 uint8_t port_addr
; /**< Port of the low/full speed device */
330 /** Split transaction position
331 * One of the following values:
332 * - DWC_HCSPLIT_XACTPOS_MID
333 * - DWC_HCSPLIT_XACTPOS_BEGIN
334 * - DWC_HCSPLIT_XACTPOS_END
335 * - DWC_HCSPLIT_XACTPOS_ALL */
338 /** Set when the host channel does a short read. */
342 * Number of requests issued for this channel since it was assigned to
343 * the current transfer (not counting PINGs).
348 * Queue Head for the transfer being processed by this channel.
350 struct dwc_otg_qh
*qh
;
354 /** Entry in list of host channels. */
355 struct list_head hc_list_entry
;
359 * The following parameters may be specified when starting the module. These
360 * parameters define how the DWC_otg controller should be configured.
361 * Parameter values are passed to the CIL initialization function
364 typedef struct dwc_otg_core_params
367 #define dwc_param_opt_default 1
370 * Specifies the OTG capabilities. The driver will automatically
371 * detect the value for this parameter if none is specified.
372 * 0 - HNP and SRP capable (default)
373 * 1 - SRP Only capable
374 * 2 - No HNP/SRP capable
377 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
378 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
379 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
380 //#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
381 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
384 * Specifies whether to use slave or DMA mode for accessing the data
385 * FIFOs. The driver will automatically detect the value for this
386 * parameter if none is specified.
388 * 1 - DMA (default, if available)
391 #define dwc_param_dma_enable_default 1
394 * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
395 * FIFOs in device mode. The driver will automatically detect the value for this
396 * parameter if none is specified.
398 * 1 - DMA Descriptor(default, if available)
400 int32_t dma_desc_enable
;
401 #define dwc_param_dma_desc_enable_default 0
402 /** The DMA Burst size (applicable only for External DMA
403 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
405 int32_t dma_burst_size
; /* Translate this to GAHBCFG values */
406 //#define dwc_param_dma_burst_size_default 32
407 #define dwc_param_dma_burst_size_default 32
410 * Specifies the maximum speed of operation in host and device mode.
411 * The actual speed depends on the speed of the attached device and
412 * the value of phy_type. The actual speed depends on the speed of the
414 * 0 - High Speed (default)
418 #define dwc_param_speed_default 0
419 #define DWC_SPEED_PARAM_HIGH 0
420 #define DWC_SPEED_PARAM_FULL 1
422 /** Specifies whether low power mode is supported when attached
423 * to a Full Speed or Low Speed device in host mode.
424 * 0 - Don't support low power mode (default)
425 * 1 - Support low power mode
427 int32_t host_support_fs_ls_low_power
;
428 #define dwc_param_host_support_fs_ls_low_power_default 0
430 /** Specifies the PHY clock rate in low power mode when connected to a
431 * Low Speed device in host mode. This parameter is applicable only if
432 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
433 * then defaults to 6 MHZ otherwise 48 MHZ.
438 int32_t host_ls_low_power_phy_clk
;
439 #define dwc_param_host_ls_low_power_phy_clk_default 0
440 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
441 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
444 * 0 - Use cC FIFO size parameters
445 * 1 - Allow dynamic FIFO sizing (default)
447 int32_t enable_dynamic_fifo
;
448 #define dwc_param_enable_dynamic_fifo_default 1
450 /** Total number of 4-byte words in the data FIFO memory. This
451 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
453 * 32 to 32768 (default 8192)
454 * Note: The total FIFO memory depth in the FPGA configuration is 8192.
456 int32_t data_fifo_size
;
457 #define dwc_param_data_fifo_size_default 8192
459 /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
460 * FIFO sizing is enabled.
461 * 16 to 32768 (default 1064)
463 int32_t dev_rx_fifo_size
;
464 //#define dwc_param_dev_rx_fifo_size_default 1064
465 #define dwc_param_dev_rx_fifo_size_default 0x100
468 * Specifies whether dedicated transmit FIFOs are
469 * enabled for non periodic IN endpoints in device mode
473 int32_t en_multiple_tx_fifo
;
474 #define dwc_param_en_multiple_tx_fifo_default 1
476 /** Number of 4-byte words in each of the Tx FIFOs in device
477 * mode when dynamic FIFO sizing is enabled.
478 * 4 to 768 (default 256)
480 uint32_t dev_tx_fifo_size
[MAX_TX_FIFOS
];
481 //#define dwc_param_dev_tx_fifo_size_default 256
482 #define dwc_param_dev_tx_fifo_size_default 0x80
484 /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
485 * when dynamic FIFO sizing is enabled.
486 * 16 to 32768 (default 1024)
488 int32_t dev_nperio_tx_fifo_size
;
489 //#define dwc_param_dev_nperio_tx_fifo_size_default 1024
490 #define dwc_param_dev_nperio_tx_fifo_size_default 0x80
492 /** Number of 4-byte words in each of the periodic Tx FIFOs in device
493 * mode when dynamic FIFO sizing is enabled.
494 * 4 to 768 (default 256)
496 uint32_t dev_perio_tx_fifo_size
[MAX_PERIO_FIFOS
];
497 //#define dwc_param_dev_perio_tx_fifo_size_default 256
498 #define dwc_param_dev_perio_tx_fifo_size_default 0x80
500 /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
501 * FIFO sizing is enabled.
502 * 16 to 32768 (default 1024)
504 int32_t host_rx_fifo_size
;
505 //#define dwc_param_host_rx_fifo_size_default 1024
506 #define dwc_param_host_rx_fifo_size_default 0x292
508 /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
509 * when Dynamic FIFO sizing is enabled in the core.
510 * 16 to 32768 (default 1024)
512 int32_t host_nperio_tx_fifo_size
;
513 //#define dwc_param_host_nperio_tx_fifo_size_default 1024
514 //#define dwc_param_host_nperio_tx_fifo_size_default 0x292
515 #define dwc_param_host_nperio_tx_fifo_size_default 0x80
517 /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
518 * FIFO sizing is enabled.
519 * 16 to 32768 (default 1024)
521 int32_t host_perio_tx_fifo_size
;
522 //#define dwc_param_host_perio_tx_fifo_size_default 1024
523 #define dwc_param_host_perio_tx_fifo_size_default 0x292
525 /** The maximum transfer size supported in bytes.
526 * 2047 to 65,535 (default 65,535)
528 int32_t max_transfer_size
;
529 #define dwc_param_max_transfer_size_default 65535
531 /** The maximum number of packets in a transfer.
532 * 15 to 511 (default 511)
534 int32_t max_packet_count
;
535 #define dwc_param_max_packet_count_default 511
537 /** The number of host channel registers to use.
538 * 1 to 16 (default 12)
539 * Note: The FPGA configuration supports a maximum of 12 host channels.
541 int32_t host_channels
;
542 //#define dwc_param_host_channels_default 12
543 #define dwc_param_host_channels_default 16
545 /** The number of endpoints in addition to EP0 available for device
547 * 1 to 15 (default 6 IN and OUT)
548 * Note: The FPGA configuration supports a maximum of 6 IN and OUT
549 * endpoints in addition to EP0.
551 int32_t dev_endpoints
;
552 //#define dwc_param_dev_endpoints_default 6
553 #define dwc_param_dev_endpoints_default 8
556 * Specifies the type of PHY interface to use. By default, the driver
557 * will automatically detect the phy_type.
560 * 1 - UTMI+ (default)
564 #define DWC_PHY_TYPE_PARAM_FS 0
565 #define DWC_PHY_TYPE_PARAM_UTMI 1
566 #define DWC_PHY_TYPE_PARAM_ULPI 2
567 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
570 * Specifies the UTMI+ Data Width. This parameter is
571 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
572 * PHY_TYPE, this parameter indicates the data width between
573 * the MAC and the ULPI Wrapper.) Also, this parameter is
574 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
575 * to "8 and 16 bits", meaning that the core has been
576 * configured to work at either data path width.
578 * 8 or 16 bits (default 16)
580 int32_t phy_utmi_width
;
581 #define dwc_param_phy_utmi_width_default 16
584 * Specifies whether the ULPI operates at double or single
585 * data rate. This parameter is only applicable if PHY_TYPE is
588 * 0 - single data rate ULPI interface with 8 bit wide data
590 * 1 - double data rate ULPI interface with 4 bit wide data
593 int32_t phy_ulpi_ddr
;
594 #define dwc_param_phy_ulpi_ddr_default 0
597 * Specifies whether to use the internal or external supply to
598 * drive the vbus with a ULPI phy.
600 int32_t phy_ulpi_ext_vbus
;
601 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
602 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
603 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
606 * Specifies whether to use the I2Cinterface for full speed PHY. This
607 * parameter is only applicable if PHY_TYPE is FS.
612 #define dwc_param_i2c_enable_default 0
615 #define dwc_param_ulpi_fs_ls_default 0
618 #define dwc_param_ts_dline_default 0
620 /** Thresholding enable flag-
621 * bit 0 - enable non-ISO Tx thresholding
622 * bit 1 - enable ISO Tx thresholding
623 * bit 2 - enable Rx thresholding
626 #define dwc_param_thr_ctl_default 0
628 /** Thresholding length for Tx
629 * FIFOs in 32 bit DWORDs
631 uint32_t tx_thr_length
;
632 #define dwc_param_tx_thr_length_default 64
634 /** Thresholding length for Rx
635 * FIFOs in 32 bit DWORDs
637 uint32_t rx_thr_length
;
638 #define dwc_param_rx_thr_length_default 64
640 /** Per Transfer Interrupt
646 #define dwc_param_pti_enable_default 0
648 /** Molti Processor Interrupt
654 #define dwc_param_mpi_enable_default 0
656 } dwc_otg_core_params_t
;
659 struct dwc_otg_core_if
;
660 typedef struct hc_xfer_info
662 struct dwc_otg_core_if
*core_if
;
668 * The <code>dwc_otg_core_if</code> structure contains information needed to manage
669 * the DWC_otg controller acting in either host or device mode. It
670 * represents the programming view of the controller as a whole.
672 typedef struct dwc_otg_core_if
674 /** Parameters that define how the core should be configured.*/
675 dwc_otg_core_params_t
*core_params
;
677 /** Core Global registers starting at offset 000h. */
678 dwc_otg_core_global_regs_t
*core_global_regs
;
680 /** Device-specific information */
681 dwc_otg_dev_if_t
*dev_if
;
682 /** Host-specific information */
683 dwc_otg_host_if_t
*host_if
;
685 /** Value from SNPSID register */
689 * Set to 1 if the core PHY interface bits in USBCFG have been
692 uint8_t phy_init_done
;
695 * SRP Success flag, set by srp success interrupt in FS I2C mode
698 uint8_t srp_timer_started
;
700 /* Common configuration information */
701 /** Power and Clock Gating Control Register */
702 volatile uint32_t *pcgcctl
;
703 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
705 /** Push/pop addresses for endpoints or host channels.*/
706 uint32_t *data_fifo
[MAX_EPS_CHANNELS
];
707 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
708 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
710 /** Total RAM for FIFOs (Bytes) */
711 uint16_t total_fifo_size
;
712 /** Size of Rx FIFO (Bytes) */
713 uint16_t rx_fifo_size
;
714 /** Size of Non-periodic Tx FIFO (Bytes) */
715 uint16_t nperio_tx_fifo_size
;
718 /** 1 if DMA is enabled, 0 otherwise. */
721 /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
722 uint8_t dma_desc_enable
;
724 /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
725 uint8_t pti_enh_enable
;
727 /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
728 uint8_t multiproc_int_enable
;
730 /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
731 uint8_t en_multiple_tx_fifo
;
733 /** Set to 1 if multiple packets of a high-bandwidth transfer is in
734 * process of being queued */
735 uint8_t queuing_high_bandwidth
;
737 /** Hardware Configuration -- stored here for convenience.*/
738 hwcfg1_data_t hwcfg1
;
739 hwcfg2_data_t hwcfg2
;
740 hwcfg3_data_t hwcfg3
;
741 hwcfg4_data_t hwcfg4
;
743 /** Host and Device Configuration -- stored here for convenience.*/
747 /** The operational State, during transations
748 * (a_host>>a_peripherial and b_device=>b_host) this may not
749 * match the core but allows the software to determine
755 * Set to 1 if the HCD needs to be restarted on a session request
756 * interrupt. This is required if no connector ID status change has
757 * occurred since the HCD was last disconnected.
759 uint8_t restart_hcd_on_session_req
;
762 /** A-Device is a_host */
764 /** A-Device is a_suspend */
765 #define A_SUSPEND (2)
766 /** A-Device is a_peripherial */
767 #define A_PERIPHERAL (3)
768 /** B-Device is operating as a Peripheral. */
769 #define B_PERIPHERAL (4)
770 /** B-Device is operating as a Host. */
774 struct dwc_otg_cil_callbacks
*hcd_cb
;
776 struct dwc_otg_cil_callbacks
*pcd_cb
;
778 /** Device mode Periodic Tx FIFO Mask */
780 /** Device mode Periodic Tx FIFO Mask */
783 /** Workqueue object used for handling several interrupts */
784 struct workqueue_struct
*wq_otg
;
786 /** Work object used for handling "Connector ID Status Change" Interrupt */
787 struct work_struct w_conn_id
;
789 /** Work object used for handling "Wakeup Detected" Interrupt */
790 struct delayed_work w_wkp
;
793 uint32_t start_hcchar_val
[MAX_EPS_CHANNELS
];
795 hc_xfer_info_t hc_xfer_info
[MAX_EPS_CHANNELS
];
796 struct timer_list hc_xfer_timer
[MAX_EPS_CHANNELS
];
798 uint32_t hfnum_7_samples
;
799 uint64_t hfnum_7_frrem_accum
;
800 uint32_t hfnum_0_samples
;
801 uint64_t hfnum_0_frrem_accum
;
802 uint32_t hfnum_other_samples
;
803 uint64_t hfnum_other_frrem_accum
;
809 /*We must clear S3C24XX_EINTPEND external interrupt register
810 * because after clearing in this register trigerred IRQ from
811 * H/W core in kernel interrupt can be occured again before OTG
812 * handlers clear all IRQ sources of Core registers because of
813 * timing latencies and Low Level IRQ Type.
816 #ifdef CONFIG_MACH_IPMATE
817 #define S3C2410X_CLEAR_EINTPEND() \
819 if (!dwc_otg_read_core_intr(core_if)) { \
820 __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
824 #define S3C2410X_CLEAR_EINTPEND() do { } while (0)
828 * The following functions are functions for works
829 * using during handling some interrupts
831 extern void w_conn_id_status_change(struct work_struct
*p
);
832 extern void w_wakeup_detected(struct work_struct
*p
);
836 * The following functions support initialization of the CIL driver component
837 * and the DWC_otg controller.
839 extern dwc_otg_core_if_t
*dwc_otg_cil_init(const uint32_t *_reg_base_addr
,
840 dwc_otg_core_params_t
*_core_params
);
841 extern void dwc_otg_cil_remove(dwc_otg_core_if_t
*_core_if
);
842 extern void dwc_otg_core_init(dwc_otg_core_if_t
*_core_if
);
843 extern void dwc_otg_core_host_init(dwc_otg_core_if_t
*_core_if
);
844 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t
*_core_if
);
845 extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t
*_core_if
);
846 extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t
*_core_if
);
848 /** @name Device CIL Functions
849 * The following functions support managing the DWC_otg controller in device
853 extern void dwc_otg_wakeup(dwc_otg_core_if_t
*_core_if
);
854 extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t
*_core_if
, uint32_t *_dest
);
855 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t
*_core_if
);
856 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
857 extern void dwc_otg_ep_activate(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
858 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
859 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
860 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
861 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
862 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
863 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
, int _dma
);
864 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
865 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t
*_core_if
, dwc_ep_t
*_ep
);
866 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t
*_core_if
);
867 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t
*_core_if
);
868 extern void dwc_otg_dump_spram(dwc_otg_core_if_t
*_core_if
);
870 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
);
871 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t
*core_if
, dwc_ep_t
*ep
);
875 /** @name Host CIL Functions
876 * The following functions support managing the DWC_otg controller in host
880 extern void dwc_otg_hc_init(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
881 extern void dwc_otg_hc_halt(struct dwc_otg_hcd
*_hcd
,
883 dwc_otg_halt_status_e _halt_status
);
884 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
885 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
886 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
887 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
888 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
);
889 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t
*_core_if
);
890 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t
*_core_if
);
893 * This function Reads HPRT0 in preparation to modify. It keeps the
894 * WC bits 0 so that if they are read as 1, they won't clear when you
897 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t
*_core_if
)
900 hprt0
.d32
= dwc_read_reg32(_core_if
->host_if
->hprt0
);
902 hprt0
.b
.prtconndet
= 0;
903 hprt0
.b
.prtenchng
= 0;
904 hprt0
.b
.prtovrcurrchng
= 0;
908 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t
*_core_if
);
911 /** @name Common CIL Functions
912 * The following functions support managing the DWC_otg controller in either
913 * device or host mode.
917 extern void dwc_otg_read_packet(dwc_otg_core_if_t
*core_if
,
921 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t
*_core_if
);
923 extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t
*_core_if
,
925 extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t
*_core_if
);
926 extern void dwc_otg_core_reset( dwc_otg_core_if_t
*_core_if
);
928 extern dwc_otg_dma_desc_t
* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr
, uint32_t count
);
929 extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t
* desc_addr
, uint32_t dma_desc_addr
, uint32_t count
);
932 * This function returns the Core Interrupt register.
934 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t
*_core_if
)
936 return (dwc_read_reg32(&_core_if
->core_global_regs
->gintsts
) &
937 dwc_read_reg32(&_core_if
->core_global_regs
->gintmsk
));
941 * This function returns the OTG Interrupt register.
943 static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t
*_core_if
)
945 return (dwc_read_reg32 (&_core_if
->core_global_regs
->gotgint
));
949 * This function reads the Device All Endpoints Interrupt register and
950 * returns the IN endpoint interrupt bits.
952 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t
*core_if
)
956 if(core_if
->multiproc_int_enable
) {
957 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachint
) &
958 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachintmsk
);
960 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daint
) &
961 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daintmsk
);
968 * This function reads the Device All Endpoints Interrupt register and
969 * returns the OUT endpoint interrupt bits.
971 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t
*core_if
)
975 if(core_if
->multiproc_int_enable
) {
976 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachint
) &
977 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->deachintmsk
);
979 v
= dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daint
) &
980 dwc_read_reg32(&core_if
->dev_if
->dev_global_regs
->daintmsk
);
983 return ((v
& 0xffff0000) >> 16);
987 * This function returns the Device IN EP Interrupt register
989 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t
*core_if
,
992 dwc_otg_dev_if_t
*dev_if
= core_if
->dev_if
;
993 uint32_t v
, msk
, emp
;
995 if(core_if
->multiproc_int_enable
) {
996 msk
= dwc_read_reg32(&dev_if
->dev_global_regs
->diepeachintmsk
[ep
->num
]);
997 emp
= dwc_read_reg32(&dev_if
->dev_global_regs
->dtknqr4_fifoemptymsk
);
998 msk
|= ((emp
>> ep
->num
) & 0x1) << 7;
999 v
= dwc_read_reg32(&dev_if
->in_ep_regs
[ep
->num
]->diepint
) & msk
;
1001 msk
= dwc_read_reg32(&dev_if
->dev_global_regs
->diepmsk
);
1002 emp
= dwc_read_reg32(&dev_if
->dev_global_regs
->dtknqr4_fifoemptymsk
);
1003 msk
|= ((emp
>> ep
->num
) & 0x1) << 7;
1004 v
= dwc_read_reg32(&dev_if
->in_ep_regs
[ep
->num
]->diepint
) & msk
;
1011 * This function returns the Device OUT EP Interrupt register
1013 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t
*_core_if
,
1016 dwc_otg_dev_if_t
*dev_if
= _core_if
->dev_if
;
1018 doepmsk_data_t msk
= { .d32
= 0 };
1020 if(_core_if
->multiproc_int_enable
) {
1021 msk
.d32
= dwc_read_reg32(&dev_if
->dev_global_regs
->doepeachintmsk
[_ep
->num
]);
1022 if(_core_if
->pti_enh_enable
) {
1023 msk
.b
.pktdrpsts
= 1;
1025 v
= dwc_read_reg32( &dev_if
->out_ep_regs
[_ep
->num
]->doepint
) & msk
.d32
;
1027 msk
.d32
= dwc_read_reg32(&dev_if
->dev_global_regs
->doepmsk
);
1028 if(_core_if
->pti_enh_enable
) {
1029 msk
.b
.pktdrpsts
= 1;
1031 v
= dwc_read_reg32( &dev_if
->out_ep_regs
[_ep
->num
]->doepint
) & msk
.d32
;
1037 * This function returns the Host All Channel Interrupt register
1039 static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t
*_core_if
)
1041 return (dwc_read_reg32 (&_core_if
->host_if
->host_global_regs
->haint
));
1044 static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t
*_core_if
, dwc_hc_t
*_hc
)
1046 return (dwc_read_reg32 (&_core_if
->host_if
->hc_regs
[_hc
->hc_num
]->hcint
));
1051 * This function returns the mode of the operation, host or device.
1053 * @return 0 - Device Mode, 1 - Host Mode
1055 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t
*_core_if
)
1057 return (dwc_read_reg32( &_core_if
->core_global_regs
->gintsts
) & 0x1);
1060 static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t
*_core_if
)
1062 return (dwc_otg_mode(_core_if
) != DWC_HOST_MODE
);
1064 static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t
*_core_if
)
1066 return (dwc_otg_mode(_core_if
) == DWC_HOST_MODE
);
1069 extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t
*_core_if
);
1075 * DWC_otg CIL callback structure. This structure allows the HCD and
1076 * PCD to register functions used for starting and stopping the PCD
1077 * and HCD for role change on for a DRD.
1079 typedef struct dwc_otg_cil_callbacks
1081 /** Start function for role change */
1082 int (*start
) (void *_p
);
1083 /** Stop Function for role change */
1084 int (*stop
) (void *_p
);
1085 /** Disconnect Function for role change */
1086 int (*disconnect
) (void *_p
);
1087 /** Resume/Remote wakeup Function */
1088 int (*resume_wakeup
) (void *_p
);
1089 /** Suspend function */
1090 int (*suspend
) (void *_p
);
1091 /** Session Start (SRP) */
1092 int (*session_start
) (void *_p
);
1093 /** Pointer passed to start() and stop() */
1095 } dwc_otg_cil_callbacks_t
;
1097 extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t
*_core_if
,
1098 dwc_otg_cil_callbacks_t
*_cb
,
1100 extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t
*_core_if
,
1101 dwc_otg_cil_callbacks_t
*_cb
,