1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include <linux/kernel.h>
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/init.h>
55 #include <linux/device.h>
56 #include <linux/errno.h>
57 #include <linux/types.h>
58 #include <linux/stat.h> /* permission constants */
59 #include <linux/version.h>
60 #include <linux/platform_device.h>
62 #include <linux/irq.h>
65 #include <asm/sizes.h>
70 #include "otg_driver.h"
75 #define DWC_DRIVER_VERSION "2.72a 24-JUN-2008"
76 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
78 static const char dwc_driver_name
[] = "dwc_otg";
80 /*-------------------------------------------------------------------------*/
81 /* Encapsulate the module parameter settings */
83 static dwc_otg_core_params_t dwc_otg_module_params
= {
87 .dma_desc_enable
= -1,
90 .host_support_fs_ls_low_power
= -1,
91 .host_ls_low_power_phy_clk
= -1,
92 .enable_dynamic_fifo
= -1,
94 .dev_rx_fifo_size
= -1,
95 .dev_nperio_tx_fifo_size
= -1,
96 .dev_perio_tx_fifo_size
= {
97 /* dev_perio_tx_fifo_size_1 */
115 .host_rx_fifo_size
= -1,
116 .host_nperio_tx_fifo_size
= -1,
117 .host_perio_tx_fifo_size
= -1,
118 .max_transfer_size
= -1,
119 .max_packet_count
= -1,
123 .phy_utmi_width
= -1,
125 .phy_ulpi_ext_vbus
= -1,
129 .en_multiple_tx_fifo
= -1,
130 .dev_tx_fifo_size
= {
131 /* dev_tx_fifo_size */
157 * Global Debug Level Mask.
159 uint32_t g_dbg_lvl
= 0; /* OFF */
162 * This function is called during module intialization to verify that
163 * the module parameters are in a valid state.
165 static int check_parameters(dwc_otg_core_if_t
*core_if
)
170 /* Checks if the parameter is outside of its valid range of values */
171 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
172 ((dwc_otg_module_params._param_ < (_low_)) || \
173 (dwc_otg_module_params._param_ > (_high_)))
175 /* If the parameter has been set by the user, check that the parameter value is
176 * within the value range of values. If not, report a module error. */
177 #define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
179 if (dwc_otg_module_params._param_ != -1) { \
180 if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
181 DWC_ERROR("`%d' invalid for parameter `%s'\n", \
182 dwc_otg_module_params._param_, _string_); \
183 dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
189 DWC_OTG_PARAM_ERR(opt
,0,1,"opt");
190 DWC_OTG_PARAM_ERR(otg_cap
,0,2,"otg_cap");
191 DWC_OTG_PARAM_ERR(dma_enable
,0,1,"dma_enable");
192 DWC_OTG_PARAM_ERR(dma_desc_enable
,0,1,"dma_desc_enable");
193 DWC_OTG_PARAM_ERR(speed
,0,1,"speed");
194 DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power
,0,1,"host_support_fs_ls_low_power");
195 DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk
,0,1,"host_ls_low_power_phy_clk");
196 DWC_OTG_PARAM_ERR(enable_dynamic_fifo
,0,1,"enable_dynamic_fifo");
197 DWC_OTG_PARAM_ERR(data_fifo_size
,32,32768,"data_fifo_size");
198 DWC_OTG_PARAM_ERR(dev_rx_fifo_size
,16,32768,"dev_rx_fifo_size");
199 DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size
,16,32768,"dev_nperio_tx_fifo_size");
200 DWC_OTG_PARAM_ERR(host_rx_fifo_size
,16,32768,"host_rx_fifo_size");
201 DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size
,16,32768,"host_nperio_tx_fifo_size");
202 DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size
,16,32768,"host_perio_tx_fifo_size");
203 DWC_OTG_PARAM_ERR(max_transfer_size
,2047,524288,"max_transfer_size");
204 DWC_OTG_PARAM_ERR(max_packet_count
,15,511,"max_packet_count");
205 DWC_OTG_PARAM_ERR(host_channels
,1,16,"host_channels");
206 DWC_OTG_PARAM_ERR(dev_endpoints
,1,15,"dev_endpoints");
207 DWC_OTG_PARAM_ERR(phy_type
,0,2,"phy_type");
208 DWC_OTG_PARAM_ERR(phy_ulpi_ddr
,0,1,"phy_ulpi_ddr");
209 DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus
,0,1,"phy_ulpi_ext_vbus");
210 DWC_OTG_PARAM_ERR(i2c_enable
,0,1,"i2c_enable");
211 DWC_OTG_PARAM_ERR(ulpi_fs_ls
,0,1,"ulpi_fs_ls");
212 DWC_OTG_PARAM_ERR(ts_dline
,0,1,"ts_dline");
214 if (dwc_otg_module_params
.dma_burst_size
!= -1) {
215 if (DWC_OTG_PARAM_TEST(dma_burst_size
,1,1) &&
216 DWC_OTG_PARAM_TEST(dma_burst_size
,4,4) &&
217 DWC_OTG_PARAM_TEST(dma_burst_size
,8,8) &&
218 DWC_OTG_PARAM_TEST(dma_burst_size
,16,16) &&
219 DWC_OTG_PARAM_TEST(dma_burst_size
,32,32) &&
220 DWC_OTG_PARAM_TEST(dma_burst_size
,64,64) &&
221 DWC_OTG_PARAM_TEST(dma_burst_size
,128,128) &&
222 DWC_OTG_PARAM_TEST(dma_burst_size
,256,256)) {
223 DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
224 dwc_otg_module_params
.dma_burst_size
);
225 dwc_otg_module_params
.dma_burst_size
= 32;
231 while(dwc_otg_module_params
.dma_burst_size
> 1) {
233 dwc_otg_module_params
.dma_burst_size
>>= 1;
235 dwc_otg_module_params
.dma_burst_size
= brst_sz
;
239 if (dwc_otg_module_params
.phy_utmi_width
!= -1) {
240 if (DWC_OTG_PARAM_TEST(phy_utmi_width
, 8, 8) &&
241 DWC_OTG_PARAM_TEST(phy_utmi_width
, 16, 16)) {
242 DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
243 dwc_otg_module_params
.phy_utmi_width
);
244 dwc_otg_module_params
.phy_utmi_width
= 16;
249 for (i
= 0; i
< 15; i
++) {
250 /** @todo should be like above */
251 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
252 if (dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
] != -1) {
253 if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size
[i
], 4, 768)) {
254 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
255 dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
], "dev_perio_tx_fifo_size", i
);
256 dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
] = dwc_param_dev_perio_tx_fifo_size_default
;
262 DWC_OTG_PARAM_ERR(en_multiple_tx_fifo
, 0, 1, "en_multiple_tx_fifo");
264 for (i
= 0; i
< 15; i
++) {
265 /** @todo should be like above */
266 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
267 if (dwc_otg_module_params
.dev_tx_fifo_size
[i
] != -1) {
268 if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size
[i
], 4, 768)) {
269 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
270 dwc_otg_module_params
.dev_tx_fifo_size
[i
], "dev_tx_fifo_size", i
);
271 dwc_otg_module_params
.dev_tx_fifo_size
[i
] = dwc_param_dev_tx_fifo_size_default
;
277 DWC_OTG_PARAM_ERR(thr_ctl
, 0, 7, "thr_ctl");
278 DWC_OTG_PARAM_ERR(tx_thr_length
, 8, 128, "tx_thr_length");
279 DWC_OTG_PARAM_ERR(rx_thr_length
, 8, 128, "rx_thr_length");
281 DWC_OTG_PARAM_ERR(pti_enable
,0,1,"pti_enable");
282 DWC_OTG_PARAM_ERR(mpi_enable
,0,1,"mpi_enable");
284 /* At this point, all module parameters that have been set by the user
285 * are valid, and those that have not are left unset. Now set their
286 * default values and/or check the parameters against the hardware
287 * configurations of the OTG core. */
289 /* This sets the parameter to the default value if it has not been set by the
291 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
294 if (dwc_otg_module_params._param_ == -1) { \
296 dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
301 /* This checks the macro agains the hardware configuration to see if it is
302 * valid. It is possible that the default value could be invalid. In this
303 * case, it will report a module error if the user touched the parameter.
304 * Otherwise it will adjust the value without any error. */
305 #define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
307 int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
309 if (!(_is_valid_)) { \
311 DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
314 dwc_otg_module_params._param_ = (_set_valid_); \
320 retval
+= DWC_OTG_PARAM_CHECK_VALID(otg_cap
, "otg_cap",
324 switch (dwc_otg_module_params
.otg_cap
) {
325 case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
:
326 if (core_if
->hwcfg2
.b
.op_mode
!= DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG
)
329 case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE
:
330 if ((core_if
->hwcfg2
.b
.op_mode
!= DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG
) &&
331 (core_if
->hwcfg2
.b
.op_mode
!= DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG
) &&
332 (core_if
->hwcfg2
.b
.op_mode
!= DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
) &&
333 (core_if
->hwcfg2
.b
.op_mode
!= DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST
)) {
337 case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
:
343 (((core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG
) ||
344 (core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG
) ||
345 (core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
) ||
346 (core_if
->hwcfg2
.b
.op_mode
== DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST
)) ?
347 DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE
:
348 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
));
350 retval
+= DWC_OTG_PARAM_CHECK_VALID(dma_enable
, "dma_enable",
351 ((dwc_otg_module_params
.dma_enable
== 1) && (core_if
->hwcfg2
.b
.architecture
== 0)) ? 0 : 1,
354 retval
+= DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable
, "dma_desc_enable",
355 ((dwc_otg_module_params
.dma_desc_enable
== 1) &&
356 ((dwc_otg_module_params
.dma_enable
== 0) || (core_if
->hwcfg4
.b
.desc_dma
== 0))) ? 0 : 1,
359 retval
+= DWC_OTG_PARAM_CHECK_VALID(opt
, "opt", 1, 0);
361 DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size
);
363 retval
+= DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power
,
364 "host_support_fs_ls_low_power",
367 retval
+= DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo
,
368 "enable_dynamic_fifo",
369 ((dwc_otg_module_params
.enable_dynamic_fifo
== 0) ||
370 (core_if
->hwcfg2
.b
.dynamic_fifo
== 1)), 0);
372 retval
+= DWC_OTG_PARAM_CHECK_VALID(data_fifo_size
,
374 (dwc_otg_module_params
.data_fifo_size
<= core_if
->hwcfg3
.b
.dfifo_depth
),
375 core_if
->hwcfg3
.b
.dfifo_depth
);
377 retval
+= DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size
,
379 (dwc_otg_module_params
.dev_rx_fifo_size
<= dwc_read_reg32(&core_if
->core_global_regs
->grxfsiz
)),
380 dwc_read_reg32(&core_if
->core_global_regs
->grxfsiz
));
382 retval
+= DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size
,
383 "dev_nperio_tx_fifo_size",
384 (dwc_otg_module_params
.dev_nperio_tx_fifo_size
<= (dwc_read_reg32(&core_if
->core_global_regs
->gnptxfsiz
) >> 16)),
385 (dwc_read_reg32(&core_if
->core_global_regs
->gnptxfsiz
) >> 16));
387 retval
+= DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size
,
389 (dwc_otg_module_params
.host_rx_fifo_size
<= dwc_read_reg32(&core_if
->core_global_regs
->grxfsiz
)),
390 dwc_read_reg32(&core_if
->core_global_regs
->grxfsiz
));
392 retval
+= DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size
,
393 "host_nperio_tx_fifo_size",
394 (dwc_otg_module_params
.host_nperio_tx_fifo_size
<= (dwc_read_reg32(&core_if
->core_global_regs
->gnptxfsiz
) >> 16)),
395 (dwc_read_reg32(&core_if
->core_global_regs
->gnptxfsiz
) >> 16));
397 retval
+= DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size
,
398 "host_perio_tx_fifo_size",
399 (dwc_otg_module_params
.host_perio_tx_fifo_size
<= ((dwc_read_reg32(&core_if
->core_global_regs
->hptxfsiz
) >> 16))),
400 ((dwc_read_reg32(&core_if
->core_global_regs
->hptxfsiz
) >> 16)));
402 retval
+= DWC_OTG_PARAM_CHECK_VALID(max_transfer_size
,
404 (dwc_otg_module_params
.max_transfer_size
< (1 << (core_if
->hwcfg3
.b
.xfer_size_cntr_width
+ 11))),
405 ((1 << (core_if
->hwcfg3
.b
.xfer_size_cntr_width
+ 11)) - 1));
407 retval
+= DWC_OTG_PARAM_CHECK_VALID(max_packet_count
,
409 (dwc_otg_module_params
.max_packet_count
< (1 << (core_if
->hwcfg3
.b
.packet_size_cntr_width
+ 4))),
410 ((1 << (core_if
->hwcfg3
.b
.packet_size_cntr_width
+ 4)) - 1));
412 retval
+= DWC_OTG_PARAM_CHECK_VALID(host_channels
,
414 (dwc_otg_module_params
.host_channels
<= (core_if
->hwcfg2
.b
.num_host_chan
+ 1)),
415 (core_if
->hwcfg2
.b
.num_host_chan
+ 1));
417 retval
+= DWC_OTG_PARAM_CHECK_VALID(dev_endpoints
,
419 (dwc_otg_module_params
.dev_endpoints
<= (core_if
->hwcfg2
.b
.num_dev_ep
)),
420 core_if
->hwcfg2
.b
.num_dev_ep
);
423 * Define the following to disable the FS PHY Hardware checking. This is for
424 * internal testing only.
426 * #define NO_FS_PHY_HW_CHECKS
429 #ifdef NO_FS_PHY_HW_CHECKS
430 retval
+= DWC_OTG_PARAM_CHECK_VALID(phy_type
,
433 retval
+= DWC_OTG_PARAM_CHECK_VALID(phy_type
,
437 if ((dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_UTMI
) &&
438 ((core_if
->hwcfg2
.b
.hs_phy_type
== 1) ||
439 (core_if
->hwcfg2
.b
.hs_phy_type
== 3))) {
442 else if ((dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_ULPI
) &&
443 ((core_if
->hwcfg2
.b
.hs_phy_type
== 2) ||
444 (core_if
->hwcfg2
.b
.hs_phy_type
== 3))) {
447 else if ((dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_FS
) &&
448 (core_if
->hwcfg2
.b
.fs_phy_type
== 1)) {
454 int set
= DWC_PHY_TYPE_PARAM_FS
;
455 if (core_if
->hwcfg2
.b
.hs_phy_type
) {
456 if ((core_if
->hwcfg2
.b
.hs_phy_type
== 3) ||
457 (core_if
->hwcfg2
.b
.hs_phy_type
== 1)) {
458 set
= DWC_PHY_TYPE_PARAM_UTMI
;
461 set
= DWC_PHY_TYPE_PARAM_ULPI
;
468 retval
+= DWC_OTG_PARAM_CHECK_VALID(speed
, "speed",
469 (dwc_otg_module_params
.speed
== 0) && (dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_FS
) ? 0 : 1,
470 dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_FS
? 1 : 0);
472 retval
+= DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk
,
473 "host_ls_low_power_phy_clk",
474 ((dwc_otg_module_params
.host_ls_low_power_phy_clk
== DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
) && (dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_FS
) ? 0 : 1),
475 ((dwc_otg_module_params
.phy_type
== DWC_PHY_TYPE_PARAM_FS
) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
: DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
));
477 DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr
);
478 DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus
);
479 DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width
);
480 DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls
);
481 DWC_OTG_PARAM_SET_DEFAULT(ts_dline
);
483 #ifdef NO_FS_PHY_HW_CHECKS
484 retval
+= DWC_OTG_PARAM_CHECK_VALID(i2c_enable
, "i2c_enable", 1, 0);
486 retval
+= DWC_OTG_PARAM_CHECK_VALID(i2c_enable
,
488 (dwc_otg_module_params
.i2c_enable
== 1) && (core_if
->hwcfg3
.b
.i2c
== 0) ? 0 : 1,
492 for (i
= 0; i
< 15; i
++) {
496 if (dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
] == -1) {
498 dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
] = dwc_param_dev_perio_tx_fifo_size_default
;
500 if (!(dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
] <= (dwc_read_reg32(&core_if
->core_global_regs
->dptxfsiz_dieptxf
[i
])))) {
502 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
], i
);
505 dwc_otg_module_params
.dev_perio_tx_fifo_size
[i
] = dwc_read_reg32(&core_if
->core_global_regs
->dptxfsiz_dieptxf
[i
]);
510 retval
+= DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo
, "en_multiple_tx_fifo",
511 ((dwc_otg_module_params
.en_multiple_tx_fifo
== 1) && (core_if
->hwcfg4
.b
.ded_fifo_en
== 0)) ? 0 : 1,
514 for (i
= 0; i
< 15; i
++) {
518 if (dwc_otg_module_params
.dev_tx_fifo_size
[i
] == -1) {
520 dwc_otg_module_params
.dev_tx_fifo_size
[i
] = dwc_param_dev_tx_fifo_size_default
;
522 if (!(dwc_otg_module_params
.dev_tx_fifo_size
[i
] <= (dwc_read_reg32(&core_if
->core_global_regs
->dptxfsiz_dieptxf
[i
])))) {
524 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params
.dev_tx_fifo_size
[i
], i
);
527 dwc_otg_module_params
.dev_tx_fifo_size
[i
] = dwc_read_reg32(&core_if
->core_global_regs
->dptxfsiz_dieptxf
[i
]);
532 retval
+= DWC_OTG_PARAM_CHECK_VALID(thr_ctl
, "thr_ctl",
533 ((dwc_otg_module_params
.thr_ctl
!= 0) && ((dwc_otg_module_params
.dma_enable
== 0) || (core_if
->hwcfg4
.b
.ded_fifo_en
== 0))) ? 0 : 1,
536 DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length
);
537 DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length
);
539 retval
+= DWC_OTG_PARAM_CHECK_VALID(pti_enable
, "pti_enable",
540 ((dwc_otg_module_params
.pti_enable
== 0) || ((dwc_otg_module_params
.pti_enable
== 1) && (core_if
->snpsid
>= 0x4F54272A))) ? 1 : 0,
543 retval
+= DWC_OTG_PARAM_CHECK_VALID(mpi_enable
, "mpi_enable",
544 ((dwc_otg_module_params
.mpi_enable
== 0) || ((dwc_otg_module_params
.mpi_enable
== 1) && (core_if
->hwcfg2
.b
.multi_proc_int
== 1))) ? 1 : 0,
550 * This function is the top level interrupt handler for the Common
551 * (Device and host modes) interrupts.
553 static irqreturn_t
dwc_otg_common_irq(int irq
, void *dev
)
555 dwc_otg_device_t
*otg_dev
= dev
;
556 int32_t retval
= IRQ_NONE
;
558 retval
= dwc_otg_handle_common_intr(otg_dev
->core_if
);
559 return IRQ_RETVAL(retval
);
563 * This function is called when a lm_device is unregistered with the
564 * dwc_otg_driver. This happens, for example, when the rmmod command is
565 * executed. The device may or may not be electrically present. If it is
566 * present, the driver stops device processing. Any resources used on behalf
567 * of this device are freed.
571 static int dwc_otg_driver_cleanup(struct platform_device
*pdev
)
573 dwc_otg_device_t
*otg_dev
= platform_get_drvdata(pdev
);
574 DWC_DEBUGPL(DBG_ANY
, "%s(%p)\n", __func__
, pdev
);
577 /* Memory allocation for the dwc_otg_device failed. */
578 DWC_DEBUGPL(DBG_ANY
, "%s: otg_dev NULL!\n", __func__
);
585 if (otg_dev
->common_irq_installed
) {
586 free_irq(otg_dev
->irq
, otg_dev
);
589 #ifndef DWC_DEVICE_ONLY
591 dwc_otg_hcd_remove(pdev
);
593 DWC_DEBUGPL(DBG_ANY
, "%s: otg_dev->hcd NULL!\n", __func__
);
598 #ifndef DWC_HOST_ONLY
600 dwc_otg_pcd_remove(pdev
);
603 if (otg_dev
->core_if
) {
604 dwc_otg_cil_remove(otg_dev
->core_if
);
608 * Remove the device attributes
610 dwc_otg_attr_remove(pdev
);
616 iounmap(otg_dev
->base
);
621 * Clear the drvdata pointer.
623 platform_set_drvdata(pdev
, 0);
629 * This function is called when an lm_device is bound to a
630 * dwc_otg_driver. It creates the driver components required to
631 * control the device (CIL, HCD, and PCD) and it initializes the
632 * device. The driver components are stored in a dwc_otg_device
633 * structure. A reference to the dwc_otg_device is saved in the
634 * lm_device. This allows the driver to access the dwc_otg_device
635 * structure on subsequent calls to driver methods for this device.
637 * @param[in] lmdev lm_device definition
639 static int __devinit
dwc_otg_driver_probe(struct platform_device
*pdev
)
641 struct device
*dev
= &pdev
->dev
;
644 dwc_otg_device_t
*dwc_otg_device
;
645 struct resource
*res
;
647 dev_dbg(dev
, "dwc_otg_driver_probe(%p)\n", pdev
);
649 dwc_otg_device
= kmalloc(sizeof(dwc_otg_device_t
), GFP_KERNEL
);
651 if (!dwc_otg_device
) {
652 dev_err(dev
, "kmalloc of dwc_otg_device failed\n");
657 memset(dwc_otg_device
, 0, sizeof(*dwc_otg_device
));
658 dwc_otg_device
->reg_offset
= 0xFFFFFFFF;
660 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
662 dev_err(dev
, "Found OTG with no register addr.\n");
666 dwc_otg_device
->rsrc_start
= res
->start
;
667 dwc_otg_device
->rsrc_len
= res
->end
- res
->start
+ 1;
669 dwc_otg_device
->base
= ioremap(dwc_otg_device
->rsrc_start
, dwc_otg_device
->rsrc_len
);
671 if (!dwc_otg_device
->base
) {
672 dev_err(dev
, "ioremap() failed\n");
676 dev_dbg(dev
, "base=0x%08x\n", (unsigned)dwc_otg_device
->base
);
679 * Attempt to ensure this device is really a DWC_otg Controller.
680 * Read and verify the SNPSID register contents. The value should be
681 * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
683 snpsid
= dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device
->base
+ 0x40));
685 if ((snpsid
& 0xFFFFF000) != OTG_CORE_REV_2_00
) {
686 dev_err(dev
, "Bad value for SNPSID: 0x%08x\n", snpsid
);
691 DWC_PRINT("Core Release: %x.%x%x%x\n",
692 (snpsid
>> 12 & 0xF),
698 * Initialize driver data to point to the global DWC_otg
701 platform_set_drvdata(pdev
, dwc_otg_device
);
703 dev_dbg(dev
, "dwc_otg_device=0x%p\n", dwc_otg_device
);
705 dwc_otg_device
->core_if
= dwc_otg_cil_init(dwc_otg_device
->base
,
706 &dwc_otg_module_params
);
708 dwc_otg_device
->core_if
->snpsid
= snpsid
;
710 if (!dwc_otg_device
->core_if
) {
711 dev_err(dev
, "CIL initialization failed!\n");
717 * Validate parameter values.
719 if (check_parameters(dwc_otg_device
->core_if
)) {
725 * Create Device Attributes in sysfs
727 dwc_otg_attr_create(pdev
);
730 * Disable the global interrupt until all the interrupt
731 * handlers are installed.
733 dwc_otg_disable_global_interrupts(dwc_otg_device
->core_if
);
736 * Install the interrupt handler for the common interrupts before
737 * enabling common interrupts in core_init below.
739 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
741 dev_err(dev
, "Fount OTG with to IRQ.\n");
745 dwc_otg_device
->irq
= res
->start
;
747 retval
= request_irq(res
->start
, dwc_otg_common_irq
,
748 IRQF_SHARED
, "dwc_otg", dwc_otg_device
);
750 DWC_ERROR("request of irq%d failed\n", res
->start
);
754 dwc_otg_device
->common_irq_installed
= 1;
758 * Initialize the DWC_otg core.
760 dwc_otg_core_init(dwc_otg_device
->core_if
);
762 #ifndef DWC_HOST_ONLY
766 retval
= dwc_otg_pcd_init(pdev
);
768 DWC_ERROR("dwc_otg_pcd_init failed\n");
769 dwc_otg_device
->pcd
= NULL
;
773 #ifndef DWC_DEVICE_ONLY
777 retval
= dwc_otg_hcd_init(pdev
);
779 DWC_ERROR("dwc_otg_hcd_init failed\n");
780 dwc_otg_device
->hcd
= NULL
;
786 * Enable the global interrupt after all the interrupt
787 * handlers are installed.
789 dwc_otg_enable_global_interrupts(dwc_otg_device
->core_if
);
794 dwc_otg_driver_cleanup(pdev
);
798 static int __devexit
dwc_otg_driver_remove(struct platform_device
*pdev
)
800 return dwc_otg_driver_cleanup(pdev
);
803 static struct platform_driver dwc_otg_platform_driver
= {
804 .driver
.name
= "dwc_otg",
805 .probe
= dwc_otg_driver_probe
,
806 .remove
= __devexit_p(dwc_otg_driver_remove
),
809 static int __init
dwc_otg_init_module(void)
811 return platform_driver_register(&dwc_otg_platform_driver
);
814 static void __exit
dwc_otg_cleanup_module(void)
816 platform_driver_unregister(&dwc_otg_platform_driver
);
819 module_init(dwc_otg_init_module
);
820 module_exit(dwc_otg_cleanup_module
);
823 * This function is called when the driver is removed from the kernel
824 * with the rmmod command. The driver unregisters itself with its bus
829 MODULE_DESCRIPTION(DWC_DRIVER_DESC
);
830 MODULE_AUTHOR("Synopsys Inc.");
831 MODULE_LICENSE("GPL");
833 module_param_named(otg_cap
, dwc_otg_module_params
.otg_cap
, int, 0444);
834 MODULE_PARM_DESC(otg_cap
, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
835 module_param_named(opt
, dwc_otg_module_params
.opt
, int, 0444);
836 MODULE_PARM_DESC(opt
, "OPT Mode");
837 module_param_named(dma_enable
, dwc_otg_module_params
.dma_enable
, int, 0444);
838 MODULE_PARM_DESC(dma_enable
, "DMA Mode 0=Slave 1=DMA enabled");
840 module_param_named(dma_desc_enable
, dwc_otg_module_params
.dma_desc_enable
, int, 0444);
841 MODULE_PARM_DESC(dma_desc_enable
, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
843 module_param_named(dma_burst_size
, dwc_otg_module_params
.dma_burst_size
, int, 0444);
844 MODULE_PARM_DESC(dma_burst_size
, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
845 module_param_named(speed
, dwc_otg_module_params
.speed
, int, 0444);
846 MODULE_PARM_DESC(speed
, "Speed 0=High Speed 1=Full Speed");
847 module_param_named(host_support_fs_ls_low_power
, dwc_otg_module_params
.host_support_fs_ls_low_power
, int, 0444);
848 MODULE_PARM_DESC(host_support_fs_ls_low_power
, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
849 module_param_named(host_ls_low_power_phy_clk
, dwc_otg_module_params
.host_ls_low_power_phy_clk
, int, 0444);
850 MODULE_PARM_DESC(host_ls_low_power_phy_clk
, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
851 module_param_named(enable_dynamic_fifo
, dwc_otg_module_params
.enable_dynamic_fifo
, int, 0444);
852 MODULE_PARM_DESC(enable_dynamic_fifo
, "0=cC Setting 1=Allow Dynamic Sizing");
853 module_param_named(data_fifo_size
, dwc_otg_module_params
.data_fifo_size
, int, 0444);
854 MODULE_PARM_DESC(data_fifo_size
, "Total number of words in the data FIFO memory 32-32768");
855 module_param_named(dev_rx_fifo_size
, dwc_otg_module_params
.dev_rx_fifo_size
, int, 0444);
856 MODULE_PARM_DESC(dev_rx_fifo_size
, "Number of words in the Rx FIFO 16-32768");
857 module_param_named(dev_nperio_tx_fifo_size
, dwc_otg_module_params
.dev_nperio_tx_fifo_size
, int, 0444);
858 MODULE_PARM_DESC(dev_nperio_tx_fifo_size
, "Number of words in the non-periodic Tx FIFO 16-32768");
859 module_param_named(dev_perio_tx_fifo_size_1
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[0], int, 0444);
860 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1
, "Number of words in the periodic Tx FIFO 4-768");
861 module_param_named(dev_perio_tx_fifo_size_2
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[1], int, 0444);
862 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2
, "Number of words in the periodic Tx FIFO 4-768");
863 module_param_named(dev_perio_tx_fifo_size_3
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[2], int, 0444);
864 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3
, "Number of words in the periodic Tx FIFO 4-768");
865 module_param_named(dev_perio_tx_fifo_size_4
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[3], int, 0444);
866 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4
, "Number of words in the periodic Tx FIFO 4-768");
867 module_param_named(dev_perio_tx_fifo_size_5
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[4], int, 0444);
868 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5
, "Number of words in the periodic Tx FIFO 4-768");
869 module_param_named(dev_perio_tx_fifo_size_6
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[5], int, 0444);
870 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6
, "Number of words in the periodic Tx FIFO 4-768");
871 module_param_named(dev_perio_tx_fifo_size_7
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[6], int, 0444);
872 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7
, "Number of words in the periodic Tx FIFO 4-768");
873 module_param_named(dev_perio_tx_fifo_size_8
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[7], int, 0444);
874 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8
, "Number of words in the periodic Tx FIFO 4-768");
875 module_param_named(dev_perio_tx_fifo_size_9
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[8], int, 0444);
876 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9
, "Number of words in the periodic Tx FIFO 4-768");
877 module_param_named(dev_perio_tx_fifo_size_10
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[9], int, 0444);
878 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10
, "Number of words in the periodic Tx FIFO 4-768");
879 module_param_named(dev_perio_tx_fifo_size_11
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[10], int, 0444);
880 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11
, "Number of words in the periodic Tx FIFO 4-768");
881 module_param_named(dev_perio_tx_fifo_size_12
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[11], int, 0444);
882 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12
, "Number of words in the periodic Tx FIFO 4-768");
883 module_param_named(dev_perio_tx_fifo_size_13
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[12], int, 0444);
884 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13
, "Number of words in the periodic Tx FIFO 4-768");
885 module_param_named(dev_perio_tx_fifo_size_14
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[13], int, 0444);
886 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14
, "Number of words in the periodic Tx FIFO 4-768");
887 module_param_named(dev_perio_tx_fifo_size_15
, dwc_otg_module_params
.dev_perio_tx_fifo_size
[14], int, 0444);
888 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15
, "Number of words in the periodic Tx FIFO 4-768");
889 module_param_named(host_rx_fifo_size
, dwc_otg_module_params
.host_rx_fifo_size
, int, 0444);
890 MODULE_PARM_DESC(host_rx_fifo_size
, "Number of words in the Rx FIFO 16-32768");
891 module_param_named(host_nperio_tx_fifo_size
, dwc_otg_module_params
.host_nperio_tx_fifo_size
, int, 0444);
892 MODULE_PARM_DESC(host_nperio_tx_fifo_size
, "Number of words in the non-periodic Tx FIFO 16-32768");
893 module_param_named(host_perio_tx_fifo_size
, dwc_otg_module_params
.host_perio_tx_fifo_size
, int, 0444);
894 MODULE_PARM_DESC(host_perio_tx_fifo_size
, "Number of words in the host periodic Tx FIFO 16-32768");
895 module_param_named(max_transfer_size
, dwc_otg_module_params
.max_transfer_size
, int, 0444);
896 /** @todo Set the max to 512K, modify checks */
897 MODULE_PARM_DESC(max_transfer_size
, "The maximum transfer size supported in bytes 2047-65535");
898 module_param_named(max_packet_count
, dwc_otg_module_params
.max_packet_count
, int, 0444);
899 MODULE_PARM_DESC(max_packet_count
, "The maximum number of packets in a transfer 15-511");
900 module_param_named(host_channels
, dwc_otg_module_params
.host_channels
, int, 0444);
901 MODULE_PARM_DESC(host_channels
, "The number of host channel registers to use 1-16");
902 module_param_named(dev_endpoints
, dwc_otg_module_params
.dev_endpoints
, int, 0444);
903 MODULE_PARM_DESC(dev_endpoints
, "The number of endpoints in addition to EP0 available for device mode 1-15");
904 module_param_named(phy_type
, dwc_otg_module_params
.phy_type
, int, 0444);
905 MODULE_PARM_DESC(phy_type
, "0=Reserved 1=UTMI+ 2=ULPI");
906 module_param_named(phy_utmi_width
, dwc_otg_module_params
.phy_utmi_width
, int, 0444);
907 MODULE_PARM_DESC(phy_utmi_width
, "Specifies the UTMI+ Data Width 8 or 16 bits");
908 module_param_named(phy_ulpi_ddr
, dwc_otg_module_params
.phy_ulpi_ddr
, int, 0444);
909 MODULE_PARM_DESC(phy_ulpi_ddr
, "ULPI at double or single data rate 0=Single 1=Double");
910 module_param_named(phy_ulpi_ext_vbus
, dwc_otg_module_params
.phy_ulpi_ext_vbus
, int, 0444);
911 MODULE_PARM_DESC(phy_ulpi_ext_vbus
, "ULPI PHY using internal or external vbus 0=Internal");
912 module_param_named(i2c_enable
, dwc_otg_module_params
.i2c_enable
, int, 0444);
913 MODULE_PARM_DESC(i2c_enable
, "FS PHY Interface");
914 module_param_named(ulpi_fs_ls
, dwc_otg_module_params
.ulpi_fs_ls
, int, 0444);
915 MODULE_PARM_DESC(ulpi_fs_ls
, "ULPI PHY FS/LS mode only");
916 module_param_named(ts_dline
, dwc_otg_module_params
.ts_dline
, int, 0444);
917 MODULE_PARM_DESC(ts_dline
, "Term select Dline pulsing for all PHYs");
918 module_param_named(debug
, g_dbg_lvl
, int, 0444);
919 MODULE_PARM_DESC(debug
, "");
921 module_param_named(en_multiple_tx_fifo
, dwc_otg_module_params
.en_multiple_tx_fifo
, int, 0444);
922 MODULE_PARM_DESC(en_multiple_tx_fifo
, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
923 module_param_named(dev_tx_fifo_size_1
, dwc_otg_module_params
.dev_tx_fifo_size
[0], int, 0444);
924 MODULE_PARM_DESC(dev_tx_fifo_size_1
, "Number of words in the Tx FIFO 4-768");
925 module_param_named(dev_tx_fifo_size_2
, dwc_otg_module_params
.dev_tx_fifo_size
[1], int, 0444);
926 MODULE_PARM_DESC(dev_tx_fifo_size_2
, "Number of words in the Tx FIFO 4-768");
927 module_param_named(dev_tx_fifo_size_3
, dwc_otg_module_params
.dev_tx_fifo_size
[2], int, 0444);
928 MODULE_PARM_DESC(dev_tx_fifo_size_3
, "Number of words in the Tx FIFO 4-768");
929 module_param_named(dev_tx_fifo_size_4
, dwc_otg_module_params
.dev_tx_fifo_size
[3], int, 0444);
930 MODULE_PARM_DESC(dev_tx_fifo_size_4
, "Number of words in the Tx FIFO 4-768");
931 module_param_named(dev_tx_fifo_size_5
, dwc_otg_module_params
.dev_tx_fifo_size
[4], int, 0444);
932 MODULE_PARM_DESC(dev_tx_fifo_size_5
, "Number of words in the Tx FIFO 4-768");
933 module_param_named(dev_tx_fifo_size_6
, dwc_otg_module_params
.dev_tx_fifo_size
[5], int, 0444);
934 MODULE_PARM_DESC(dev_tx_fifo_size_6
, "Number of words in the Tx FIFO 4-768");
935 module_param_named(dev_tx_fifo_size_7
, dwc_otg_module_params
.dev_tx_fifo_size
[6], int, 0444);
936 MODULE_PARM_DESC(dev_tx_fifo_size_7
, "Number of words in the Tx FIFO 4-768");
937 module_param_named(dev_tx_fifo_size_8
, dwc_otg_module_params
.dev_tx_fifo_size
[7], int, 0444);
938 MODULE_PARM_DESC(dev_tx_fifo_size_8
, "Number of words in the Tx FIFO 4-768");
939 module_param_named(dev_tx_fifo_size_9
, dwc_otg_module_params
.dev_tx_fifo_size
[8], int, 0444);
940 MODULE_PARM_DESC(dev_tx_fifo_size_9
, "Number of words in the Tx FIFO 4-768");
941 module_param_named(dev_tx_fifo_size_10
, dwc_otg_module_params
.dev_tx_fifo_size
[9], int, 0444);
942 MODULE_PARM_DESC(dev_tx_fifo_size_10
, "Number of words in the Tx FIFO 4-768");
943 module_param_named(dev_tx_fifo_size_11
, dwc_otg_module_params
.dev_tx_fifo_size
[10], int, 0444);
944 MODULE_PARM_DESC(dev_tx_fifo_size_11
, "Number of words in the Tx FIFO 4-768");
945 module_param_named(dev_tx_fifo_size_12
, dwc_otg_module_params
.dev_tx_fifo_size
[11], int, 0444);
946 MODULE_PARM_DESC(dev_tx_fifo_size_12
, "Number of words in the Tx FIFO 4-768");
947 module_param_named(dev_tx_fifo_size_13
, dwc_otg_module_params
.dev_tx_fifo_size
[12], int, 0444);
948 MODULE_PARM_DESC(dev_tx_fifo_size_13
, "Number of words in the Tx FIFO 4-768");
949 module_param_named(dev_tx_fifo_size_14
, dwc_otg_module_params
.dev_tx_fifo_size
[13], int, 0444);
950 MODULE_PARM_DESC(dev_tx_fifo_size_14
, "Number of words in the Tx FIFO 4-768");
951 module_param_named(dev_tx_fifo_size_15
, dwc_otg_module_params
.dev_tx_fifo_size
[14], int, 0444);
952 MODULE_PARM_DESC(dev_tx_fifo_size_15
, "Number of words in the Tx FIFO 4-768");
954 module_param_named(thr_ctl
, dwc_otg_module_params
.thr_ctl
, int, 0444);
955 MODULE_PARM_DESC(thr_ctl
, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
956 module_param_named(tx_thr_length
, dwc_otg_module_params
.tx_thr_length
, int, 0444);
957 MODULE_PARM_DESC(tx_thr_length
, "Tx Threshold length in 32 bit DWORDs");
958 module_param_named(rx_thr_length
, dwc_otg_module_params
.rx_thr_length
, int, 0444);
959 MODULE_PARM_DESC(rx_thr_length
, "Rx Threshold length in 32 bit DWORDs");
961 module_param_named(pti_enable
, dwc_otg_module_params
.pti_enable
, int, 0444);
962 MODULE_PARM_DESC(pti_enable
, "Per Transfer Interrupt mode 0=disabled 1=enabled");
964 module_param_named(mpi_enable
, dwc_otg_module_params
.mpi_enable
, int, 0444);
965 MODULE_PARM_DESC(mpi_enable
, "Multiprocessor Interrupt mode 0=disabled 1=enabled");