target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
   3  * $Revision: #63 $
   4  * $Date: 2008/09/24 $
   5  * $Change: 1101777 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  * The dwc_otg_driver module provides the initialization and cleanup entry
  36  * points for the DWC_otg driver. This module will be dynamically installed
  37  * after Linux is booted using the insmod command. When the module is
  38  * installed, the dwc_otg_driver_init function is called. When the module is
  39  * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
  40  *
  41  * This module also defines a data structure for the dwc_otg_driver, which is
  42  * used in conjunction with the standard ARM lm_device structure. These
  43  * structures allow the OTG driver to comply with the standard Linux driver
  44  * model in which devices and drivers are registered with a bus driver. This
  45  * has the benefit that Linux can expose attributes of the driver and device
  46  * in its special sysfs file system. Users can then read or write files in
  47  * this file system to perform diagnostics on the driver components or the
  48  * device.
  49  */
  50
  51 #include <linux/kernel.h>
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/init.h>
  55 #include <linux/device.h>
  56 #include <linux/errno.h>
  57 #include <linux/types.h>
  58 #include <linux/stat.h>  /* permission constants */
  59 #include <linux/version.h>
  60 #include <linux/platform_device.h>
  61 #include <linux/io.h>
  62 #include <linux/irq.h>
  63 #include <asm/io.h>
  64
  65 #include <asm/sizes.h>
  66
  67 #include "otg_plat.h"
  68 #include "otg_attr.h"
  69 #include "otg_driver.h"
  70 #include "otg_cil.h"
  71 #include "otg_pcd.h"
  72 #include "otg_hcd.h"
  73
  74 #define DWC_DRIVER_VERSION      "2.72a 24-JUN-2008"
  75 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
  76
  77 static const char dwc_driver_name[] = "dwc_otg";
  78
  79 /*-------------------------------------------------------------------------*/
  80 /* Encapsulate the module parameter settings */
  81
  82 static dwc_otg_core_params_t dwc_otg_module_params = {
  83         .opt = -1,
  84         .otg_cap = -1,
  85         .dma_enable = -1,
  86         .dma_desc_enable = -1,
  87         .dma_burst_size = -1,
  88         .speed = -1,
  89         .host_support_fs_ls_low_power = -1,
  90         .host_ls_low_power_phy_clk = -1,
  91         .enable_dynamic_fifo = -1,
  92         .data_fifo_size = -1,
  93         .dev_rx_fifo_size = -1,
  94         .dev_nperio_tx_fifo_size = -1,
  95         .dev_perio_tx_fifo_size = {
  96                 /* dev_perio_tx_fifo_size_1 */
  97                 -1,
  98                 -1,
  99                 -1,
 100                 -1,
 101                 -1,
 102                 -1,
 103                 -1,
 104                 -1,
 105                 -1,
 106                 -1,
 107                 -1,
 108                 -1,
 109                 -1,
 110                 -1,
 111                 -1
 112                 /* 15 */
 113         },
 114         .host_rx_fifo_size = -1,
 115         .host_nperio_tx_fifo_size = -1,
 116         .host_perio_tx_fifo_size = -1,
 117         .max_transfer_size = -1,
 118         .max_packet_count = -1,
 119         .host_channels = -1,
 120         .dev_endpoints = -1,
 121         .phy_type = -1,
 122         .phy_utmi_width = -1,
 123         .phy_ulpi_ddr = -1,
 124         .phy_ulpi_ext_vbus = -1,
 125         .i2c_enable = -1,
 126         .ulpi_fs_ls = -1,
 127         .ts_dline = -1,
 128         .en_multiple_tx_fifo = -1,
 129         .dev_tx_fifo_size = {
 130                 /* dev_tx_fifo_size */
 131                 -1,
 132                 -1,
 133                 -1,
 134                 -1,
 135                 -1,
 136                 -1,
 137                 -1,
 138                 -1,
 139                 -1,
 140                 -1,
 141                 -1,
 142                 -1,
 143                 -1,
 144                 -1,
 145                 -1
 146                 /* 15 */
 147         },
 148         .thr_ctl = -1,
 149         .tx_thr_length = -1,
 150         .rx_thr_length = -1,
 151         .pti_enable = -1,
 152         .mpi_enable = -1,
 153 };
 154
 155 /**
 156  * Global Debug Level Mask.
 157  */
 158 uint32_t g_dbg_lvl = 0; /* OFF */
 159
 160 /**
 161  * This function is called during module intialization to verify that
 162  * the module parameters are in a valid state.
 163  */
 164 static int check_parameters(dwc_otg_core_if_t *core_if)
 165 {
 166         int i;
 167         int retval = 0;
 168
 169 /* Checks if the parameter is outside of its valid range of values */
 170 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
 171                 ((dwc_otg_module_params._param_ < (_low_)) || \
 172                 (dwc_otg_module_params._param_ > (_high_)))
 173
 174 /* If the parameter has been set by the user, check that the parameter value is
 175  * within the value range of values.  If not, report a module error. */
 176 #define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
 177                 do { \
 178                         if (dwc_otg_module_params._param_ != -1) { \
 179                                 if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
 180                                         DWC_ERROR("`%d' invalid for parameter `%s'\n", \
 181                                                   dwc_otg_module_params._param_, _string_); \
 182                                         dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
 183                                         retval++; \
 184                                 } \
 185                         } \
 186                 } while (0)
 187
 188         DWC_OTG_PARAM_ERR(opt,0,1,"opt");
 189         DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
 190         DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
 191         DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
 192         DWC_OTG_PARAM_ERR(speed,0,1,"speed");
 193         DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
 194         DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
 195         DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
 196         DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
 197         DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
 198         DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
 199         DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
 200         DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
 201         DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
 202         DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
 203         DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
 204         DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
 205         DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
 206         DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
 207         DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
 208         DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
 209         DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
 210         DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
 211         DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
 212
 213         if (dwc_otg_module_params.dma_burst_size != -1) {
 214                 if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
 215                     DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
 216                     DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
 217                     DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
 218                     DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
 219                     DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
 220                     DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
 221                     DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
 222                         DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
 223                                   dwc_otg_module_params.dma_burst_size);
 224                         dwc_otg_module_params.dma_burst_size = 32;
 225                         retval++;
 226                 }
 227
 228                 {
 229                         uint8_t brst_sz = 0;
 230                         while(dwc_otg_module_params.dma_burst_size > 1) {
 231                                 brst_sz ++;
 232                                 dwc_otg_module_params.dma_burst_size >>= 1;
 233                         }
 234                         dwc_otg_module_params.dma_burst_size = brst_sz;
 235                 }
 236         }
 237
 238         if (dwc_otg_module_params.phy_utmi_width != -1) {
 239                 if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
 240                     DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
 241                         DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
 242                                   dwc_otg_module_params.phy_utmi_width);
 243                         dwc_otg_module_params.phy_utmi_width = 16;
 244                         retval++;
 245                 }
 246         }
 247
 248         for (i = 0; i < 15; i++) {
 249                 /** @todo should be like above */
 250                 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
 251                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
 252                         if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
 253                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 254                                           dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
 255                                 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 256                                 retval++;
 257                         }
 258                 }
 259         }
 260
 261         DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
 262
 263         for (i = 0; i < 15; i++) {
 264                 /** @todo should be like above */
 265                 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
 266                 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
 267                         if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
 268                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 269                                           dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
 270                                 dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 271                                 retval++;
 272                         }
 273                 }
 274         }
 275
 276         DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
 277         DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
 278         DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
 279
 280         DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
 281         DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
 282
 283         /* At this point, all module parameters that have been set by the user
 284          * are valid, and those that have not are left unset.  Now set their
 285          * default values and/or check the parameters against the hardware
 286          * configurations of the OTG core. */
 287
 288 /* This sets the parameter to the default value if it has not been set by the
 289  * user */
 290 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
 291         ({ \
 292                 int changed = 1; \
 293                 if (dwc_otg_module_params._param_ == -1) { \
 294                         changed = 0; \
 295                         dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
 296                 } \
 297                 changed; \
 298         })
 299
 300 /* This checks the macro agains the hardware configuration to see if it is
 301  * valid.  It is possible that the default value could be invalid. In this
 302  * case, it will report a module error if the user touched the parameter.
 303  * Otherwise it will adjust the value without any error. */
 304 #define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
 305         ({ \
 306                 int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
 307                 int error = 0; \
 308                 if (!(_is_valid_)) { \
 309                         if (changed) { \
 310                                 DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
 311                                 error = 1; \
 312                         } \
 313                         dwc_otg_module_params._param_ = (_set_valid_); \
 314                 } \
 315                 error; \
 316         })
 317
 318         /* OTG Cap */
 319         retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
 320                                 ({
 321                                         int valid;
 322                                         valid = 1;
 323                                         switch (dwc_otg_module_params.otg_cap) {
 324                                         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
 325                                                 if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
 326                                                         valid = 0;
 327                                                 break;
 328                                         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
 329                                                 if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
 330                                                     (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
 331                                                     (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
 332                                                     (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
 333                                                         valid = 0;
 334                                                 }
 335                                                 break;
 336                                         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 337                                                 /* always valid */
 338                                                 break;
 339                                         }
 340                                         valid;
 341                                 }),
 342                                 (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
 343                                   (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
 344                                   (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 345                                   (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
 346                                  DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
 347                                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
 348
 349         retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
 350                                 ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
 351                                 0);
 352
 353         retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
 354                                 ((dwc_otg_module_params.dma_desc_enable == 1) &&
 355                                  ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
 356                                 0);
 357
 358         retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
 359
 360         DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
 361
 362         retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
 363                                 "host_support_fs_ls_low_power",
 364                                 1, 0);
 365
 366         retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
 367                                         "enable_dynamic_fifo",
 368                                         ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
 369                                         (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
 370
 371         retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
 372                                         "data_fifo_size",
 373                                         (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
 374                                         core_if->hwcfg3.b.dfifo_depth);
 375
 376         retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
 377                                         "dev_rx_fifo_size",
 378                                         (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 379                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 380
 381         retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
 382                                         "dev_nperio_tx_fifo_size",
 383                                         (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 384                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 385
 386         retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
 387                                         "host_rx_fifo_size",
 388                                         (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 389                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 390
 391         retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
 392                                         "host_nperio_tx_fifo_size",
 393                                         (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 394                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 395
 396         retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
 397                                         "host_perio_tx_fifo_size",
 398                                         (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
 399                                         ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
 400
 401         retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
 402                                         "max_transfer_size",
 403                                         (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
 404                                         ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
 405
 406         retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
 407                                         "max_packet_count",
 408                                         (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
 409                                         ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
 410
 411         retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
 412                                         "host_channels",
 413                                         (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
 414                                         (core_if->hwcfg2.b.num_host_chan + 1));
 415
 416         retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
 417                                         "dev_endpoints",
 418                                         (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
 419                                         core_if->hwcfg2.b.num_dev_ep);
 420
 421 /*
 422  * Define the following to disable the FS PHY Hardware checking.  This is for
 423  * internal testing only.
 424  *
 425  * #define NO_FS_PHY_HW_CHECKS
 426  */
 427
 428 #ifdef NO_FS_PHY_HW_CHECKS
 429         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 430                                 "phy_type", 1, 0);
 431 #else
 432         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 433                                 "phy_type",
 434                                 ({
 435                                         int valid = 0;
 436                                         if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
 437                                         ((core_if->hwcfg2.b.hs_phy_type == 1) ||
 438                                          (core_if->hwcfg2.b.hs_phy_type == 3))) {
 439                                                 valid = 1;
 440                                         }
 441                                         else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
 442                                                  ((core_if->hwcfg2.b.hs_phy_type == 2) ||
 443                                                   (core_if->hwcfg2.b.hs_phy_type == 3))) {
 444                                                 valid = 1;
 445                                         }
 446                                         else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
 447                                                  (core_if->hwcfg2.b.fs_phy_type == 1)) {
 448                                                 valid = 1;
 449                                         }
 450                                         valid;
 451                                 }),
 452                                 ({
 453                                         int set = DWC_PHY_TYPE_PARAM_FS;
 454                                         if (core_if->hwcfg2.b.hs_phy_type) {
 455                                                 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
 456                                                 (core_if->hwcfg2.b.hs_phy_type == 1)) {
 457                                                         set = DWC_PHY_TYPE_PARAM_UTMI;
 458                                                 }
 459                                                 else {
 460                                                         set = DWC_PHY_TYPE_PARAM_ULPI;
 461                                                 }
 462                                         }
 463                                         set;
 464                                 }));
 465 #endif
 466
 467         retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
 468                                 (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
 469                                 dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
 470
 471         retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
 472                                 "host_ls_low_power_phy_clk",
 473                                 ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
 474                                 ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
 475
 476         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
 477         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
 478         DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
 479         DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
 480         DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
 481
 482 #ifdef NO_FS_PHY_HW_CHECKS
 483         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
 484 #else
 485         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
 486                                 "i2c_enable",
 487                                 (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
 488                                 0);
 489 #endif
 490
 491         for (i = 0; i < 15; i++) {
 492                 int changed = 1;
 493                 int error = 0;
 494
 495                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
 496                         changed = 0;
 497                         dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 498                 }
 499                 if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
 500                         if (changed) {
 501                                 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
 502                                 error = 1;
 503                         }
 504                         dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
 505                 }
 506                 retval += error;
 507         }
 508
 509         retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
 510                                                 ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
 511                                                 0);
 512
 513         for (i = 0; i < 15; i++) {
 514                 int changed = 1;
 515                 int error = 0;
 516
 517                 if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
 518                         changed = 0;
 519                         dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 520                 }
 521                 if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
 522                         if (changed) {
 523                                 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
 524                                 error = 1;
 525                         }
 526                         dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
 527                 }
 528                 retval += error;
 529         }
 530
 531         retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
 532                                 ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
 533                                 0);
 534
 535         DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
 536         DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
 537
 538         retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
 539                 ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
 540                         0);
 541
 542         retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
 543                         ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
 544                         0);
 545         return retval;
 546 }
 547
 548 /**
 549  * This function is the top level interrupt handler for the Common
 550  * (Device and host modes) interrupts.
 551  */
 552 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
 553 {
 554         dwc_otg_device_t *otg_dev = dev;
 555         int32_t retval = IRQ_NONE;
 556
 557         retval = dwc_otg_handle_common_intr(otg_dev->core_if);
 558         return IRQ_RETVAL(retval);
 559 }
 560
 561 /**
 562  * This function is called when a lm_device is unregistered with the
 563  * dwc_otg_driver. This happens, for example, when the rmmod command is
 564  * executed. The device may or may not be electrically present. If it is
 565  * present, the driver stops device processing. Any resources used on behalf
 566  * of this device are freed.
 567  *
 568  * @param[in] lmdev
 569  */
 570 static int dwc_otg_driver_cleanup(struct platform_device *pdev)
 571 {
 572         dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
 573         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
 574
 575         if (!otg_dev) {
 576                 /* Memory allocation for the dwc_otg_device failed. */
 577                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
 578                 return 0;
 579         }
 580
 581         /*
 582          * Free the IRQ
 583          */
 584         if (otg_dev->common_irq_installed) {
 585                 free_irq(otg_dev->irq, otg_dev);
 586         }
 587
 588 #ifndef DWC_DEVICE_ONLY
 589         if (otg_dev->hcd) {
 590                 dwc_otg_hcd_remove(pdev);
 591         } else {
 592                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
 593                 return 0;
 594         }
 595 #endif
 596
 597 #ifndef DWC_HOST_ONLY
 598         if (otg_dev->pcd) {
 599                 dwc_otg_pcd_remove(pdev);
 600         }
 601 #endif
 602         if (otg_dev->core_if) {
 603                 dwc_otg_cil_remove(otg_dev->core_if);
 604         }
 605
 606         /*
 607          * Remove the device attributes
 608          */
 609         dwc_otg_attr_remove(pdev);
 610
 611         /*
 612          * Return the memory.
 613          */
 614         if (otg_dev->base) {
 615                 iounmap(otg_dev->base);
 616         }
 617         kfree(otg_dev);
 618
 619         /*
 620          * Clear the drvdata pointer.
 621          */
 622         platform_set_drvdata(pdev, 0);
 623
 624         return 0;
 625 }
 626
 627 /**
 628  * This function is called when an lm_device is bound to a
 629  * dwc_otg_driver. It creates the driver components required to
 630  * control the device (CIL, HCD, and PCD) and it initializes the
 631  * device. The driver components are stored in a dwc_otg_device
 632  * structure. A reference to the dwc_otg_device is saved in the
 633  * lm_device. This allows the driver to access the dwc_otg_device
 634  * structure on subsequent calls to driver methods for this device.
 635  *
 636  * @param[in] lmdev  lm_device definition
 637  */
 638 static int dwc_otg_driver_probe(struct platform_device *pdev)
 639 {
 640         struct device *dev = &pdev->dev;
 641         int retval = 0;
 642         uint32_t snpsid;
 643         dwc_otg_device_t *dwc_otg_device;
 644         struct resource *res;
 645
 646         dev_dbg(dev, "dwc_otg_driver_probe(%p)\n", pdev);
 647
 648         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
 649
 650         if (!dwc_otg_device) {
 651                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
 652                 retval = -ENOMEM;
 653                 goto fail;
 654         }
 655
 656         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
 657         dwc_otg_device->reg_offset = 0xFFFFFFFF;
 658
 659         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 660         if (!res) {
 661                 dev_err(dev, "Found OTG with no register addr.\n");
 662                 retval = -ENODEV;
 663                 goto fail;
 664         }
 665         dwc_otg_device->rsrc_start = res->start;
 666         dwc_otg_device->rsrc_len = res->end - res->start + 1;
 667
 668         dwc_otg_device->base = ioremap(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
 669
 670         if (!dwc_otg_device->base) {
 671                 dev_err(dev, "ioremap() failed\n");
 672                 retval = -ENOMEM;
 673                 goto fail;
 674         }
 675         dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
 676
 677         /*
 678          * Attempt to ensure this device is really a DWC_otg Controller.
 679          * Read and verify the SNPSID register contents. The value should be
 680          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
 681          */
 682         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
 683
 684         if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
 685                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
 686                 retval = -EINVAL;
 687                 goto fail;
 688         }
 689
 690         DWC_PRINT("Core Release: %x.%x%x%x\n",
 691                         (snpsid >> 12 & 0xF),
 692                         (snpsid >> 8 & 0xF),
 693                         (snpsid >> 4 & 0xF),
 694                         (snpsid & 0xF));
 695
 696         /*
 697          * Initialize driver data to point to the global DWC_otg
 698          * Device structure.
 699          */
 700         platform_set_drvdata(pdev, dwc_otg_device);
 701
 702         dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
 703
 704         dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base,
 705                                                    &dwc_otg_module_params);
 706
 707         dwc_otg_device->core_if->snpsid = snpsid;
 708
 709         if (!dwc_otg_device->core_if) {
 710                 dev_err(dev, "CIL initialization failed!\n");
 711                 retval = -ENOMEM;
 712                 goto fail;
 713         }
 714
 715         /*
 716          * Validate parameter values.
 717          */
 718         if (check_parameters(dwc_otg_device->core_if)) {
 719                 retval = -EINVAL;
 720                 goto fail;
 721         }
 722
 723         /*
 724          * Create Device Attributes in sysfs
 725          */
 726         dwc_otg_attr_create(pdev);
 727
 728         /*
 729          * Disable the global interrupt until all the interrupt
 730          * handlers are installed.
 731          */
 732         dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
 733
 734         /*
 735          * Install the interrupt handler for the common interrupts before
 736          * enabling common interrupts in core_init below.
 737          */
 738         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 739         if (!res) {
 740                 dev_err(dev, "Fount OTG with to IRQ.\n");
 741                 retval = -ENODEV;
 742                 goto fail;
 743         }
 744         dwc_otg_device->irq = res->start;
 745
 746         retval = request_irq(res->start, dwc_otg_common_irq,
 747                              IRQF_SHARED, "dwc_otg", dwc_otg_device);
 748         if (retval) {
 749                 DWC_ERROR("request of irq%d failed\n", res->start);
 750                 retval = -EBUSY;
 751                 goto fail;
 752         } else {
 753                 dwc_otg_device->common_irq_installed = 1;
 754         }
 755
 756         /*
 757          * Initialize the DWC_otg core.
 758          */
 759         dwc_otg_core_init(dwc_otg_device->core_if);
 760
 761 #ifndef DWC_HOST_ONLY
 762         /*
 763          * Initialize the PCD
 764          */
 765         retval = dwc_otg_pcd_init(pdev);
 766         if (retval != 0) {
 767                 DWC_ERROR("dwc_otg_pcd_init failed\n");
 768                 dwc_otg_device->pcd = NULL;
 769                 goto fail;
 770         }
 771 #endif
 772 #ifndef DWC_DEVICE_ONLY
 773         /*
 774          * Initialize the HCD
 775          */
 776         retval = dwc_otg_hcd_init(pdev);
 777         if (retval != 0) {
 778                 DWC_ERROR("dwc_otg_hcd_init failed\n");
 779                 dwc_otg_device->hcd = NULL;
 780                 goto fail;
 781         }
 782 #endif
 783
 784         /*
 785          * Enable the global interrupt after all the interrupt
 786          * handlers are installed.
 787          */
 788         dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
 789
 790         return 0;
 791
 792  fail:
 793         dwc_otg_driver_cleanup(pdev);
 794         return retval;
 795 }
 796
 797 static int dwc_otg_driver_remove(struct platform_device *pdev)
 798 {
 799         return dwc_otg_driver_cleanup(pdev);
 800 }
 801
 802 static struct platform_driver dwc_otg_platform_driver = {
 803         .driver.name = "dwc_otg",
 804         .probe = dwc_otg_driver_probe,
 805         .remove = dwc_otg_driver_remove,
 806 };
 807
 808 static int __init dwc_otg_init_module(void)
 809 {
 810         return platform_driver_register(&dwc_otg_platform_driver);
 811 }
 812
 813 static void __exit dwc_otg_cleanup_module(void)
 814 {
 815         platform_driver_unregister(&dwc_otg_platform_driver);
 816 }
 817
 818 module_init(dwc_otg_init_module);
 819 module_exit(dwc_otg_cleanup_module);
 820
 821 /**
 822  * This function is called when the driver is removed from the kernel
 823  * with the rmmod command. The driver unregisters itself with its bus
 824  * driver.
 825  *
 826  */
 827
 828 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
 829 MODULE_AUTHOR("Synopsys Inc.");
 830 MODULE_LICENSE("GPL");
 831
 832 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
 833 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
 834 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
 835 MODULE_PARM_DESC(opt, "OPT Mode");
 836 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
 837 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
 838
 839 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
 840 MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
 841
 842 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
 843 MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
 844 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
 845 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
 846 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
 847 MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
 848 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
 849 MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
 850 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
 851 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
 852 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
 853 MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
 854 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
 855 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
 856 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
 857 MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
 858 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
 859 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
 860 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
 861 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
 862 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
 863 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
 864 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
 865 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
 866 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
 867 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
 868 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
 869 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
 870 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
 871 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
 872 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
 873 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
 874 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
 875 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
 876 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
 877 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
 878 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
 879 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
 880 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
 881 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
 882 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
 883 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
 884 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
 885 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
 886 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
 887 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
 888 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
 889 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
 890 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
 891 MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
 892 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
 893 MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
 894 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
 895 /** @todo Set the max to 512K, modify checks */
 896 MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
 897 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
 898 MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
 899 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
 900 MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
 901 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
 902 MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
 903 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
 904 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
 905 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
 906 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
 907 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
 908 MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
 909 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
 910 MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
 911 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
 912 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
 913 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
 914 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
 915 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
 916 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
 917 module_param_named(debug, g_dbg_lvl, int, 0444);
 918 MODULE_PARM_DESC(debug, "");
 919
 920 module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
 921 MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
 922 module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
 923 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
 924 module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
 925 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
 926 module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
 927 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
 928 module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
 929 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
 930 module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
 931 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
 932 module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
 933 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
 934 module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
 935 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
 936 module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
 937 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
 938 module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
 939 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
 940 module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
 941 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
 942 module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
 943 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
 944 module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
 945 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
 946 module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
 947 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
 948 module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
 949 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
 950 module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
 951 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
 952
 953 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
 954 MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
 955 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
 956 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
 957 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
 958 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
 959
 960 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
 961 MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
 962
 963 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
 964 MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");