1 --- a/arch/arm/mm/cache-v6.S
2 +++ b/arch/arm/mm/cache-v6.S
3 @@ -179,6 +179,10 @@ ENTRY(v6_flush_kern_dcache_page)
4 * - end - virtual end address of region
6 ENTRY(v6_dma_inv_range)
11 tst r0, #D_CACHE_LINE_SIZE - 1
12 bic r0, r0, #D_CACHE_LINE_SIZE - 1
14 @@ -187,6 +191,10 @@ ENTRY(v6_dma_inv_range)
15 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
17 tst r1, #D_CACHE_LINE_SIZE - 1
19 + ldrneb r2, [r1, #-1]
20 + strneb r2, [r1, #-1]
22 bic r1, r1, #D_CACHE_LINE_SIZE - 1
24 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
25 @@ -201,6 +209,10 @@ ENTRY(v6_dma_inv_range)
27 add r0, r0, #D_CACHE_LINE_SIZE
35 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
36 @@ -214,6 +226,9 @@ ENTRY(v6_dma_inv_range)
37 ENTRY(v6_dma_clean_range)
38 bic r0, r0, #D_CACHE_LINE_SIZE - 1
44 mcr p15, 0, r0, c7, c10, 1 @ clean D line
46 @@ -232,6 +247,10 @@ ENTRY(v6_dma_clean_range)
47 * - end - virtual end address of region
49 ENTRY(v6_dma_flush_range)
54 bic r0, r0, #D_CACHE_LINE_SIZE - 1
57 @@ -241,6 +260,10 @@ ENTRY(v6_dma_flush_range)
59 add r0, r0, #D_CACHE_LINE_SIZE
67 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer