1 --- a/arch/arm/mach-cns3xxx/Makefile
2 +++ b/arch/arm/mach-cns3xxx/Makefile
4 -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
5 +obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o
6 obj-$(CONFIG_PCI) += pcie.o
7 obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
8 obj-$(CONFIG_MACH_GW2388) += laguna.o
9 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
10 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
11 @@ -199,7 +199,10 @@ static void __init cns3420_init(void)
16 + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
18 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
19 + NR_IRQS_CNS3XXX + 32);
20 cns3xxx_pcie_init(0x3);
22 pm_power_off = cns3xxx_power_off;
23 --- a/arch/arm/mach-cns3xxx/core.c
24 +++ b/arch/arm/mach-cns3xxx/core.c
26 #include <asm/hardware/gic.h>
27 #include <asm/smp_twd.h>
28 #include <asm/hardware/cache-l2x0.h>
29 -#include <asm/gpio.h>
30 #include <mach/cns3xxx.h>
33 @@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
37 -static inline void gpio_line_config(u8 line, u32 direction)
42 - reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
44 - __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
46 - reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
47 - reg |= (1 << (line - 32));
48 - __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
52 - reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
53 - reg &= ~(1 << line);
54 - __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
56 - reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
57 - reg &= ~(1 << (line - 32));
58 - __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
63 -static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
65 - gpio_line_config(gpio, CNS3XXX_GPIO_IN);
69 -static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
71 - gpio_line_set(gpio, level);
72 - gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
76 -static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
78 - return gpio_get_value(gpio);
81 -static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
83 - gpio_set_value(gpio, value);
86 -static struct gpio_chip cns3xxx_gpio_chip = {
87 - .label = "CNS3XXX_GPIO_CHIP",
88 - .direction_input = cns3xxx_gpio_direction_input,
89 - .direction_output = cns3xxx_gpio_direction_output,
90 - .get = cns3xxx_gpio_get_value,
91 - .set = cns3xxx_gpio_set_value,
96 void __init cns3xxx_common_init(void)
98 #ifdef CONFIG_LOCAL_TIMERS
99 twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
101 iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
103 - gpiochip_add(&cns3xxx_gpio_chip);
106 /* used by entry-macro.S */
108 +++ b/arch/arm/mach-cns3xxx/gpio.c
111 + * Copyright 2012 Gateworks Corporation
112 + * Chris Lang <clang@gateworks.com>
113 + * Tim Harvey <tharvey@gateworks.com>
115 + * This file is free software; you can redistribute it and/or modify
116 + * it under the terms of the GNU General Public License, Version 2, as
117 + * published by the Free Software Foundation.
120 +#include <linux/module.h>
121 +#include <linux/init.h>
122 +#include <linux/interrupt.h>
123 +#include <linux/io.h>
124 +#include <linux/gpio.h>
125 +#include <linux/irq.h>
127 +#include <asm/mach/irq.h>
132 +#define GPIO_INPUT 0x04
133 +#define GPIO_DIR 0x08
134 +#define GPIO_SET 0x10
135 +#define GPIO_CLEAR 0x14
136 +#define GPIO_INTERRUPT_ENABLE 0x20
137 +#define GPIO_INTERRUPT_RAW_STATUS 0x24
138 +#define GPIO_INTERRUPT_MASKED_STATUS 0x28
139 +#define GPIO_INTERRUPT_MASK 0x2C
140 +#define GPIO_INTERRUPT_CLEAR 0x30
141 +#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34
142 +#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38
143 +#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C
145 +#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0
146 +#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
147 +#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0
148 +#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1
149 +#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0
150 +#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
151 +#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0
152 +#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1
154 +struct cns3xxx_gpio_chip {
155 + struct gpio_chip chip;
157 + void __iomem *base;
158 + int secondary_irq_base;
161 +static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
162 +static int cns3xxx_gpio_chip_count;
165 +__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
169 + reg = __raw_readl(cchip->base + GPIO_DIR);
173 + reg &= !(1 << pin);
174 + __raw_writel(reg, cchip->base + GPIO_DIR);
178 + * GENERIC_GPIO primatives
180 +static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
182 + struct cns3xxx_gpio_chip *cchip =
183 + container_of(chip, struct cns3xxx_gpio_chip, chip);
184 + unsigned long flags;
186 + spin_lock_irqsave(&cchip->lock, flags);
187 + __set_direction(cchip, pin, 1);
188 + spin_unlock_irqrestore(&cchip->lock, flags);
193 +static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
195 + struct cns3xxx_gpio_chip *cchip =
196 + container_of(chip, struct cns3xxx_gpio_chip, chip);
199 + val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
204 +static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
206 + struct cns3xxx_gpio_chip *cchip =
207 + container_of(chip, struct cns3xxx_gpio_chip, chip);
208 + unsigned long flags;
210 + spin_lock_irqsave(&cchip->lock, flags);
212 + __raw_writel(1 << pin, cchip->base + GPIO_SET);
214 + __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
215 + __set_direction(cchip, pin, 0);
216 + spin_unlock_irqrestore(&cchip->lock, flags);
221 +static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
224 + struct cns3xxx_gpio_chip *cchip =
225 + container_of(chip, struct cns3xxx_gpio_chip, chip);
228 + __raw_writel(1 << pin, cchip->base + GPIO_SET);
230 + __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
233 +static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
235 + struct cns3xxx_gpio_chip *cchip =
236 + container_of(chip, struct cns3xxx_gpio_chip, chip);
238 + return cchip->secondary_irq_base + pin;
246 +/* one interrupt per GPIO controller (GPIOA/GPIOB)
247 + * this is called in task context, with IRQs enabled
249 +static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
251 + struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
252 + struct irq_chip *chip = irq_get_chip(irq);
253 + struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
254 + struct irq_chip_type *ct = gc->chip_types;
258 + chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
260 + /* see which pin(s) triggered the interrupt */
261 + reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
262 + for (i = 0; i < 32; i++) {
263 + if (reg & (1 << i)) {
264 + /* let the generic IRQ layer handle an interrupt */
265 + generic_handle_irq(cchip->secondary_irq_base + i);
269 + chained_irq_exit(chip, desc); /* unmask the base interrupt */
272 +static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
274 + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
275 + struct cns3xxx_gpio_chip *cchip = gc->private;
276 + u32 gpio = d->irq - cchip->secondary_irq_base;
277 + unsigned long flags;
278 + u32 method, edges, type;
280 + spin_lock_irqsave(&cchip->lock, flags);
281 + method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
282 + edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
283 + type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
284 + method &= ~(1 << gpio);
285 + edges &= ~(1 << gpio);
286 + type &= ~(1 << gpio);
289 + case IRQ_TYPE_EDGE_RISING:
290 + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
291 + edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
292 + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
294 + case IRQ_TYPE_EDGE_FALLING:
295 + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
296 + edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
297 + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
299 + case IRQ_TYPE_EDGE_BOTH:
300 + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
301 + edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
303 + case IRQ_TYPE_LEVEL_LOW:
304 + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
305 + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
307 + case IRQ_TYPE_LEVEL_HIGH:
308 + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
309 + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
312 + printk(KERN_WARNING "No irq type\n");
313 + spin_unlock_irqrestore(&cchip->lock, flags);
317 + __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
318 + __raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
319 + __raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
320 + spin_unlock_irqrestore(&cchip->lock, flags);
322 + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
323 + __irq_set_handler_locked(d->irq, handle_level_irq);
324 + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
325 + __irq_set_handler_locked(d->irq, handle_edge_irq);
330 +void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
331 + u32 base, int irq, int secondary_irq_base)
333 + struct cns3xxx_gpio_chip *cchip;
334 + struct irq_chip_generic *gc;
335 + struct irq_chip_type *ct;
338 + if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
341 + snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
342 + cns3xxx_gpio_chip_count);
344 + cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
345 + cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
346 + cchip->chip.direction_input = cns3xxx_gpio_direction_input;
347 + cchip->chip.get = cns3xxx_gpio_get;
348 + cchip->chip.direction_output = cns3xxx_gpio_direction_output;
349 + cchip->chip.set = cns3xxx_gpio_set;
350 + cchip->chip.to_irq = cns3xxx_gpio_to_irq;
351 + cchip->chip.base = gpio_base;
352 + cchip->chip.ngpio = ngpio;
353 + cchip->chip.can_sleep = 0;
354 + spin_lock_init(&cchip->lock);
355 + cchip->base = (void __iomem *)base;
356 + cchip->secondary_irq_base = secondary_irq_base;
358 + BUG_ON(gpiochip_add(&cchip->chip) < 0);
359 + cns3xxx_gpio_chip_count++;
361 + /* clear GPIO interrupts */
362 + __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
367 + gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, secondary_irq_base,
368 + cchip->base, handle_edge_irq);
369 + gc->private = cchip;
371 + ct = gc->chip_types;
372 + ct->type = IRQ_TYPE_EDGE_FALLING;
373 + ct->regs.ack = GPIO_INTERRUPT_CLEAR;
374 + ct->regs.enable = GPIO_INTERRUPT_ENABLE;
375 + ct->chip.irq_ack = irq_gc_ack_set_bit;
376 + ct->chip.irq_enable = irq_gc_unmask_enable_reg;
377 + ct->chip.irq_disable = irq_gc_mask_disable_reg;
378 + ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
379 + ct->handler = handle_edge_irq;
381 + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
384 + irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
385 + irq_set_handler_data(irq, cchip);
387 --- a/arch/arm/mach-cns3xxx/include/mach/gpio.h
388 +++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
391 * arch/arm/mach-cns3xxx/include/mach/gpio.h
393 - * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
395 - * Copyright 2011 Gateworks Corporation
396 - * Chris Lang <clang@gateworks.com>
398 - * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
399 - * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
401 - * This program is free software; you can redistribute it and/or modify
402 - * it under the terms of the GNU General Public License as published by
403 - * the Free Software Foundation; either version 2 of the License, or
404 - * (at your option) any later version.
406 - * This program is distributed in the hope that it will be useful,
407 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
408 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
409 - * GNU General Public License for more details.
411 - * You should have received a copy of the GNU General Public License
412 - * along with this program; if not, write to the Free Software
413 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
414 + * This file is licensed under the terms of the GNU General Public
415 + * License version 2. This program is licensed "as is" without any
416 + * warranty of any kind, whether express or implied.
420 #ifndef __ASM_ARCH_CNS3XXX_GPIO_H
421 #define __ASM_ARCH_CNS3XXX_GPIO_H
423 #include <linux/kernel.h>
424 -#include <linux/io.h>
425 -#include <mach/platform.h>
426 -#include <asm-generic/gpio.h> /* cansleep wrappers */
428 -#define NR_BUILTIN_GPIO 64
430 -#define CNS3XXX_GPIO_IN 0x0
431 -#define CNS3XXX_GPIO_OUT 0x1
433 -#define CNS3XXX_GPIO_LO 0
434 -#define CNS3XXX_GPIO_HI 1
436 -#define CNS3XXX_GPIO_OUTPUT 0x00
437 -#define CNS3XXX_GPIO_INPUT 0x04
438 -#define CNS3XXX_GPIO_DIR 0x08
439 -#define CNS3XXX_GPIO_SET 0x10
440 -#define CNS3XXX_GPIO_CLEAR 0x14
442 -static inline void gpio_line_get(u8 line, int *value)
445 - *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
447 - *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
450 -static inline void gpio_line_set(u8 line, int value)
454 - __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
456 - __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
459 - __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
461 - __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
465 -static inline int gpio_get_value(unsigned gpio)
467 - if (gpio < NR_BUILTIN_GPIO)
470 - gpio_line_get(gpio, &value);
474 - return __gpio_get_value(gpio);
477 -static inline void gpio_set_value(unsigned gpio, int value)
479 - if (gpio < NR_BUILTIN_GPIO)
480 - gpio_line_set(gpio, value);
482 - __gpio_set_value(gpio, value);
485 -#define gpio_cansleep __gpio_cansleep
487 -extern int gpio_to_irq(int gpio);
488 -extern int irq_to_gpio(int gpio);
489 +extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
490 + u32 base, int irq, int secondary_irq_base);
493 --- a/arch/arm/mach-cns3xxx/laguna.c
494 +++ b/arch/arm/mach-cns3xxx/laguna.c
496 #include <mach/irqs.h>
497 #include <mach/platform.h>
499 +#include <mach/gpio.h>
500 #include <asm/hardware/gic.h>
503 @@ -760,6 +761,10 @@ static int __init laguna_model_setup(voi
506 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
507 + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
509 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
510 + NR_IRQS_CNS3XXX + 32);
512 if (strncmp(laguna_info.model, "GW", 2) == 0) {
513 if (laguna_info.config_bitmap & ETH0_LOAD)
514 --- a/arch/arm/Kconfig
515 +++ b/arch/arm/Kconfig
516 @@ -366,7 +366,8 @@ config ARCH_CLPS711X
518 bool "Cavium Networks CNS3XXX family"
520 - select ARCH_WANT_OPTIONAL_GPIOLIB
521 + select ARCH_REQUIRE_GPIOLIB
522 + select GENERIC_IRQ_CHIP
523 select GENERIC_CLOCKEVENTS
526 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
527 +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
528 @@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
530 #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
532 -#define NR_IRQS NR_IRQS_CNS3XXX
533 +#define NR_IRQS (NR_IRQS_CNS3XXX + 64)
536 #endif /* __MACH_BOARD_CNS3XXX_H */