1 --- a/arch/arm/mach-cns3xxx/core.c
2 +++ b/arch/arm/mach-cns3xxx/core.c
3 @@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void)
5 #ifdef CONFIG_CACHE_L2X0
7 -void __init cns3xxx_l2x0_init(void)
8 +static int cns3xxx_l2x0_enable = 1;
10 +static int __init cns3xxx_l2x0_disable(char *s)
12 + cns3xxx_l2x0_enable = 0;
15 +__setup("nol2x0", cns3xxx_l2x0_disable);
17 +static int __init cns3xxx_l2x0_init(void)
19 - void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
23 + if (!cns3xxx_l2x0_enable)
26 + base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
32 * Tag RAM Control register
33 @@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void)
35 /* 32 KiB, 8-way, parity disable */
36 l2x0_init(base, 0x00500000, 0xfe0f0fff);
40 +arch_initcall(cns3xxx_l2x0_init);
42 #endif /* CONFIG_CACHE_L2X0 */
44 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
45 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
46 @@ -217,8 +217,6 @@ static struct platform_device *cns3420_p
48 static void __init cns3420_init(void)
50 - cns3xxx_l2x0_init();
52 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
55 --- a/arch/arm/mach-cns3xxx/core.h
56 +++ b/arch/arm/mach-cns3xxx/core.h
58 extern struct smp_operations cns3xxx_smp_ops;
59 extern void cns3xxx_timer_init(void);
61 -#ifdef CONFIG_CACHE_L2X0
62 -void __init cns3xxx_l2x0_init(void);
64 -static inline void cns3xxx_l2x0_init(void) {}
65 -#endif /* CONFIG_CACHE_L2X0 */
68 extern void __init cns3xxx_pcie_init_late(void);