1 --- a/arch/arm/mach-cns3xxx/laguna.c
2 +++ b/arch/arm/mach-cns3xxx/laguna.c
4 #include <linux/kernel.h>
5 #include <linux/compiler.h>
7 +#include <linux/irq.h>
8 #include <linux/gpio.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/serial_core.h>
11 @@ -887,6 +888,47 @@ static int laguna_register_gpio(struct g
15 +/* allow disabling of external isolated PCIe IRQs */
16 +static int cns3xxx_pciextirq = 1;
17 +static int __init cns3xxx_pciextirq_disable(char *s)
19 + cns3xxx_pciextirq = 0;
22 +__setup("noextirq", cns3xxx_pciextirq_disable);
24 +static int __init laguna_pcie_init_irq(void)
26 + u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
27 + u32 reg = (__raw_readl(mem) >> 26) & 0xf;
29 + IRQ_CNS3XXX_EXTERNAL_PIN0,
30 + IRQ_CNS3XXX_EXTERNAL_PIN1,
31 + IRQ_CNS3XXX_EXTERNAL_PIN2,
35 + if (!machine_is_gw2388())
38 + /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
39 + if (cns3xxx_pciextirq && reg != 1)
40 + cns3xxx_pciextirq = 0;
42 + if (cns3xxx_pciextirq) {
43 + printk("laguna: using isolated PCI interrupts:"
44 + " irq%d/irq%d/irq%d/irq%d\n",
45 + irqs[0], irqs[1], irqs[2], irqs[3]);
46 + cns3xxx_pcie_set_irqs(0, irqs);
48 + printk("laguna: using shared PCI interrupts: irq%d\n",
49 + IRQ_CNS3XXX_PCIE0_DEVICE);
54 +subsys_initcall(laguna_pcie_init_irq);
56 static int __init laguna_model_setup(void)
59 @@ -898,8 +940,33 @@ static int __init laguna_model_setup(voi
60 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
61 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
63 - cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
64 - NR_IRQS_CNS3XXX + 32);
67 + * If pcie external interrupts are supported and desired
68 + * configure IRQ types and configure pin function.
69 + * Note that cns3xxx_pciextirq is enabled by default, but can be
70 + * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
71 + * the baseboard model does not support this hardware feature.
73 + if (cns3xxx_pciextirq) {
74 + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
75 + reg = __raw_readl(mem);
76 + /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
79 + __raw_writel(reg, mem);
81 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
82 + IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
84 + irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
85 + irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
86 + irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
87 + irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
89 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
90 + IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
93 if (strncmp(laguna_info.model, "GW", 2) == 0) {
94 if (laguna_info.config_bitmap & ETH0_LOAD)
95 --- a/arch/arm/mach-cns3xxx/pcie.c
96 +++ b/arch/arm/mach-cns3xxx/pcie.c
99 #include <linux/ioport.h>
100 #include <linux/interrupt.h>
101 +#include <linux/irq.h>
102 #include <linux/ptrace.h>
103 #include <asm/mach/map.h>
105 @@ -27,7 +28,7 @@ struct cns3xxx_pcie {
106 void __iomem *host_regs; /* PCI config registers for host bridge */
107 void __iomem *cfg0_regs; /* PCI Type 0 config registers */
108 void __iomem *cfg1_regs; /* PCI Type 1 config registers */
109 - unsigned int irqs[2];
110 + unsigned int irqs[5];
111 struct resource res_io;
112 struct resource res_mem;
114 @@ -95,7 +96,7 @@ static inline int check_master_abort(str
115 void __iomem *host_base;
118 - host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
119 + host_base = (void __iomem *) cnspci->host_regs;
120 sreg = __raw_readw(host_base + 0x6) & 0xF900;
121 ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
123 @@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops =
124 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
126 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
127 - int irq = cnspci->irqs[!!dev->bus->number];
128 + int irq = cnspci->irqs[!!dev->bus->number + pin - 1];
130 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
131 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
132 @@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
133 .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
134 .flags = IORESOURCE_MEM,
136 - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
138 + IRQ_CNS3XXX_PCIE0_RC,
139 + IRQ_CNS3XXX_PCIE0_DEVICE,
140 + IRQ_CNS3XXX_PCIE0_DEVICE,
141 + IRQ_CNS3XXX_PCIE0_DEVICE,
142 + IRQ_CNS3XXX_PCIE0_DEVICE,
147 @@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
148 .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
149 .flags = IORESOURCE_MEM,
151 - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
153 + IRQ_CNS3XXX_PCIE1_RC,
154 + IRQ_CNS3XXX_PCIE1_DEVICE,
155 + IRQ_CNS3XXX_PCIE1_DEVICE,
156 + IRQ_CNS3XXX_PCIE1_DEVICE,
157 + IRQ_CNS3XXX_PCIE1_DEVICE,
162 @@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un
166 +void __init cns3xxx_pcie_set_irqs(int bus, int *irqs)
170 + for (i = 0; i < 4; i++)
171 + cns3xxx_pcie[bus].irqs[i + 1] = irqs[i];
174 void __init cns3xxx_pcie_init_late(void)
177 --- a/arch/arm/mach-cns3xxx/core.h
178 +++ b/arch/arm/mach-cns3xxx/core.h
179 @@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void);
182 extern void __init cns3xxx_pcie_init_late(void);
183 +extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs);
185 static inline void __init cns3xxx_pcie_init_late(void) {}
186 +static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {}
189 void __init cns3xxx_map_io(void);