2 * m5485pci.h -- ColdFire 547x/548x PCI controller support.
3 * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
5 #ifndef __MCF548X_PCI_H__
6 #define __MCF548X_PCI_H__
9 /* PCI Type 0 Configuration Registers */
10 #define MCF_PCIIDR MCF_REG32(0x000B00)
11 /* PCI Device ID/Vendor ID */
12 #define MCF_PCISCR MCF_REG32(0x000B04)
13 /* PCI Status/Command */
14 #define MCF_PCICCRIR MCF_REG32(0x000B08)
15 /* PCI Class Code / Revision ID */
16 #define MCF_PCICR1 MCF_REG32(0x000B0C)
17 /* PCI Configuration 1 Register */
18 #define MCF_PCIBAR0 MCF_REG32(0x000B10)
19 /* PCI Base Address Register 0 */
20 #define MCF_PCIBAR1 MCF_REG32(0x000B14)
21 /* PCI Base Address Register 1 */
22 #define MCF_PCICCPR MCF_REG32(0x000B28)
23 /* PCI Cardbus CIS Pointer */
24 #define MCF_PCISID MCF_REG32(0x000B2C)
25 /* Subsystem ID/Subsystem Vendor ID*/
26 #define MCF_PCIERBAR MCF_REG32(0x000B30)
27 /* PCI Expansion ROM */
28 #define MCF_PCICPR MCF_REG32(0x000B30)
29 /* PCI Capabilities Pointer */
30 #define MCF_PCICR2 MCF_REG32(0x000B3C)
31 /* PCI Configuration Register 2 */
33 /* General Control/Status Registers */
34 #define MCF_PCIGSCR MCF_REG32(0x000B60)
35 /* Global Status/Control Register */
36 #define MCF_PCITBATR0 MCF_REG32(0x000B64)
37 /* Target Base Address Translation 0*/
38 #define MCF_PCITBATR1 MCF_REG32(0x000B68)
39 /* Target Base Address Translation 1*/
40 #define MCF_PCITCR MCF_REG32(0x000B6C)
41 /* Target Control Register */
42 #define MCF_PCIIW0BTAR MCF_REG32(0x000B70)
43 /* Initiator Window 0 Base Address */
44 #define MCF_PCIIW1BTAR MCF_REG32(0x000B74)
45 /* Initiator Window 1 Base Address */
46 #define MCF_PCIIW2BTAR MCF_REG32(0x000B78)
47 /* Initiator Window 2 Base Address */
48 #define MCF_PCIIWCR MCF_REG32(0x000B80)
49 /* Initiator Window Configuration */
50 #define MCF_PCIICR MCF_REG32(0x000B84)
51 /* Initiator Control Register */
52 #define MCF_PCIISR MCF_REG32(0x000B88)
53 /* Initiator Status Register */
54 #define MCF_PCICAR MCF_REG32(0x000BF8)
55 /* Configuration Address Register */
57 /* CommBus FIFO Transmit Interface Registers */
58 #define MCF_PCITPSR MCF_REG32(0x008400)
59 /* Tx Packet Size Register */
60 #define MCF_PCITSAR MCF_REG32(0x008404)
61 /* Tx Start Address Register */
62 #define MCF_PCITTCR MCF_REG32(0x008408)
63 /* Tx Transaction Control Register */
64 #define MCF_PCITER MCF_REG32(0x00840C)
65 /* Tx Enables Register */
66 #define MCF_PCITNAR MCF_REG32(0x008410)
67 /* Tx Next Address Register */
68 #define MCF_PCITLWR MCF_REG32(0x008414)
69 /* Tx Last Word Register */
70 #define MCF_PCITDCR MCF_REG32(0x008418)
71 /* Tx Done Counts Register */
72 #define MCF_PCITSR MCF_REG32(0x00841C)
73 /* Tx Status Register */
74 #define MCF_PCITFDR MCF_REG32(0x008440)
75 /* Tx FIFO Data Register */
76 #define MCF_PCITFSR MCF_REG32(0x008444)
77 /* Tx FIFO Status Register */
78 #define MCF_PCITFCR MCF_REG32(0x008448)
79 /* Tx FIFO Control Register */
80 #define MCF_PCITFAR MCF_REG32(0x00844C)
81 /* Tx FIFO Alarm Register */
82 #define MCF_PCITFRPR MCF_REG32(0x008450)
83 /* Tx FIFO Read Pointer Register */
84 #define MCF_PCITFWPR MCF_REG32(0x008454)
85 /* Tx FIFO Write Pointer Register */
87 /* CommBus FIFO Receive Interface Registers */
88 #define MCF_PCIRPSR MCF_REG32(0x008480)
89 /* Tx Packet Size Register */
90 #define MCF_PCIRSAR MCF_REG32(0x008484)
91 /* Tx Start Address Register */
92 #define MCF_PCIRTCR MCF_REG32(0x008488)
93 /* Tx Transaction Control Register */
94 #define MCF_PCIRER MCF_REG32(0x00848C)
95 /* Tx Enables Register */
96 #define MCF_PCIRNAR MCF_REG32(0x008490)
97 /* Tx Next Address Register */
98 #define MCF_PCIRDCR MCF_REG32(0x008498)
99 /* Tx Done Counts Register */
100 #define MCF_PCIRSR MCF_REG32(0x00849C)
101 /* Tx Status Register */
102 #define MCF_PCIRFDR MCF_REG32(0x0084C0)
103 /* Tx FIFO Data Register */
104 #define MCF_PCIRFSR MCF_REG32(0x0084C4)
105 /* Tx FIFO Status Register */
106 #define MCF_PCIRFCR MCF_REG32(0x0084C8)
107 /* Tx FIFO Control Register */
108 #define MCF_PCIRFAR MCF_REG32(0x0084CC)
109 /* Tx FIFO Alarm Register */
110 #define MCF_PCIRFRPR MCF_REG32(0x0084D0)
111 /* Tx FIFO Read Pointer Register */
112 #define MCF_PCIRFWPR MCF_REG32(0x0084D4)
113 /* Tx FIFO Write Pointer Register */
115 /* PCI Arbiter Registers */
116 #define MCF_PCIARB_PACR MCF_REG32(0x000C00)
117 #define MCF_PCIARB_PASR MCF_REG32(0x000C04)
120 /* Bit definitions and macros for MCF_PCIIDR */
121 #define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
122 #define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
124 /* Bit definitions and macros for MCF_PCISCR */
125 #define MCF_PCISCR_M (0x00000002)
126 #define MCF_PCISCR_B (0x00000004)
127 #define MCF_PCISCR_SP (0x00000008)
128 #define MCF_PCISCR_MW (0x00000010)
129 #define MCF_PCISCR_PER (0x00000040)
130 #define MCF_PCISCR_S (0x00000100)
131 #define MCF_PCISCR_F (0x00000200)
132 #define MCF_PCISCR_C (0x00100000)
133 #define MCF_PCISCR_66M (0x00200000)
134 #define MCF_PCISCR_R (0x00400000)
135 #define MCF_PCISCR_FC (0x00800000)
136 #define MCF_PCISCR_DP (0x01000000)
137 #define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25)
138 #define MCF_PCISCR_TS (0x08000000)
139 #define MCF_PCISCR_TR (0x10000000)
140 #define MCF_PCISCR_MA (0x20000000)
141 #define MCF_PCISCR_SE (0x40000000)
142 #define MCF_PCISCR_PE (0x80000000)
144 /* Bit definitions and macros for MCF_PCICCRIR */
145 #define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
146 #define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
148 /* Bit definitions and macros for MCF_PCICR1 */
149 #define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
150 #define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
151 #define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
152 #define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
154 /* Bit definitions and macros for MCF_PCIBAR# */
155 #define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18)
156 #define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30)
158 /* Bit definitions and macros for MCF_PCICR2 */
159 #define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
160 #define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
161 #define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
162 #define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
164 /* Bit definitions and macros for MCF_PCIGSCR */
165 #define MCF_PCIGSCR_PR (0x00000001)
166 #define MCF_PCIGSCR_SEE (0x00001000)
167 #define MCF_PCIGSCR_PEE (0x00002000)
168 #define MCF_PCIGSCR_SE (0x10000000)
169 #define MCF_PCIGSCR_PE (0x20000000)
171 /* Bit definitions and macros for MCF_PCITBATR0 */
172 #define MCF_PCITBATR0_EN (0x00000001)
173 #define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
175 /* Bit definitions and macros for MCF_PCITBATR1 */
176 #define MCF_PCITBATR1_EN (0x00000001)
177 #define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
179 /* Bit definitions and macros for MCF_PCITCR */
180 #define MCF_PCITCR_P (0x00010000)
181 #define MCF_PCITCR_LD (0x01000000)
183 /* Bit definitions and macros for MCF_PCIIW0BTAR */
184 #define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
185 #define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
186 #define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
188 /* Bit definitions and macros for MCF_PCIIW1BTAR */
189 #define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
190 #define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
191 #define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
193 /* Bit definitions and macros for MCF_PCIIW2BTAR */
194 #define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
195 #define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
196 #define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
198 /* Bit definitions and macros for MCF_PCIIWCR */
199 #define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
200 #define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
201 #define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
202 #define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
203 #define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
204 #define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
205 #define MCF_PCIIWCR_WINCTRL0_IO (0x09000000)
206 #define MCF_PCIIWCR_WINCTRL0_E (0x01000000)
207 #define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
208 #define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
209 #define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
210 #define MCF_PCIIWCR_WINCTRL1_IO (0x00090000)
211 #define MCF_PCIIWCR_WINCTRL1_E (0x00010000)
212 #define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
213 #define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
214 #define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
215 #define MCF_PCIIWCR_WINCTRL2_IO (0x00000900)
216 #define MCF_PCIIWCR_WINCTRL2_E (0x00000100)
219 /* Bit definitions and macros for MCF_PCIICR */
220 #define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
221 #define MCF_PCIICR_TAE (0x01000000)
222 #define MCF_PCIICR_IAE (0x02000000)
223 #define MCF_PCIICR_REE (0x04000000)
225 /* Bit definitions and macros for MCF_PCIISR */
226 #define MCF_PCIISR_TA (0x01000000)
227 #define MCF_PCIISR_IA (0x02000000)
228 #define MCF_PCIISR_RE (0x04000000)
230 /* Bit definitions and macros for MCF_PCICAR */
231 #define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
232 #define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
233 #define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
234 #define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
235 #define MCF_PCICAR_E (0x80000000)
237 /* Bit definitions and macros for MCF_PCITPSR */
238 #define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
240 /* Bit definitions and macros for MCF_PCITTCR */
241 #define MCF_PCITTCR_DI (0x00000001)
242 #define MCF_PCITTCR_W (0x00000010)
243 #define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
244 #define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
245 #define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
247 /* Bit definitions and macros for MCF_PCITER */
248 #define MCF_PCITER_NE (0x00010000)
249 #define MCF_PCITER_IAE (0x00020000)
250 #define MCF_PCITER_TAE (0x00040000)
251 #define MCF_PCITER_RE (0x00080000)
252 #define MCF_PCITER_SE (0x00100000)
253 #define MCF_PCITER_FEE (0x00200000)
254 #define MCF_PCITER_ME (0x01000000)
255 #define MCF_PCITER_BE (0x08000000)
256 #define MCF_PCITER_CM (0x10000000)
257 #define MCF_PCITER_RF (0x40000000)
258 #define MCF_PCITER_RC (0x80000000)
260 /* Bit definitions and macros for MCF_PCITDCR */
261 #define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
262 #define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
264 /* Bit definitions and macros for MCF_PCITSR */
265 #define MCF_PCITSR_IA (0x00010000)
266 #define MCF_PCITSR_TA (0x00020000)
267 #define MCF_PCITSR_RE (0x00040000)
268 #define MCF_PCITSR_SE (0x00080000)
269 #define MCF_PCITSR_FE (0x00100000)
270 #define MCF_PCITSR_BE1 (0x00200000)
271 #define MCF_PCITSR_BE2 (0x00400000)
272 #define MCF_PCITSR_BE3 (0x00800000)
273 #define MCF_PCITSR_NT (0x01000000)
275 /* Bit definitions and macros for MCF_PCITFSR */
276 #define MCF_PCITFSR_EMT (0x00010000)
277 #define MCF_PCITFSR_ALARM (0x00020000)
278 #define MCF_PCITFSR_FU (0x00040000)
279 #define MCF_PCITFSR_FR (0x00080000)
280 #define MCF_PCITFSR_OF (0x00100000)
281 #define MCF_PCITFSR_UF (0x00200000)
282 #define MCF_PCITFSR_RXW (0x00400000)
284 /* Bit definitions and macros for MCF_PCITFCR */
285 #define MCF_PCITFCR_OF_MSK (0x00080000)
286 #define MCF_PCITFCR_UF_MSK (0x00100000)
287 #define MCF_PCITFCR_RXW_MSK (0x00200000)
288 #define MCF_PCITFCR_FAE_MSK (0x00400000)
289 #define MCF_PCITFCR_IP_MSK (0x00800000)
290 #define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24)
292 /* Bit definitions and macros for MCF_PCITFAR */
293 #define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
295 /* Bit definitions and macros for MCF_PCITFRPR */
296 #define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
298 /* Bit definitions and macros for MCF_PCITFWPR */
299 #define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
301 /* Bit definitions and macros for MCF_PCIRPSR */
302 #define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
304 /* Bit definitions and macros for MCF_PCIRTCR */
305 #define MCF_PCIRTCR_DI (0x00000001)
306 #define MCF_PCIRTCR_W (0x00000010)
307 #define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
308 #define MCF_PCIRTCR_FB (0x00001000)
309 #define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
310 #define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
312 /* Bit definitions and macros for MCF_PCIRER */
313 #define MCF_PCIRER_NE (0x00010000)
314 #define MCF_PCIRER_IAE (0x00020000)
315 #define MCF_PCIRER_TAE (0x00040000)
316 #define MCF_PCIRER_RE (0x00080000)
317 #define MCF_PCIRER_SE (0x00100000)
318 #define MCF_PCIRER_FEE (0x00200000)
319 #define MCF_PCIRER_ME (0x01000000)
320 #define MCF_PCIRER_BE (0x08000000)
321 #define MCF_PCIRER_CM (0x10000000)
322 #define MCF_PCIRER_FE (0x20000000)
323 #define MCF_PCIRER_RF (0x40000000)
324 #define MCF_PCIRER_RC (0x80000000)
326 /* Bit definitions and macros for MCF_PCIRDCR */
327 #define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
328 #define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
330 /* Bit definitions and macros for MCF_PCIRSR */
331 #define MCF_PCIRSR_IA (0x00010000)
332 #define MCF_PCIRSR_TA (0x00020000)
333 #define MCF_PCIRSR_RE (0x00040000)
334 #define MCF_PCIRSR_SE (0x00080000)
335 #define MCF_PCIRSR_FE (0x00100000)
336 #define MCF_PCIRSR_BE1 (0x00200000)
337 #define MCF_PCIRSR_BE2 (0x00400000)
338 #define MCF_PCIRSR_BE3 (0x00800000)
339 #define MCF_PCIRSR_NT (0x01000000)
341 /* Bit definitions and macros for MCF_PCIRFSR */
342 #define MCF_PCIRFSR_EMT (0x00010000)
343 #define MCF_PCIRFSR_ALARM (0x00020000)
344 #define MCF_PCIRFSR_FU (0x00040000)
345 #define MCF_PCIRFSR_FR (0x00080000)
346 #define MCF_PCIRFSR_OF (0x00100000)
347 #define MCF_PCIRFSR_UF (0x00200000)
348 #define MCF_PCIRFSR_RXW (0x00400000)
350 /* Bit definitions and macros for MCF_PCIRFCR */
351 #define MCF_PCIRFCR_OF_MSK (0x00080000)
352 #define MCF_PCIRFCR_UF_MSK (0x00100000)
353 #define MCF_PCIRFCR_RXW_MSK (0x00200000)
354 #define MCF_PCIRFCR_FAE_MSK (0x00400000)
355 #define MCF_PCIRFCR_IP_MSK (0x00800000)
356 #define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
358 /* Bit definitions and macros for MCF_PCIRFAR */
359 #define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
361 /* Bit definitions and macros for MCF_PCIRFRPR */
362 #define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
364 /* Bit definitions and macros for MCF_PCIRFWPR */
365 #define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
368 /* Bit definitions and macros for MCF_PCIARB_PACR */
369 #define MCF_PCIARB_PACR_INTMPRI (0x00000001)
370 #define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
371 #define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
372 #define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
373 #define MCF_PCIARB_PACR_PKMD (0x40000000)
374 #define MCF_PCIARB_PACR_DS (0x80000000)
376 /* Bit definitions and macros for MCF_PCIARB_PASR */
377 #define MCF_PCIARB_PASR_ITLMBK (0x00010000)
378 #define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
380 #endif /* __MCF548X_PCI_H__ */
projects / openwrt / staging / dedeckeh.git / blob