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[openwrt/staging/florian.git] / target / linux / coldfire / patches / 007-Add-eDMA-support-for-MCF5445x.patch
1 From cd07e01d0c6c207a6138e9d5229dfa8c88ab3879 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Thu, 4 Aug 2011 09:59:40 +0800
4 Subject: [PATCH 07/52] Add eDMA support for MCF5445x
5
6 Add MCF5445x on-chip eDMA controller driver.
7
8 Signed-off-by: Alison Wang <b18965@freescale.com>
9 ---
10 arch/m68k/include/asm/mcf_edma.h | 246 +++++++++
11 drivers/Makefile | 2 +
12 drivers/dma/Kconfig | 15 +
13 drivers/dma/Makefile | 4 +
14 drivers/dma/mcf_edma.c | 1029 ++++++++++++++++++++++++++++++++++++++
15 drivers/dma/mcf_edma_test.c | 276 ++++++++++
16 6 files changed, 1572 insertions(+), 0 deletions(-)
17 create mode 100644 arch/m68k/include/asm/mcf_edma.h
18 create mode 100644 drivers/dma/mcf_edma.c
19 create mode 100644 drivers/dma/mcf_edma_test.c
20
21 --- /dev/null
22 +++ b/arch/m68k/include/asm/mcf_edma.h
23 @@ -0,0 +1,246 @@
24 +/*
25 + * mcf_edma.h - Coldfire eDMA driver header file.
26 + *
27 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
28 + *
29 + * Add support for m5441x platform (Lanttor.Guo@freescale.com)
30 + *
31 + * This program is free software; you can redistribute it and/or modify it
32 + * under the terms of the GNU General Public License as published by the
33 + * Free Software Foundation; either version 2 of the License, or (at your
34 + * option) any later version.
35 + */
36 +
37 +#ifndef _MCF_EDMA_H
38 +#define _MCF_EDMA_H
39 +
40 +#include <asm/mcfsim.h>
41 +#include <linux/interrupt.h>
42 +#if defined(CONFIG_M5445X)
43 +#include <asm/mcf5445x_edma.h>
44 +#elif defined(CONFIG_M5441X)
45 +#include <asm/mcf5441x_edma.h>
46 +#endif
47 +#include <linux/scatterlist.h>
48 +
49 +#define MCF_EDMA_INT0_CHANNEL_BASE (8)
50 +#define MCF_EDMA_INT0_CONTROLLER_BASE (64)
51 +#define MCF_EDMA_INT0_BASE (MCF_EDMA_INT0_CHANNEL_BASE + \
52 + MCF_EDMA_INT0_CONTROLLER_BASE)
53 +#define MCF_EDMA_INT0_NUM (16)
54 +#define MCF_EDMA_INT0_END (MCF_EDMA_INT0_NUM)
55 +
56 +#if defined(CONFIG_M5441X)
57 +#define MCF_EDMA_INT1_CHANNEL_BASE (8)
58 +#define MCF_EDMA_INT1_CONTROLLER_BASE (128)
59 +#define MCF_EDMA_INT1_BASE (MCF_EDMA_INT1_CHANNEL_BASE + \
60 + MCF_EDMA_INT1_CONTROLLER_BASE)
61 +#define MCF_EDMA_INT1_NUM (40)
62 +#define MCF_EDMA_INT1_END (MCF_EDMA_INT0_END + MCF_EDMA_INT1_NUM)
63 +
64 +#define MCF_EDMA_INT2_CHANNEL_BASE (0)
65 +#define MCF_EDMA_INT2_CONTROLLER_BASE (192)
66 +#define MCF_EDMA_INT2_BASE (MCF_EDMA_INT2_CHANNEL_BASE + \
67 + MCF_EDMA_INT2_CONTROLLER_BASE)
68 +#define MCF_EDMA_INT2_NUM (8)
69 +#define MCF_EDMA_INT2_END (MCF_EDMA_INT1_END + MCF_EDMA_INT2_NUM)
70 +
71 +#endif
72 +
73 +#if defined(CONFIG_M5445X)
74 +#define MCF_EDMA_CHANNELS (16) /* 0-15 */
75 +#elif defined(CONFIG_M5441X)
76 +#define MCF_EDMA_CHANNELS (64) /* 0-63 */
77 +#endif
78 +
79 +#define MCF_EDMA_CHANNEL_ANY (0xFF)
80 +#define MCF_EDMA_INT_ERR (16) /* edma error interrupt */
81 +
82 +#define MCF_EDMA_TCD_PER_CHAN 256
83 +
84 +#ifdef CONFIG_M54455
85 +/* eDMA engine TCD memory description */
86 +
87 +struct TCD {
88 + u32 saddr;
89 + u16 attr;
90 + u16 soff;
91 + u32 nbytes;
92 + u32 slast;
93 + u32 daddr;
94 + u16 citer;
95 + u16 doff;
96 + u32 dlast_sga;
97 + u16 biter;
98 + u16 csr;
99 +} __packed;
100 +
101 +struct fsl_edma_requestbuf {
102 + dma_addr_t saddr;
103 + dma_addr_t daddr;
104 + u32 soff;
105 + u32 doff;
106 + u32 attr;
107 + u32 minor_loop;
108 + u32 len;
109 +};
110 +
111 +/*
112 + * config the eDMA to use the TCD sg feature
113 + *
114 + * @channel: which channel. in fact this function is designed to satisfy
115 + * the ATA driver TCD SG need, i.e. by now it is a special
116 + * func, because it need prev alloc channel TCD physical memory
117 + * first, we add the ATA's in the eDMA init only
118 + * @buf: buffer array to fill the TCDs
119 + * @nents: the size of the buf
120 + */
121 +void mcf_edma_sg_config(int channel, struct fsl_edma_requestbuf *buf,
122 + int nents);
123 +
124 +/*
125 + * The zero-copy version of mcf_edma_sg_config()
126 + */
127 +void mcf_edma_sglist_config(int channel, struct scatterlist *sgl, int n_elem,
128 + int dma_dir, u32 addr, u32 attr,
129 + u32 soff, u32 doff, u32 nbytes);
130 +#endif
131 +
132 +/* Setup transfer control descriptor (TCD)
133 + * channel - descriptor number
134 + * source - source address
135 + * dest - destination address
136 + * attr - attributes
137 + * soff - source offset
138 + * nbytes - number of bytes to be transfered in minor loop
139 + * slast - last source address adjustment
140 + * citer - major loop count
141 + * biter - begining minor loop count
142 + * doff - destination offset
143 + * dlast_sga - last destination address adjustment
144 + * major_int - generate interrupt after each major loop
145 + * disable_req - disable DMA request after major loop
146 + */
147 +void mcf_edma_set_tcd_params(int channel, u32 source, u32 dest,
148 + u32 attr, u32 soff, u32 nbytes, u32 slast,
149 + u32 citer, u32 biter, u32 doff, u32 dlast_sga,
150 + int major_int, int disable_req);
151 +
152 +/* Setup transfer control descriptor (TCD) and enable halfway irq
153 + * channel - descriptor number
154 + * source - source address
155 + * dest - destination address
156 + * attr - attributes
157 + * soff - source offset
158 + * nbytes - number of bytes to be transfered in minor loop
159 + * slast - last source address adjustment
160 + * biter - major loop count
161 + * doff - destination offset
162 + * dlast_sga - last destination address adjustment
163 + * disable_req - disable DMA request after major loop
164 + */
165 +void mcf_edma_set_tcd_params_halfirq(int channel, u32 source, u32 dest,
166 + u32 attr, u32 soff, u32 nbytes, u32 slast,
167 + u32 biter, u32 doff, u32 dlast_sga,
168 + int disable_req);
169 +
170 +/* check if dma is done
171 + * channel - descriptor number
172 + * return 1 if done
173 + */
174 +int mcf_edma_check_done(int channel);
175 +
176 +/* Starts eDMA transfer on specified channel
177 + * channel - eDMA TCD number
178 + */
179 +static inline void
180 +mcf_edma_start_transfer(int channel)
181 +{
182 + MCF_EDMA_SERQ = channel;
183 + MCF_EDMA_SSRT = channel;
184 +}
185 +
186 +/* Restart eDMA transfer from halfirq
187 + * channel - eDMA TCD number
188 + */
189 +static inline void
190 +mcf_edma_confirm_halfirq(int channel)
191 +{
192 + /*MCF_EDMA_TCD_CSR(channel) = 7;*/
193 + MCF_EDMA_SSRT = channel;
194 +}
195 +
196 +/* Starts eDMA transfer on specified channel based on peripheral request
197 + * channel - eDMA TCD number
198 + */
199 +static inline void mcf_edma_enable_transfer(int channel)
200 +{
201 + MCF_EDMA_SERQ = channel;
202 +}
203 +
204 +
205 +/* Stops eDMA transfer
206 + * channel - eDMA TCD number
207 + */
208 +static inline void
209 +mcf_edma_stop_transfer(int channel)
210 +{
211 + MCF_EDMA_CINT = channel;
212 + MCF_EDMA_CERQ = channel;
213 +}
214 +
215 +/* Confirm that interrupt has been handled
216 + * channel - eDMA TCD number
217 + */
218 +static inline void
219 +mcf_edma_confirm_interrupt_handled(int channel)
220 +{
221 + MCF_EDMA_CINT = channel;
222 +}
223 +
224 +/**
225 + * mcf_edma_request_channel - Request an eDMA channel
226 + * @channel: channel number. In case it is equal to EDMA_CHANNEL_ANY
227 + * it will be allocated a first free eDMA channel.
228 + * @handler: dma handler
229 + * @error_handler: dma error handler
230 + * @irq_level: irq level for the dma handler
231 + * @arg: argument to pass back
232 + * @lock: optional spinlock to hold over interrupt
233 + * @device_id: device id
234 + *
235 + * Returns allocatedd channel number if success or
236 + * a negative value if failure.
237 + */
238 +int mcf_edma_request_channel(int channel,
239 + irqreturn_t(*handler) (int, void *),
240 + void (*error_handler) (int, void *),
241 + u8 irq_level,
242 + void *arg,
243 + spinlock_t *lock, const char *device_id);
244 +
245 +/**
246 + * Update the channel callback/arg
247 + * @channel: channel number
248 + * @handler: dma handler
249 + * @error_handler: dma error handler
250 + * @arg: argument to pass back
251 + *
252 + * Returns 0 if success or a negative value if failure
253 + */
254 +int mcf_edma_set_callback(int channel,
255 + irqreturn_t(*handler) (int, void *),
256 + void (*error_handler) (int, void *), void *arg);
257 +
258 +/**
259 + * Free the edma channel
260 + * @channel: channel number
261 + * @arg: argument created with
262 + *
263 + * Returns 0 if success or a negative value if failure
264 + */
265 +int mcf_edma_free_channel(int channel, void *arg);
266 +
267 +void mcf_edma_dump_channel(int channel);
268 +
269 +#endif /* _MCF_EDMA_H */
270 --- a/drivers/Makefile
271 +++ b/drivers/Makefile
272 @@ -39,6 +39,7 @@ obj-$(CONFIG_FB_I810) += video
273 obj-$(CONFIG_FB_INTEL) += video/intelfb/
274
275 obj-$(CONFIG_PARPORT) += parport/
276 +obj-$(CONFIG_COLDFIRE_EDMA) += dma/
277 obj-y += base/ block/ misc/ mfd/ nfc/
278 obj-$(CONFIG_NUBUS) += nubus/
279 obj-y += macintosh/
280 @@ -114,6 +115,7 @@ obj-$(CONFIG_BCMA) += bcma/
281 obj-$(CONFIG_VHOST_NET) += vhost/
282 obj-$(CONFIG_VLYNQ) += vlynq/
283 obj-$(CONFIG_STAGING) += staging/
284 +obj-$(CONFIG_MCD_DMA) += dma/
285 obj-y += platform/
286 obj-y += ieee802154/
287 #common clk code
288 --- a/drivers/dma/Kconfig
289 +++ b/drivers/dma/Kconfig
290 @@ -114,6 +114,21 @@ config MPC512X_DMA
291 ---help---
292 Enable support for the Freescale MPC512x built-in DMA engine.
293
294 +config COLDFIRE_EDMA
295 + tristate "Coldfire eDMA support"
296 + default y
297 + depends on COLDFIRE && (M5445X || M5441X)
298 + help
299 + Enable support for Coldfire eDMA controller. For example
300 + used by Coldfire SSI Audio device driver.
301 +
302 +config COLDFIRE_EDMA_TEST
303 + tristate "Coldfire eDMA simple test module"
304 + default m
305 + depends on COLDFIRE_EDMA
306 + help
307 + This is simple eDMA test module.
308 +
309 config MV_XOR
310 bool "Marvell XOR engine support"
311 depends on PLAT_ORION
312 --- a/drivers/dma/Makefile
313 +++ b/drivers/dma/Makefile
314 @@ -13,10 +13,14 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioat/
315 obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
316 obj-$(CONFIG_FSL_DMA) += fsldma.o
317 obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
318 +obj-$(CONFIG_COLDFIRE_EDMA) += mcf_edma.o
319 +obj-$(CONFIG_COLDFIRE_EDMA_TEST) += mcf_edma_test.o
320 obj-$(CONFIG_MV_XOR) += mv_xor.o
321 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
322 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
323 obj-$(CONFIG_MX3_IPU) += ipu/
324 +obj-$(CONFIG_MCD_DMA) += mcddma.o
325 +mcddma-objs := MCD_dmaApi.o MCD_tasks.o MCD_tasksInit.o
326 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
327 obj-$(CONFIG_SH_DMAE) += shdma.o
328 obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
329 --- /dev/null
330 +++ b/drivers/dma/mcf_edma.c
331 @@ -0,0 +1,1029 @@
332 +/*
333 + * mcf_edma.c - eDMA driver for Coldfire.
334 + *
335 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
336 + * Author: Andrey Butok
337 + * Yaroslav Vinogradov
338 + * Lanttor.Guo@freescale.com add m5441x platform support.
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * This program is distributed in the hope that it will be useful,
346 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
347 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
348 + * GNU General Public License for more details.
349 + *
350 + * You should have received a copy of the GNU General Public License
351 + * along with this program; if not, write to the Free Software
352 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
353 + *
354 + ***************************************************************************
355 + * Changes:
356 + * v0.002 29 February 2008 Andrey Butok, Freescale Semiconductor
357 + * Added support of atomatic channel allocation from the
358 + * channel pool.
359 + * v0.001 12 February 2008 Andrey Butok
360 + * Initial Release - developed on uClinux with 2.6.23 kernel.
361 + * Based on coldfire_edma.c code
362 + * of Yaroslav Vinogradov (Freescale Semiconductor, Inc.)
363 + *
364 + * NOTE: This driver was tested on MCF52277 platform.
365 + * It should also work on other Coldfire platdorms with eDMA module.
366 + *
367 + * TBD: Try to make it more general.
368 + * Try to integrate with current <asm/dma.h> <kernel/dma.c> API
369 + * or use Intel DMA API
370 + */
371 +
372 +#include <linux/dma-mapping.h>
373 +#include <asm/mcf_edma.h>
374 +#include <linux/init.h>
375 +#include <linux/module.h>
376 +#include <asm/coldfire.h>
377 +#include <linux/fs.h>
378 +#include <linux/cdev.h>
379 +#include <linux/seq_file.h>
380 +#include <linux/proc_fs.h>
381 +
382 +/* Please add here processors that were tested with this driver */
383 +#if !defined(CONFIG_M5227x) && !defined(CONFIG_M5445X) && \
384 + !defined(CONFIG_M5441X)
385 +#error "The driver is not tested/designed for your processor!"
386 +#endif
387 +
388 +#define MCF_EDMA_DRIVER_VERSION "Revision: 0.003"
389 +#define MCF_EDMA_DRIVER_AUTHOR "Freescale Semiconductor Inc, Andrey Butok"
390 +#define MCF_EDMA_DRIVER_DESC "Coldfire EDMA driver."
391 +#define MCF_EDMA_DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
392 +#define MCF_EDMA_DRIVER_LICENSE "GPL"
393 +#define MCF_EDMA_DRIVER_NAME "mcf_edma"
394 +
395 +#define MCF_EDMA_DEV_MINOR (1)
396 +
397 +#undef MCF_EDMA_DEBUG
398 +
399 +#ifdef MCF_EDMA_DEBUG
400 +#define DBG(fmt, args...) printk(KERN_INFO "[%s] " fmt, \
401 + __func__, ## args)
402 +#else
403 +#define DBG(fmt, args...) do {} while (0)
404 +#endif
405 +
406 +#define ERR(format, arg...) printk(KERN_ERR "%s:%s: " format "\n", \
407 + __FILE__, __func__ , ## arg)
408 +#define INFO(stuff...) printk(KERN_INFO MCF_EDMA_DRIVER_NAME \
409 + ": " stuff)
410 +
411 +/* DMA channel pool used for atomtic channel allocation.
412 + * You can edit this list. First candidates are "Not used/Reserved" channels */
413 +u8 mcf_edma_channel_pool[] = { 1, /* Not used */
414 + 0, /* External DMA request */
415 + 5, /* UART1 Receive */
416 + 6, /* UART1 Transmit */
417 + 7, /* UART2 Receive */
418 + 8, /* UART2 Transmit */
419 +#if defined(CONFIG_M5441X)
420 + 16,
421 + 55,
422 + 56,
423 + 63,
424 +#endif
425 +};
426 +
427 +/*
428 + * Callback handler data for each TCD
429 + */
430 +struct mcf_edma_isr_record {
431 + irqreturn_t(*irq_handler) (int, void *); /* interrupt handler */
432 + void (*error_handler) (int, void *); /* error interrupt handler */
433 + void *arg; /* argument to pass back */
434 + int allocated; /* busy flag */
435 + spinlock_t *lock; /* spin lock (optional) */
436 + const char *device_id; /* dev id string, used in procfs */
437 +};
438 +
439 +/*
440 + * Device structure
441 + */
442 +struct mcf_edma_dev {
443 + struct cdev cdev; /* character device */
444 + struct mcf_edma_isr_record dma_interrupt_handlers[MCF_EDMA_CHANNELS];
445 +};
446 +
447 +/* allocated major device number */
448 +static int mcf_edma_major;
449 +
450 +/* device driver structure */
451 +static struct mcf_edma_dev *mcf_edma_devp;
452 +
453 +#ifdef CONFIG_M54455
454 +/* PATA controller structure */
455 +static struct {
456 + struct TCD *pata_tcd_va;
457 + dma_addr_t pata_tcd_pa;
458 +} fsl_pata_dma_tcd;
459 +#endif
460 +
461 +/* device driver file operations */
462 +const struct file_operations mcf_edma_fops = {
463 + .owner = THIS_MODULE,
464 +};
465 +
466 +/**
467 + * mcf_edma_isr - eDMA channel interrupt handler
468 + * @irq: interrupt number
469 + * @dev_id: argument
470 + */
471 +static irqreturn_t
472 +mcf_edma_isr(int irq, void *dev_id)
473 +{
474 + int channel = -1;
475 + int result = IRQ_HANDLED;
476 +
477 +#if defined(CONFIG_M5445X)
478 + channel = irq - MCF_EDMA_INT0_BASE;
479 +#elif defined(CONFIG_M5441X)
480 + if (irq >= MCF_EDMA_INT0_BASE &&
481 + irq < MCF_EDMA_INT0_BASE + MCF_EDMA_INT0_NUM)
482 + channel = irq - MCF_EDMA_INT0_BASE;
483 + else if (irq >= MCF_EDMA_INT1_BASE &&
484 + irq < MCF_EDMA_INT1_BASE + MCF_EDMA_INT1_NUM)
485 + channel = irq - MCF_EDMA_INT1_BASE + MCF_EDMA_INT0_END;
486 + else if (irq == MCF_EDMA_INT2_BASE &&
487 + irq < MCF_EDMA_INT2_BASE + MCF_EDMA_INT2_NUM) {
488 + int i;
489 + for (i = 0; i < MCF_EDMA_INT2_NUM; i++) {
490 + if ((MCF_EDMA_INTH >> 24) & (0x1 << i)) {
491 + channel = irq - MCF_EDMA_INT2_BASE +
492 + MCF_EDMA_INT1_END + i;
493 + break;
494 + }
495 + }
496 + } else {
497 + ERR("Bad irq number at isr!\n");
498 + return result;
499 + }
500 +#endif
501 +
502 + DBG("\n");
503 +
504 + if ((mcf_edma_devp != NULL) &&
505 + (mcf_edma_devp->dma_interrupt_handlers[channel].irq_handler)) {
506 + /* call user irq handler */
507 + if (mcf_edma_devp->dma_interrupt_handlers[channel].lock)
508 + spin_lock(mcf_edma_devp->
509 + dma_interrupt_handlers[channel].lock);
510 +
511 + result =
512 + mcf_edma_devp->dma_interrupt_handlers[channel].
513 + irq_handler(channel,
514 + mcf_edma_devp->dma_interrupt_handlers[channel].
515 + arg);
516 +
517 + if (mcf_edma_devp->dma_interrupt_handlers[channel].lock)
518 + spin_unlock(mcf_edma_devp->
519 + dma_interrupt_handlers[channel].lock);
520 + } else {
521 + /* no irq handler so just ack it */
522 + mcf_edma_confirm_interrupt_handled(channel);
523 + ERR(" No handler for DMA channel (%d)\n", channel);
524 + }
525 +
526 + return result;
527 +}
528 +
529 +/**
530 + * mcf_edma_error_isr - eDMA error interrupt handler
531 + * @irq: interrupt number
532 + * @dev_id: argument
533 + */
534 +static irqreturn_t
535 +mcf_edma_error_isr(int irq, void *dev_id)
536 +{
537 + int i;
538 +
539 +#if defined(CONFIG_M5445X)
540 + u16 err;
541 +
542 + err = MCF_EDMA_ERR;
543 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
544 + if (err & (1 << i)) {
545 + if (mcf_edma_devp != NULL &&
546 + mcf_edma_devp->dma_interrupt_handlers[i].
547 + error_handler)
548 + mcf_edma_devp->dma_interrupt_handlers[i].
549 + error_handler(i,
550 + mcf_edma_devp->
551 + dma_interrupt_handlers[i].
552 + arg);
553 + else
554 + ERR(" DMA error on channel (%d)\n", i);
555 + }
556 + }
557 +#elif defined(CONFIG_M5441X)
558 + u32 errl, errh;
559 +
560 + errl = MCF_EDMA_ERRL;
561 + errh = MCF_EDMA_ERRH;
562 +
563 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
564 + if ((errl & (1 << i)) || (errh & (1 << (i - 32)))) {
565 + if (mcf_edma_devp != NULL &&
566 + mcf_edma_devp->dma_interrupt_handlers[i].
567 + error_handler)
568 + mcf_edma_devp->dma_interrupt_handlers[i].
569 + error_handler(i, mcf_edma_devp->
570 + dma_interrupt_handlers[i].arg);
571 + else
572 + ERR(" DMA error on channel (%d)\n", i);
573 + }
574 + }
575 +#endif
576 + MCF_EDMA_CERR = MCF_EDMA_CERR_CAER;
577 + return IRQ_HANDLED;
578 +}
579 +
580 +/**
581 + * mcf_edma_check_done - Check if channel is finished or not
582 + * @channel: channel number
583 + * return: 0 if not done yet
584 + */
585 +int
586 +mcf_edma_check_done(int channel)
587 +{
588 + if (channel < 0 || channel > MCF_EDMA_CHANNELS)
589 + return 1;
590 +
591 + return MCF_EDMA_TCD_CSR(channel) & MCF_EDMA_TCD_CSR_DONE;
592 +}
593 +EXPORT_SYMBOL(mcf_edma_check_done);
594 +
595 +/**
596 + * mcf_edma_set_tcd_params - Set transfer control descriptor (TCD)
597 + * @channel: channel number
598 + * @source: source address
599 + * @dest: destination address
600 + * @attr: attributes
601 + * @soff: source offset
602 + * @nbytes: number of bytes to be transfered in minor loop
603 + * @slast: last source address adjustment
604 + * @citer: major loop count
605 + * @biter: beginning major loop count
606 + * @doff: destination offset
607 + * @dlast_sga: last destination address adjustment
608 + * @major_int: generate interrupt after each major loop
609 + * @disable_req: disable DMA request after major loop
610 + */
611 +void
612 +mcf_edma_set_tcd_params(int channel, u32 source, u32 dest,
613 + u32 attr, u32 soff, u32 nbytes, u32 slast,
614 + u32 citer, u32 biter, u32 doff, u32 dlast_sga,
615 + int major_int, int disable_req)
616 +{
617 + DBG("(%d)\n", channel);
618 +
619 + if (channel < 0 || channel > MCF_EDMA_CHANNELS)
620 + return;
621 +
622 + MCF_EDMA_TCD_SADDR(channel) = source;
623 + MCF_EDMA_TCD_DADDR(channel) = dest;
624 + MCF_EDMA_TCD_ATTR(channel) = attr;
625 + MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(soff);
626 + MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(nbytes);
627 + MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(slast);
628 + MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(citer);
629 + MCF_EDMA_TCD_BITER(channel) = MCF_EDMA_TCD_BITER_BITER(biter);
630 + MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(doff);
631 + MCF_EDMA_TCD_DLAST_SGA(channel) =
632 + MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga);
633 + MCF_EDMA_TCD_CSR(channel) = 0x0000;
634 +
635 + /* interrupt at the end of major loop */
636 + if (major_int)
637 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_INT_MAJOR;
638 + else
639 + MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_INT_MAJOR;
640 +
641 + /* disable request at the end of major loop of transfer or not */
642 + if (disable_req)
643 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_D_REQ;
644 + else
645 + MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_D_REQ;
646 +
647 + /* enable error interrupt */
648 + MCF_EDMA_SEEI = MCF_EDMA_SEEI_SEEI(channel);
649 +}
650 +EXPORT_SYMBOL(mcf_edma_set_tcd_params);
651 +#ifdef CONFIG_M54455
652 +/**
653 + * mcf_edma_sg_config - config an eDMA channel to use the S/G tcd feature
654 + * @channel: channel number
655 + * @buf: the array of tcd sg
656 + * @nents: number of tcd sg array, the max is 256 set but can modify
657 + *
658 + * limitation:
659 + * currently this function is only for PATA RX/TX on MCF54455,
660 + * so eDMA init does not allocate TCD memory for other memory
661 + *
662 + * TODO:
663 + * any one who need this feature shoule add his own TCD memory init
664 + */
665 +void mcf_edma_sg_config(int channel, struct fsl_edma_requestbuf *buf,
666 + int nents)
667 +{
668 + struct TCD *vtcd = (struct TCD *)fsl_pata_dma_tcd.pata_tcd_va;
669 + u32 ptcd = fsl_pata_dma_tcd.pata_tcd_pa;
670 + struct fsl_edma_requestbuf *pb = buf;
671 + int i;
672 +
673 + if (channel < MCF_EDMA_CHAN_ATA_RX || channel > MCF_EDMA_CHAN_ATA_TX) {
674 + printk(KERN_ERR "mcf edma sg config err, not support\n");
675 + return;
676 + }
677 + if (nents > MCF_EDMA_TCD_PER_CHAN) {
678 + printk(KERN_ERR "Too many SGs, please confirm.%d > %d\n",
679 + nents, MCF_EDMA_TCD_PER_CHAN);
680 + return;
681 + }
682 +
683 + /* build our tcd sg array */
684 + for (i = 0; i < nents; i++) {
685 + memset(vtcd, 0 , sizeof(struct TCD));
686 + vtcd->saddr = pb->saddr;
687 + vtcd->daddr = pb->daddr;
688 + vtcd->attr = pb->attr;
689 + vtcd->soff = pb->soff;
690 + vtcd->doff = pb->doff;
691 + vtcd->nbytes = pb->minor_loop;
692 + vtcd->citer = vtcd->biter = pb->len/pb->minor_loop;
693 +
694 + if (i != nents - 1) {
695 + vtcd->csr |= MCF_EDMA_TCD_CSR_E_SG;/* we are tcd sg */
696 + vtcd->dlast_sga =
697 + (u32)(ptcd + (i + 1)*sizeof(struct TCD));
698 + } else {
699 + /*this is the last sg, so enable the major int*/
700 + vtcd->csr |= MCF_EDMA_TCD_CSR_INT_MAJOR
701 + |MCF_EDMA_TCD_CSR_D_REQ;
702 + }
703 + pb++;
704 + vtcd++;
705 + }
706 +
707 + /* Now setup the firset TCD for this sg to the edma enginee */
708 + vtcd = fsl_pata_dma_tcd.pata_tcd_va;
709 +
710 + MCF_EDMA_TCD_CSR(channel) = 0x0000;
711 + MCF_EDMA_TCD_SADDR(channel) = vtcd->saddr;
712 + MCF_EDMA_TCD_DADDR(channel) = vtcd->daddr;
713 + MCF_EDMA_TCD_ATTR(channel) = vtcd->attr;
714 + MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(vtcd->soff);
715 + MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(vtcd->nbytes);
716 + MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(vtcd->slast);
717 + MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(vtcd->citer);
718 + MCF_EDMA_TCD_BITER(channel) = MCF_EDMA_TCD_BITER_BITER(vtcd->biter);
719 + MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(vtcd->doff);
720 + MCF_EDMA_TCD_DLAST_SGA(channel) =
721 + MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(vtcd->dlast_sga);
722 + MCF_EDMA_TCD_CSR(channel) |= vtcd->csr;
723 +}
724 +EXPORT_SYMBOL(mcf_edma_sg_config);
725 +
726 +/**
727 + * The zero-copy version of mcf_edma_sg_config
728 + * dma_dir : indicate teh addr direction
729 + */
730 +void mcf_edma_sglist_config(int channel, struct scatterlist *sgl, int n_elem,
731 + int dma_dir, u32 addr, u32 attr,
732 + u32 soff, u32 doff, u32 nbytes)
733 +{
734 + struct TCD *vtcd = (struct TCD *)fsl_pata_dma_tcd.pata_tcd_va;
735 + u32 ptcd = fsl_pata_dma_tcd.pata_tcd_pa;
736 + struct scatterlist *sg;
737 + u32 si;
738 +
739 + if (channel < MCF_EDMA_CHAN_ATA_RX || channel > MCF_EDMA_CHAN_ATA_TX) {
740 + printk(KERN_ERR "mcf edma sg config err, not support\n");
741 + return;
742 + }
743 + if (n_elem > MCF_EDMA_TCD_PER_CHAN) {
744 + printk(KERN_ERR "Too many SGs, please confirm.%d > %d\n",
745 + n_elem, MCF_EDMA_TCD_PER_CHAN);
746 + return;
747 + }
748 +
749 + /* build our tcd sg array */
750 + if (dma_dir == DMA_TO_DEVICE) { /* write */
751 + for_each_sg(sgl, sg, n_elem, si) {
752 + memset(vtcd, 0 , sizeof(struct TCD));
753 + vtcd->saddr = sg_dma_address(sg);
754 + vtcd->daddr = addr;
755 + vtcd->attr = attr;
756 + vtcd->soff = soff;
757 + vtcd->doff = doff;
758 + vtcd->nbytes = nbytes;
759 + vtcd->citer = vtcd->biter = sg_dma_len(sg)/nbytes;
760 +
761 + if (si != n_elem - 1) {
762 + /* we are tcd sg */
763 + vtcd->csr |= MCF_EDMA_TCD_CSR_E_SG;
764 + vtcd->dlast_sga = (u32)(ptcd + (si + 1) * \
765 + sizeof(struct TCD));
766 + } else {
767 + /*this is the last sg, so enable the major int*/
768 + vtcd->csr |= MCF_EDMA_TCD_CSR_INT_MAJOR
769 + |MCF_EDMA_TCD_CSR_D_REQ;
770 + }
771 + vtcd++;
772 + }
773 + } else {
774 + for_each_sg(sgl, sg, n_elem, si) {
775 + memset(vtcd, 0 , sizeof(struct TCD));
776 + vtcd->daddr = sg_dma_address(sg);
777 + vtcd->saddr = addr;
778 + vtcd->attr = attr;
779 + vtcd->soff = soff;
780 + vtcd->doff = doff;
781 + vtcd->nbytes = nbytes;
782 + vtcd->citer = vtcd->biter = sg_dma_len(sg)/nbytes;
783 +
784 + if (si != n_elem - 1) {
785 + /* we are tcd sg */
786 + vtcd->csr |= MCF_EDMA_TCD_CSR_E_SG;
787 + vtcd->dlast_sga = (u32)(ptcd + (si + 1) * \
788 + sizeof(struct TCD));
789 + } else {
790 + /*this is the last sg, so enable the major int*/
791 + vtcd->csr |= MCF_EDMA_TCD_CSR_INT_MAJOR
792 + |MCF_EDMA_TCD_CSR_D_REQ;
793 + }
794 + vtcd++;
795 + }
796 + }
797 +
798 + /* Now setup the firset TCD for this sg to the edma enginee */
799 + vtcd = fsl_pata_dma_tcd.pata_tcd_va;
800 +
801 + MCF_EDMA_TCD_CSR(channel) = 0x0000;
802 + MCF_EDMA_TCD_SADDR(channel) = vtcd->saddr;
803 + MCF_EDMA_TCD_DADDR(channel) = vtcd->daddr;
804 + MCF_EDMA_TCD_ATTR(channel) = vtcd->attr;
805 + MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(vtcd->soff);
806 + MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(vtcd->nbytes);
807 + MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(vtcd->slast);
808 + MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(vtcd->citer);
809 + MCF_EDMA_TCD_BITER(channel) = MCF_EDMA_TCD_BITER_BITER(vtcd->biter);
810 + MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(vtcd->doff);
811 + MCF_EDMA_TCD_DLAST_SGA(channel) =
812 + MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(vtcd->dlast_sga);
813 +
814 + MCF_EDMA_TCD_CSR(channel) |= vtcd->csr;
815 +}
816 +EXPORT_SYMBOL(mcf_edma_sglist_config);
817 +#endif
818 +/**
819 + * mcf_edma_set_tcd_params_halfirq - Set TCD AND enable half irq
820 + * @channel: channel number
821 + * @source: source address
822 + * @dest: destination address
823 + * @attr: attributes
824 + * @soff: source offset
825 + * @nbytes: number of bytes to be transfered in minor loop
826 + * @slast: last source address adjustment
827 + * @biter: beginning major loop count
828 + * @doff: destination offset
829 + * @dlast_sga: last destination address adjustment
830 + * @disable_req: disable DMA request after major loop
831 + */
832 +void
833 +mcf_edma_set_tcd_params_halfirq(int channel, u32 source, u32 dest,
834 + u32 attr, u32 soff, u32 nbytes, u32 slast,
835 + u32 biter, u32 doff, u32 dlast_sga,
836 + int disable_req)
837 +{
838 + DBG("(%d)\n", channel);
839 +
840 + if (channel < 0 || channel > MCF_EDMA_CHANNELS)
841 + return;
842 +
843 + mcf_edma_set_tcd_params(channel, source, dest,
844 + attr, soff, nbytes, slast,
845 + biter, biter, doff, dlast_sga,
846 + 1/*0*/, disable_req);
847 +
848 + if (biter < 2)
849 + printk(KERN_ERR "MCF_EDMA: Request for halfway irq denied\n");
850 +
851 + /* interrupt midway through major loop */
852 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_INT_HALF;
853 +}
854 +EXPORT_SYMBOL(mcf_edma_set_tcd_params_halfirq);
855 +
856 +/**
857 + * mcf_edma_request_channel - Request an eDMA channel
858 + * @channel: channel number. In case it is equal to EDMA_CHANNEL_ANY
859 + * it will be allocated a first free eDMA channel.
860 + * @handler: dma handler
861 + * @error_handler: dma error handler
862 + * @irq_level: irq level for the dma handler
863 + * @arg: argument to pass back
864 + * @lock: optional spinlock to hold over interrupt
865 + * @device_id: device id
866 + *
867 + * Returns allocatedd channel number if success or
868 + * a negative value if failure.
869 + */
870 +int
871 +mcf_edma_request_channel(int channel,
872 + irqreturn_t(*handler) (int, void *),
873 + void (*error_handler) (int, void *),
874 + u8 irq_level,
875 + void *arg, spinlock_t *lock, const char *device_id)
876 +{
877 + DBG("\n channel=%d\n", channel);
878 +
879 + if (mcf_edma_devp != NULL
880 + && ((channel >= 0 && channel <= MCF_EDMA_CHANNELS)
881 + || (channel == MCF_EDMA_CHANNEL_ANY))) {
882 + if (channel == MCF_EDMA_CHANNEL_ANY) {
883 + int i;
884 + for (i = 0; i < sizeof(mcf_edma_channel_pool); i++) {
885 + if (mcf_edma_devp->dma_interrupt_handlers
886 + [mcf_edma_channel_pool[i]].allocated ==
887 + 0) {
888 + channel = mcf_edma_channel_pool[i];
889 + break;
890 + }
891 + };
892 + if (channel == MCF_EDMA_CHANNEL_ANY)
893 + return -EBUSY;
894 + } else {
895 + if (mcf_edma_devp->dma_interrupt_handlers[channel].
896 + allocated)
897 + return -EBUSY;
898 + }
899 +
900 + mcf_edma_devp->dma_interrupt_handlers[channel].allocated = 1;
901 + mcf_edma_devp->dma_interrupt_handlers[channel].irq_handler =
902 + handler;
903 + mcf_edma_devp->dma_interrupt_handlers[channel].error_handler =
904 + error_handler;
905 + mcf_edma_devp->dma_interrupt_handlers[channel].arg = arg;
906 + mcf_edma_devp->dma_interrupt_handlers[channel].lock = lock;
907 + mcf_edma_devp->dma_interrupt_handlers[channel].device_id =
908 + device_id;
909 +
910 + /* Initalize interrupt controller to allow eDMA interrupts */
911 +#if defined(CONFIG_M5445X)
912 + MCF_INTC0_ICR(MCF_EDMA_INT0_CHANNEL_BASE + channel) = irq_level;
913 + MCF_INTC0_CIMR = MCF_EDMA_INT0_CHANNEL_BASE + channel;
914 +#elif defined(CONFIG_M5441X)
915 + if (channel >= 0 && channel < MCF_EDMA_INT0_END) {
916 + MCF_INTC0_ICR(MCF_EDMA_INT0_CHANNEL_BASE + channel) =
917 + irq_level;
918 + MCF_INTC0_CIMR = MCF_EDMA_INT0_CHANNEL_BASE + channel;
919 + } else if (channel >= MCF_EDMA_INT0_END &&
920 + channel < MCF_EDMA_INT1_END) {
921 + MCF_INTC1_ICR(MCF_EDMA_INT1_CHANNEL_BASE +
922 + (channel - MCF_EDMA_INT0_END)) = irq_level;
923 + MCF_INTC1_CIMR = MCF_EDMA_INT1_CHANNEL_BASE +
924 + (channel - MCF_EDMA_INT0_END);
925 + } else if (channel >= MCF_EDMA_INT1_END &&
926 + channel < MCF_EDMA_INT2_END) {
927 + MCF_INTC2_ICR(MCF_EDMA_INT2_CHANNEL_BASE) = irq_level;
928 + MCF_INTC2_CIMR = MCF_EDMA_INT2_CHANNEL_BASE;
929 + } else
930 + ERR("Bad channel number!\n");
931 +#endif
932 + return channel;
933 + }
934 + return -EINVAL;
935 +}
936 +EXPORT_SYMBOL(mcf_edma_request_channel);
937 +
938 +/**
939 + * mcf_edma_set_callback - Update the channel callback/arg
940 + * @channel: channel number
941 + * @handler: dma handler
942 + * @error_handler: dma error handler
943 + * @arg: argument to pass back
944 + *
945 + * Returns 0 if success or a negative value if failure
946 + */
947 +int
948 +mcf_edma_set_callback(int channel,
949 + irqreturn_t(*handler) (int, void *),
950 + void (*error_handler) (int, void *), void *arg)
951 +{
952 + DBG("\n");
953 +
954 + if (mcf_edma_devp != NULL && channel >= 0
955 + && channel <= MCF_EDMA_CHANNELS
956 + && mcf_edma_devp->dma_interrupt_handlers[channel].allocated) {
957 + mcf_edma_devp->dma_interrupt_handlers[channel].irq_handler =
958 + handler;
959 + mcf_edma_devp->dma_interrupt_handlers[channel].error_handler =
960 + error_handler;
961 + mcf_edma_devp->dma_interrupt_handlers[channel].arg = arg;
962 + return 0;
963 + }
964 + return -EINVAL;
965 +}
966 +EXPORT_SYMBOL(mcf_edma_set_callback);
967 +
968 +/**
969 + * mcf_edma_free_channel - Free the edma channel
970 + * @channel: channel number
971 + * @arg: argument created with
972 + *
973 + * Returns 0 if success or a negative value if failure
974 + */
975 +int
976 +mcf_edma_free_channel(int channel, void *arg)
977 +{
978 + DBG("\n");
979 +
980 + if (mcf_edma_devp != NULL && channel >= 0
981 + && channel <= MCF_EDMA_CHANNELS) {
982 + if (mcf_edma_devp->dma_interrupt_handlers[channel].allocated) {
983 +#if 1
984 + if (mcf_edma_devp->dma_interrupt_handlers[channel].
985 + arg != arg)
986 + return -EBUSY;
987 +#endif
988 +
989 + mcf_edma_devp->dma_interrupt_handlers[channel].
990 + allocated = 0;
991 + mcf_edma_devp->dma_interrupt_handlers[channel].arg =
992 + NULL;
993 + mcf_edma_devp->dma_interrupt_handlers[channel].
994 + irq_handler = NULL;
995 + mcf_edma_devp->dma_interrupt_handlers[channel].
996 + error_handler = NULL;
997 + mcf_edma_devp->dma_interrupt_handlers[channel].lock =
998 + NULL;
999 + }
1000 +
1001 + /* make sure error interrupt is disabled */
1002 + MCF_EDMA_CEEI = MCF_EDMA_CEEI_CEEI(channel);
1003 +
1004 + return 0;
1005 + }
1006 + return -EINVAL;
1007 +}
1008 +EXPORT_SYMBOL(mcf_edma_free_channel);
1009 +
1010 +/**
1011 + * mcf_edma_cleanup - cleanup driver allocated resources
1012 + */
1013 +static void
1014 +mcf_edma_cleanup(void)
1015 +{
1016 + dev_t devno;
1017 + int i;
1018 +
1019 + DBG("\n");
1020 +
1021 + /* disable all error ints */
1022 + MCF_EDMA_CEEI = MCF_EDMA_CEEI_CAEE;
1023 +
1024 + /* free interrupts/memory */
1025 + if (mcf_edma_devp) {
1026 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1027 + #if defined(CONFIG_M5445X)
1028 + free_irq(MCF_EDMA_INT0_BASE + i, mcf_edma_devp);
1029 + #elif defined(CONFIG_M5441X)
1030 + if (i >= 0 && i < MCF_EDMA_INT0_END)
1031 + free_irq(MCF_EDMA_INT0_BASE + i, mcf_edma_devp);
1032 + else if (i >= MCF_EDMA_INT0_END &&
1033 + i <= MCF_EDMA_INT1_END)
1034 + free_irq(MCF_EDMA_INT1_BASE +
1035 + (i - MCF_EDMA_INT0_END), mcf_edma_devp);
1036 + else if (i >= MCF_EDMA_INT1_END &&
1037 + i < MCF_EDMA_INT2_END) {
1038 + free_irq(MCF_EDMA_INT2_BASE, mcf_edma_devp);
1039 + break;
1040 + } else {
1041 + ERR("Bad irq number!\n");
1042 + return;
1043 + }
1044 + #endif
1045 + }
1046 +
1047 + free_irq(MCF_EDMA_INT0_BASE + MCF_EDMA_INT_ERR, mcf_edma_devp);
1048 + cdev_del(&mcf_edma_devp->cdev);
1049 + kfree(mcf_edma_devp);
1050 + }
1051 +
1052 + /* unregister character device */
1053 + devno = MKDEV(mcf_edma_major, 0);
1054 + unregister_chrdev_region(devno, 1);
1055 +}
1056 +
1057 +/**
1058 + * mcf_edma_dump_channel - dump a channel information
1059 + */
1060 +void
1061 +mcf_edma_dump_channel(int channel)
1062 +{
1063 + printk(KERN_DEBUG "EDMA Channel %d\n", channel);
1064 + printk(KERN_DEBUG " TCD Base = 0x%x\n",
1065 + (int)&MCF_EDMA_TCD_SADDR(channel));
1066 + printk(KERN_DEBUG " SRCADDR = 0x%lx\n",
1067 + MCF_EDMA_TCD_SADDR(channel));
1068 + printk(KERN_DEBUG " SRCOFF = 0x%x\n",
1069 + MCF_EDMA_TCD_SOFF(channel));
1070 + printk(KERN_DEBUG " XFR ATTRIB = 0x%x\n",
1071 + MCF_EDMA_TCD_ATTR(channel));
1072 + printk(KERN_DEBUG " SRCLAST = 0x%lx\n",
1073 + MCF_EDMA_TCD_SLAST(channel));
1074 + printk(KERN_DEBUG " DSTADDR = 0x%lx\n",
1075 + MCF_EDMA_TCD_DADDR(channel));
1076 + printk(KERN_DEBUG " MINOR BCNT = 0x%lx\n",
1077 + MCF_EDMA_TCD_NBYTES(channel));
1078 + printk(KERN_DEBUG " CUR_LOOP_CNT = 0x%x\n",
1079 + MCF_EDMA_TCD_CITER(channel)&0x1ff);
1080 + printk(KERN_DEBUG " BEG_LOOP_CNT = 0x%x\n",
1081 + MCF_EDMA_TCD_BITER(channel)&0x1ff);
1082 + printk(KERN_DEBUG " STATUS = 0x%x\n",
1083 + MCF_EDMA_TCD_CSR(channel));
1084 +
1085 +}
1086 +EXPORT_SYMBOL(mcf_edma_dump_channel);
1087 +
1088 +#ifdef CONFIG_PROC_FS
1089 +/*
1090 + * proc file system support
1091 + */
1092 +
1093 +#define FREE_CHANNEL "free"
1094 +#define DEVICE_UNKNOWN "device unknown"
1095 +
1096 +/**
1097 + * mcf_edma_proc_show - print out proc info
1098 + * @m: seq_file
1099 + * @v:
1100 + */
1101 +static int
1102 +mcf_edma_proc_show(struct seq_file *m, void *v)
1103 +{
1104 + int i;
1105 +
1106 + if (mcf_edma_devp == NULL)
1107 + return 0;
1108 +
1109 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1110 + if (mcf_edma_devp->dma_interrupt_handlers[i].allocated) {
1111 + if (mcf_edma_devp->dma_interrupt_handlers[i].device_id)
1112 + seq_printf(m, "%2d: %s\n", i,
1113 + mcf_edma_devp->
1114 + dma_interrupt_handlers[i].
1115 + device_id);
1116 + else
1117 + seq_printf(m, "%2d: %s\n", i, DEVICE_UNKNOWN);
1118 + } else
1119 + seq_printf(m, "%2d: %s\n", i, FREE_CHANNEL);
1120 + }
1121 + return 0;
1122 +}
1123 +
1124 +/**
1125 + * mcf_edma_proc_open - open the proc file
1126 + * @inode: inode ptr
1127 + * @file: file ptr
1128 + */
1129 +static int
1130 +mcf_edma_proc_open(struct inode *inode, struct file *file)
1131 +{
1132 + return single_open(file, mcf_edma_proc_show, NULL);
1133 +}
1134 +
1135 +static const struct file_operations mcf_edma_proc_operations = {
1136 + .open = mcf_edma_proc_open,
1137 + .read = seq_read,
1138 + .llseek = seq_lseek,
1139 + .release = single_release,
1140 +};
1141 +
1142 +/**
1143 + * mcf_edma_proc_init - initialize proc filesystem
1144 + */
1145 +static int __init
1146 +mcf_edma_proc_init(void)
1147 +{
1148 + struct proc_dir_entry *e;
1149 +
1150 + e = create_proc_entry("edma", 0, NULL);
1151 + if (e)
1152 + e->proc_fops = &mcf_edma_proc_operations;
1153 +
1154 + return 0;
1155 +}
1156 +
1157 +#endif
1158 +
1159 +/**
1160 + * mcf_edma_init - eDMA module init
1161 + */
1162 +static int __init
1163 +mcf_edma_init(void)
1164 +{
1165 + dev_t dev;
1166 + int result;
1167 + int i;
1168 +#ifdef CONFIG_M54455
1169 + u32 offset;
1170 +#endif
1171 +
1172 +#if defined(CONFIG_M5441X)
1173 + /* edma group priority, default grp0 > grp1 > grp2 > grp3 */
1174 + u32 grp0_pri = MCF_EDMA_CR_GRP0PRI(0x00);
1175 + u32 grp1_pri = MCF_EDMA_CR_GRP1PRI(0x01);
1176 + u32 grp2_pri = MCF_EDMA_CR_GRP2PRI(0x02);
1177 + u32 grp3_pri = MCF_EDMA_CR_GRP3PRI(0x03);
1178 +#endif
1179 +
1180 + DBG("Entry\n");
1181 +
1182 + /* allocate free major number */
1183 + result =
1184 + alloc_chrdev_region(&dev, MCF_EDMA_DEV_MINOR, 1,
1185 + MCF_EDMA_DRIVER_NAME);
1186 + if (result < 0) {
1187 + ERR("Error %d can't get major number.\n", result);
1188 + return result;
1189 + }
1190 + mcf_edma_major = MAJOR(dev);
1191 +
1192 + /* allocate device driver structure */
1193 + mcf_edma_devp = kmalloc(sizeof(struct mcf_edma_dev), GFP_KERNEL);
1194 + if (!mcf_edma_devp) {
1195 + result = -ENOMEM;
1196 + goto fail;
1197 + }
1198 +
1199 + /* init handlers (no handlers for beginning) */
1200 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1201 + mcf_edma_devp->dma_interrupt_handlers[i].irq_handler = NULL;
1202 + mcf_edma_devp->dma_interrupt_handlers[i].error_handler = NULL;
1203 + mcf_edma_devp->dma_interrupt_handlers[i].arg = NULL;
1204 + mcf_edma_devp->dma_interrupt_handlers[i].allocated = 0;
1205 + mcf_edma_devp->dma_interrupt_handlers[i].lock = NULL;
1206 + mcf_edma_devp->dma_interrupt_handlers[i].device_id = NULL;
1207 + MCF_EDMA_TCD_CSR(i) = 0x0000;
1208 + }
1209 +
1210 + /* register char device */
1211 + cdev_init(&mcf_edma_devp->cdev, &mcf_edma_fops);
1212 + mcf_edma_devp->cdev.owner = THIS_MODULE;
1213 + mcf_edma_devp->cdev.ops = &mcf_edma_fops;
1214 + result = cdev_add(&mcf_edma_devp->cdev, dev, 1);
1215 + if (result) {
1216 + ERR("Error %d adding coldfire-dma device.\n", result);
1217 + result = -ENODEV;
1218 + goto fail;
1219 + }
1220 +
1221 + /* request/enable irq for each eDMA channel */
1222 +#if defined(CONFIG_M5445X)
1223 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1224 + result = request_irq(MCF_EDMA_INT0_BASE + i,
1225 + mcf_edma_isr, IRQF_DISABLED,
1226 + MCF_EDMA_DRIVER_NAME, mcf_edma_devp);
1227 + if (result) {
1228 + ERR("Cannot request irq %d\n",
1229 + (MCF_EDMA_INT0_BASE + i));
1230 + result = -EBUSY;
1231 + goto fail;
1232 + }
1233 + }
1234 +#elif defined(CONFIG_M5441X)
1235 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1236 + if (i >= 0 && i < MCF_EDMA_INT0_END) {
1237 + result = request_irq(MCF_EDMA_INT0_BASE + i,
1238 + mcf_edma_isr, IRQF_DISABLED,
1239 + MCF_EDMA_DRIVER_NAME,
1240 + mcf_edma_devp);
1241 +
1242 + if (result) {
1243 + ERR("Cannot request irq %d\n",
1244 + (MCF_EDMA_INT0_BASE + i));
1245 + result = -EBUSY;
1246 + goto fail;
1247 + }
1248 + } else if (i >= MCF_EDMA_INT0_END && i < MCF_EDMA_INT1_END) {
1249 + result = request_irq(MCF_EDMA_INT1_BASE +
1250 + (i - MCF_EDMA_INT0_END),
1251 + mcf_edma_isr, IRQF_DISABLED,
1252 + MCF_EDMA_DRIVER_NAME,
1253 + mcf_edma_devp);
1254 +
1255 + if (result) {
1256 + ERR("Cannot request irq %d\n",
1257 + (MCF_EDMA_INT1_BASE +
1258 + (i - MCF_EDMA_INT0_END)));
1259 + result = -EBUSY;
1260 + goto fail;
1261 + }
1262 + } else if (i >= MCF_EDMA_INT1_END && MCF_EDMA_INT2_END) {
1263 + result = request_irq(MCF_EDMA_INT2_BASE,
1264 + mcf_edma_isr, IRQF_DISABLED,
1265 + MCF_EDMA_DRIVER_NAME,
1266 + mcf_edma_devp);
1267 + if (result) {
1268 + ERR("Cannot request irq %d\n",
1269 + MCF_EDMA_INT2_BASE);
1270 + result = -EBUSY;
1271 + goto fail;
1272 + }
1273 + break;
1274 + } else {
1275 + ERR(" Cannot request irq because of wrong number!\n");
1276 + result = -EBUSY;
1277 + goto fail;
1278 + }
1279 + }
1280 +#endif
1281 +
1282 + /* request error interrupt */
1283 + result = request_irq(MCF_EDMA_INT0_BASE + MCF_EDMA_INT_ERR,
1284 + mcf_edma_error_isr, IRQF_DISABLED,
1285 + MCF_EDMA_DRIVER_NAME, mcf_edma_devp);
1286 + if (result) {
1287 + ERR("Cannot request irq %d\n",
1288 + (MCF_EDMA_INT0_BASE + MCF_EDMA_INT_ERR));
1289 + result = -EBUSY;
1290 + goto fail;
1291 + }
1292 +
1293 +#if defined(CONFIG_M5445X)
1294 + MCF_EDMA_CR = 0;
1295 +#elif defined(CONFIG_M5441X)
1296 + MCF_EDMA_CR = (0 | grp0_pri | grp1_pri | grp2_pri | grp3_pri);
1297 + DBG("MCF_EDMA_CR = %lx\n", MCF_EDMA_CR);
1298 +#endif
1299 +
1300 +#ifdef CONFIG_M54455
1301 + fsl_pata_dma_tcd.pata_tcd_va = (struct TCD *) dma_alloc_coherent(NULL,
1302 + MCF_EDMA_TCD_PER_CHAN + 1,
1303 + &fsl_pata_dma_tcd.pata_tcd_pa,
1304 + GFP_KERNEL);
1305 +
1306 + if (!fsl_pata_dma_tcd.pata_tcd_va) {
1307 + printk(KERN_INFO "MCF eDMA alllocate tcd memeory failed\n");
1308 + goto fail;
1309 + }
1310 +
1311 +
1312 + offset = (fsl_pata_dma_tcd.pata_tcd_pa & (sizeof(struct TCD)-1)) ;
1313 + if (offset) {
1314 + /*
1315 + * up align the addr to 32B to match the eDMA enginee require,
1316 + * ie. sizeof tcd boundary
1317 + * */
1318 + printk(KERN_INFO "pata tcd original:pa-%x[%x]\n",
1319 + fsl_pata_dma_tcd.pata_tcd_pa,
1320 + (u32)fsl_pata_dma_tcd.pata_tcd_va);
1321 +
1322 + fsl_pata_dma_tcd.pata_tcd_pa += sizeof(struct TCD) - offset;
1323 + fsl_pata_dma_tcd.pata_tcd_va += sizeof(struct TCD) - offset;
1324 +
1325 + printk(KERN_INFO "pata tcd realigned:pa-%x[%x]\n",
1326 + fsl_pata_dma_tcd.pata_tcd_pa,
1327 + (u32)fsl_pata_dma_tcd.pata_tcd_va);
1328 + }
1329 +#endif
1330 +#ifdef CONFIG_PROC_FS
1331 + mcf_edma_proc_init();
1332 +#endif
1333 +
1334 + INFO("Initialized successfully\n");
1335 + return 0;
1336 +fail:
1337 + mcf_edma_cleanup();
1338 + return result;
1339 +}
1340 +
1341 +/**
1342 + * mcf_edma_exit - eDMA module exit
1343 + */
1344 +static void __exit
1345 +mcf_edma_exit(void)
1346 +{
1347 + mcf_edma_cleanup();
1348 +}
1349 +
1350 +#ifdef CONFIG_COLDFIRE_EDMA_MODULE
1351 +module_init(mcf_edma_init);
1352 +module_exit(mcf_edma_exit);
1353 +#else
1354 +/* get us in early */
1355 +postcore_initcall(mcf_edma_init);
1356 +#endif
1357 +
1358 +MODULE_DESCRIPTION(MCF_EDMA_DRIVER_INFO);
1359 +MODULE_AUTHOR(MCF_EDMA_DRIVER_AUTHOR);
1360 +MODULE_LICENSE(MCF_EDMA_DRIVER_LICENSE);
1361 --- /dev/null
1362 +++ b/drivers/dma/mcf_edma_test.c
1363 @@ -0,0 +1,276 @@
1364 +/*
1365 + * mcf_edma_test.c - simple test/example module for Coldfire eDMA.
1366 + *
1367 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1368 + * Author: Andrey Butok
1369 + *
1370 + * This program is free software; you can redistribute it and/or modify it
1371 + * under the terms of the GNU General Public License as published by the
1372 + * Free Software Foundation; either version 2 of the License, or (at your
1373 + * option) any later version.
1374 + *
1375 + * This program is distributed in the hope that it will be useful,
1376 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1377 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1378 + * GNU General Public License for more details.
1379 + *
1380 + * You should have received a copy of the GNU General Public License
1381 + * along with this program; if not, write to the Free Software
1382 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1383 + *
1384 + ***************************************************************************
1385 + * Changes:
1386 + * v0.001 29 February 2008 Andrey Butok
1387 + * Initial Release
1388 + *
1389 + * NOTE: This module tests eDMA driver performing
1390 + * a simple memory to memory transfer with a 32 bit
1391 + * source and destination transfer size that generates
1392 + * an interrupt when the transfer is complete.
1393 + */
1394 +
1395 +#include <linux/dma-mapping.h>
1396 +#include <linux/init.h>
1397 +#include <linux/fs.h>
1398 +#include <linux/cdev.h>
1399 +#include <linux/seq_file.h>
1400 +#include <linux/proc_fs.h>
1401 +#include <asm/mcfsim.h>
1402 +#include <asm/coldfire.h>
1403 +#include <asm/mcf_edma.h>
1404 +#include <asm/cacheflush.h>
1405 +
1406 +#define MCF_EDMA_TEST_DRIVER_VERSION "Revision: 0.001"
1407 +#define MCF_EDMA_TEST_DRIVER_AUTHOR \
1408 + "Freescale Semiconductor Inc, Andrey Butok"
1409 +#define MCF_EDMA_TEST_DRIVER_DESC \
1410 + "Simple testing module for Coldfire eDMA "
1411 +#define MCF_EDMA_TEST_DRIVER_INFO \
1412 + MCF_EDMA_TEST_DRIVER_VERSION " " MCF_EDMA_TEST_DRIVER_DESC
1413 +#define MCF_EDMA_TEST_DRIVER_LICENSE "GPL"
1414 +#define MCF_EDMA_TEST_DRIVER_NAME "mcf_edma_test"
1415 +
1416 +#ifndef TRUE
1417 +#define TRUE 1
1418 +#define FALSE 0
1419 +#endif
1420 +
1421 +#define TEST_HALFIRQ
1422 +
1423 +/* Global variable used to signal main process when interrupt is recognized */
1424 +static volatile int mcf_edma_test_interrupt;
1425 +volatile int *mcf_edma_test_interrupt_p =
1426 + (volatile int *) &mcf_edma_test_interrupt;
1427 +
1428 +/********************************************************************/
1429 +static irqreturn_t
1430 +mcf_edma_test_handler(int channel, void *dev_id)
1431 +{
1432 + int done = mcf_edma_check_done(channel);
1433 +
1434 + /* Clear interrupt flag */
1435 + mcf_edma_confirm_interrupt_handled(channel);
1436 +
1437 + if (done) {
1438 + printk(KERN_INFO "DMA Finished\n");
1439 +
1440 + /* Set interrupt status flag to TRUE */
1441 + mcf_edma_test_interrupt = TRUE;
1442 + } else {
1443 + printk(KERN_INFO "DMA Halfway Done\n");
1444 +
1445 + /* restart DMA. */
1446 + mcf_edma_confirm_halfirq(channel);
1447 + }
1448 +
1449 + return IRQ_HANDLED;
1450 +}
1451 +
1452 +static void
1453 +mcf_edma_test_error_handler(int channel, void *dev_id)
1454 +{
1455 + printk(KERN_INFO "DMA ERROR: Channel = %d\n", channel);
1456 + printk(KERN_INFO " EDMA_ES = 0x%lx\n", (MCF_EDMA_ES));
1457 + mcf_edma_dump_channel(channel);
1458 +}
1459 +
1460 +/********************************************************************/
1461 +
1462 +int
1463 +mcf_edma_test_block_compare(u8 *block1, u8 *block2, u32 size)
1464 +{
1465 + u32 i;
1466 +
1467 + for (i = 0; i < (size); i++) {
1468 + if ((*(u8 *) (block1 + i)) != (*(u8 *) (block2 + i))) {
1469 + printk(KERN_INFO "Data Mismatch index=0x%x len=0x%x "
1470 + "block1=0x%p block2=0x%p\n",
1471 + i, size, block1, block2);
1472 + return FALSE;
1473 + }
1474 + }
1475 +
1476 + return TRUE;
1477 +}
1478 +
1479 +/********************************************************************/
1480 +
1481 +void
1482 +mcf_edma_test_run(void)
1483 +{
1484 + u16 byte_count;
1485 + u32 i, j;
1486 + u8 *start_address;
1487 + u8 *dest_address;
1488 + u32 test_data;
1489 + int channel;
1490 + u32 allocated_channels_low = 0;
1491 + u32 allocated_channels_high = 0;
1492 +
1493 + printk(KERN_INFO "\n===============================================\n");
1494 + printk(KERN_INFO "\nStarting eDMA transfer test!\n");
1495 +
1496 + /* Initialize test variables */
1497 + byte_count = 0x2000;
1498 + test_data = 0xA5A5A5A5;
1499 +
1500 + /* DMA buffer must be from GFP_DMA zone, so it will not be cached */
1501 + start_address = kmalloc(byte_count, GFP_DMA);
1502 + if (start_address == NULL) {
1503 + printk(KERN_INFO MCF_EDMA_TEST_DRIVER_NAME
1504 + ": failed to allocate DMA[%d] buffer\n", byte_count);
1505 + goto err_out;
1506 + }
1507 + dest_address = kmalloc(byte_count, /*GFP_KERNEL*/GFP_DMA);
1508 + if (dest_address == NULL) {
1509 + printk(KERN_INFO MCF_EDMA_TEST_DRIVER_NAME
1510 + ": failed to allocate DMA[%d] buffer\n", byte_count);
1511 + goto err_free_mem;
1512 + }
1513 +
1514 + /* Test all automatically allocated DMA channels. The test data is
1515 + * complemented at the end of the loop, so that the testData value
1516 + * isn't the same twice in a row */
1517 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1518 + /* request eDMA channel */
1519 + channel = mcf_edma_request_channel(MCF_EDMA_CHANNEL_ANY,
1520 + mcf_edma_test_handler,
1521 + mcf_edma_test_error_handler,
1522 + 0x6,
1523 + NULL,
1524 + NULL,
1525 + MCF_EDMA_TEST_DRIVER_NAME);
1526 + if (channel < 0)
1527 + goto test_end;
1528 +
1529 +
1530 + if (channel >= 0 && channel < 32)
1531 + allocated_channels_low |= (1 << channel);
1532 + else if (channel >= 32 && channel < 64)
1533 + allocated_channels_high |= (1 << (channel - 32));
1534 +
1535 + /* Initialize data for DMA to move */
1536 + for (j = 0; j < byte_count; j = j + 4) {
1537 + *((u32 *) (start_address + j)) = test_data;
1538 + *((u32 *) (dest_address + j)) = ~test_data;
1539 + }
1540 +
1541 + /* Clear interrupt status indicator */
1542 + mcf_edma_test_interrupt = FALSE;
1543 +
1544 + /* Configure DMA Channel TCD */
1545 +#ifndef TEST_HALFIRQ
1546 + /* regular irq on completion */
1547 + mcf_edma_set_tcd_params(channel,
1548 + (u32)virt_to_phys(start_address),
1549 + (u32)virt_to_phys(dest_address),
1550 + (0 | MCF_EDMA_TCD_ATTR_SSIZE_32BIT |
1551 + MCF_EDMA_TCD_ATTR_DSIZE_32BIT), 0x04,
1552 + byte_count, 0x0, 1, 1, 0x04, 0x0, 0x1,
1553 + 0x0);
1554 +#else
1555 + /* half completion irq */
1556 + mcf_edma_set_tcd_params_halfirq(channel,
1557 + (u32)virt_to_phys(start_address),
1558 + (u32)virt_to_phys(dest_address),
1559 + (MCF_EDMA_TCD_ATTR_SSIZE_32BIT |
1560 + MCF_EDMA_TCD_ATTR_DSIZE_32BIT),
1561 + 0x04, /* soff */
1562 + byte_count/2, /* bytes/loop */
1563 + 0x0, /* slast */
1564 + 2, /* loop count */
1565 + 0x04, /* doff */
1566 + 0x0, /* dlast_sga */
1567 + 0x0); /* req dis */
1568 +#endif
1569 +
1570 + printk(KERN_INFO "DMA Channel %d Bytes = 0x%x\n",
1571 + channel, byte_count);
1572 + /* Start DMA. */
1573 + mcf_edma_start_transfer(channel);
1574 +
1575 + printk(KERN_INFO "DMA channel %d started.\n", channel);
1576 +
1577 + /* Wait for DMA to complete */
1578 + while (!*mcf_edma_test_interrupt_p)
1579 + ;
1580 +
1581 + /* Test data */
1582 + if (mcf_edma_test_block_compare
1583 + (start_address, dest_address, byte_count))
1584 + printk(KERN_INFO "Data are moved correctly.\n");
1585 + else
1586 + printk(KERN_INFO "ERROR!!! Data error!\n");
1587 +
1588 + printk(KERN_INFO "DMA channel %d test complete.\n", channel);
1589 + printk(KERN_INFO "-------------------------------\n");
1590 +
1591 + /* Complement test data so next channel test does not
1592 + * use same values */
1593 + test_data = ~test_data;
1594 + }
1595 +
1596 +test_end:
1597 + printk(KERN_INFO "All tests are complete\n\n");
1598 + printk(KERN_INFO
1599 + "It has been automatically allocated %d eDMA channels:\n", i);
1600 + for (i = 0; i < MCF_EDMA_CHANNELS; i++) {
1601 + if ((allocated_channels_low & (1 << i)) ||
1602 + (allocated_channels_high & (1 << (i - 32)))) {
1603 + printk(KERN_INFO "%d,\n", i);
1604 + mcf_edma_free_channel(i, NULL);
1605 + }
1606 + }
1607 + printk(KERN_INFO "===============================================\n\n");
1608 +
1609 + kfree(dest_address);
1610 +err_free_mem:
1611 + kfree(start_address);
1612 +err_out:
1613 + return;
1614 +}
1615 +
1616 +/********************************************************************/
1617 +
1618 +static int __init
1619 +mcf_edma_test_init(void)
1620 +{
1621 + mcf_edma_test_run();
1622 +
1623 + /* We intentionaly return -EAGAIN to prevent keeping
1624 + * the module. It does all its work from init()
1625 + * and doesn't offer any runtime functionality */
1626 + return -EAGAIN;
1627 +}
1628 +
1629 +static void __exit
1630 +mcf_edma_test_exit(void)
1631 +{
1632 +}
1633 +
1634 +module_init(mcf_edma_test_init);
1635 +module_exit(mcf_edma_test_exit);
1636 +
1637 +MODULE_DESCRIPTION(MCF_EDMA_TEST_DRIVER_INFO);
1638 +MODULE_AUTHOR(MCF_EDMA_TEST_DRIVER_AUTHOR);
1639 +MODULE_LICENSE(MCF_EDMA_TEST_DRIVER_LICENSE);
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