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[openwrt/staging/chunkeey.git] / target / linux / coldfire / patches / 008-Add-DSPI-driver-support-for-MCF5445x-MCF5441x.patch
1 From ec1abf6de20d80b8a2c43f747b5a05aba0ecd3b2 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Thu, 4 Aug 2011 09:59:40 +0800
4 Subject: [PATCH 08/52] Add DSPI driver support for MCF5445x/MCF5441x
5
6 Add DSPI driver support for MCF5445x and MCF5441x.
7
8 Signed-off-by: Alison Wang <b18965@freescale.com>
9 ---
10 arch/m68k/include/asm/mcfqspi.h | 5 +
11 drivers/spi/Kconfig | 35 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/dspi_mcf.c | 1486 +++++++++++++++++++++++++++++++++++++++
14 4 files changed, 1527 insertions(+), 0 deletions(-)
15 create mode 100644 drivers/spi/dspi_mcf.c
16
17 --- a/arch/m68k/include/asm/mcfqspi.h
18 +++ b/arch/m68k/include/asm/mcfqspi.h
19 @@ -2,6 +2,7 @@
20 * Definitions for Freescale Coldfire QSPI module
21 *
22 * Copyright 2010 Steven King <sfking@fdwdc.com>
23 + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
24 *
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License version 2
27 @@ -21,6 +22,10 @@
28 #ifndef mcfqspi_h
29 #define mcfqspi_h
30
31 +#define QSPI_CS_INIT 0x01
32 +#define QSPI_CS_ASSERT 0x02
33 +#define QSPI_CS_DROP 0x04
34 +
35 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
36 #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
37 #elif defined(CONFIG_M5249)
38 --- a/drivers/spi/Kconfig
39 +++ b/drivers/spi/Kconfig
40 @@ -154,6 +154,41 @@ config SPI_GPIO
41 GPIO operations, you should be able to leverage that for better
42 speed with a custom version of this driver; see the source code.
43
44 +config SPI_DSPI
45 + tristate "Coldfire DSPI"
46 + depends on SPI_MASTER && COLDFIRE
47 + help
48 + SPI driver for Coldfire DSPI driver only.
49 +
50 +choice
51 + prompt "Selsect DSPI controller"
52 + depends on SPI_DSPI && M5441X
53 + default DSPI0
54 +
55 +config DSPI0
56 + bool "DSPI0 controller"
57 + help
58 + DSPI0 controller on m5441x platform
59 +
60 +config DSP0_SBF_CS
61 + hex
62 + prompt "Chip select for serial flash on DSPI0"
63 + depends on DSPI0 && M5441X
64 + default 1
65 +
66 +config DSPI1
67 + bool "DSPI1 controller"
68 + help
69 + DSPI1 controller on m5441x platform
70 +endchoice
71 +
72 +config SPI_COLDFIRE_DSPI_EDMA
73 + boolean "Coldfire DSPI master driver uses eDMA"
74 + depends on SPI_MASTER && COLDFIRE && SPI_DSPI && COLDFIRE_EDMA
75 + default n
76 + help
77 + Say "yes" if you want DSPI master driver to use eDMA for transfers.
78 +
79 config SPI_IMX_VER_IMX1
80 def_bool y if SOC_IMX1
81
82 --- a/drivers/spi/Makefile
83 +++ b/drivers/spi/Makefile
84 @@ -23,6 +23,7 @@ dw_spi_midpci-objs := dw_spi_pci.o dw_
85 obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
86 obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
87 obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
88 +obj-$(CONFIG_SPI_DSPI) += dspi_mcf.o
89 obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o
90 obj-$(CONFIG_SPI_IMX) += spi_imx.o
91 obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
92 --- /dev/null
93 +++ b/drivers/spi/dspi_mcf.c
94 @@ -0,0 +1,1486 @@
95 +/*
96 + * dspi_mcf.c - DSPI controller for ColdFire processors
97 + *
98 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
99 + * Author: Matt Waddel Matt.Waddel@freescale.com
100 + * Kurt Mahan kmahan@freescale.com
101 + * Wang Huan <b18965@freescale.com>
102 + * Jingchang Lu <b22599@freescale.com>
103 + * Lanttor.Guo@freescale.com
104 + *
105 + * Based on spi_coldfire.c
106 + *
107 + * This program is free software; you can redistribute it and/or modify it
108 + * under the terms of the GNU General Public License as published by the
109 + * Free Software Foundation; either version 2 of the License, or (at your
110 + * option) any later version.
111 + *
112 + * This program is distributed in the hope that it will be useful,
113 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
114 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
115 + * GNU General Public License for more details.
116 + *
117 + * You should have received a copy of the GNU General Public License
118 + * along with this program; if not, write to the Free Software
119 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
120 + *
121 + ***************************************************************************
122 + * Changes:
123 + * v0.003 M5301x support.
124 + * v0.002 M547x/M548x support.
125 + * v0.001 Initial version. Coldfire DSPI master driver.
126 + ****************************************************************************/
127 +
128 +/*
129 + * Includes
130 + */
131 +
132 +#include <linux/init.h>
133 +#include <linux/module.h>
134 +#include <linux/device.h>
135 +#include <linux/interrupt.h>
136 +#include <linux/platform_device.h>
137 +#include <linux/spi/spi.h>
138 +#include <linux/workqueue.h>
139 +#include <linux/delay.h>
140 +#include <asm/mcfsim.h>
141 +#include <asm/mcfqspi.h>
142 +#include <asm/coldfire.h>
143 +#include <linux/io.h>
144 +#include <asm/mcfdspi.h>
145 +#include <linux/dma-mapping.h>
146 +
147 +#include <linux/time.h>
148 +#undef DSPI_COLDFIRE_DEBUG
149 +
150 +#ifdef DSPI_COLDFIRE_DEBUG
151 +#define DBG(fmt, args...) \
152 + printk(KERN_INFO "[%s] " fmt , __func__, ## args)
153 +#else
154 +#define DBG(fmt, args...) do {} while (0)
155 +#endif
156 +
157 +#if defined(CONFIG_M5445X)
158 +#include <asm/mcf5445x_dspi.h>
159 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
160 + #include <asm/mcf5445x_edma.h>
161 +#endif
162 +#elif defined(CONFIG_M5441X)
163 +#include <asm/mcf5441x_dspi.h>
164 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
165 +#include <asm/mcf5441x_edma.h>
166 +#endif
167 +#endif
168 +
169 +#if defined(CONFIG_M547X_8X)
170 +#include <asm/virtconvert.h>
171 +#include <asm/m5485dspi.h>
172 +#endif
173 +
174 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
175 +#include <asm/mcf_edma.h>
176 +#define SPI_DSPI_EDMA
177 +#define EDMA_BUFSIZE_KMALLOC (DSPI_FIFO_SIZE*4)
178 +#if defined(CONFIG_M5445X)
179 +#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI_RX
180 +#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI_TX
181 +#elif defined(CONFIG_M5441X)
182 +#if defined(CONFIG_DSPI0)
183 +#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI0_RX
184 +#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI0_TX
185 +#elif defined(CONFIG_DSPI1)
186 +#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI1_RX
187 +#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI1_TX
188 +#endif
189 +#endif
190 +
191 +#undef NEW_DMA_METHOD
192 +
193 +#endif
194 +
195 +#define DSPI_BITS MCF_DSPI_DCTAR_FMSZ(0xF)
196 +#define DSPI_BITS_16 MCF_DSPI_DCTAR_FMSZ(0xF)
197 +#define DSPI_BITS_8 MCF_DSPI_DCTAR_FMSZ(0x7)
198 +
199 +#ifdef NEW_DMA_METHOD
200 +#define DSPI_FIFO_SIZE (16)
201 +#else
202 +#define DSPI_FIFO_SIZE 16
203 +#endif
204 +
205 +#define DRIVER_NAME "Coldfire DSPI"
206 +
207 +/****************************************************************************/
208 +
209 +/*
210 + * Local constants and macros
211 + */
212 +
213 +#define START_STATE ((void *)0)
214 +#define RUNNING_STATE ((void *)1)
215 +#define DONE_STATE ((void *)2)
216 +#define ERROR_STATE ((void *)-1)
217 +
218 +#define QUEUE_RUNNING 0
219 +#define QUEUE_STOPPED 1
220 +#define TRAN_STATE_RX_VOID 0x01
221 +#define TRAN_STATE_TX_VOID 0x02
222 +#define TRAN_STATE_WORD_ODD_NUM 0x04
223 +/****************************************************************************/
224 +
225 +/*
226 + * Local Data Structures
227 + */
228 +
229 +struct DSPI_MCR {
230 + unsigned master:1;
231 + unsigned cont_scke:1;
232 + unsigned dconf:2;
233 + unsigned frz:1;
234 + unsigned mtfe:1;
235 + unsigned pcsse:1;
236 + unsigned rooe:1;
237 + unsigned pcsis:8;
238 + unsigned reserved15:1;
239 + unsigned mdis:1;
240 + unsigned dis_tx:1;
241 + unsigned dis_rxf:1;
242 + unsigned clr_tx:1;
243 + unsigned clr_rxf:1;
244 + unsigned smpl_pt:2;
245 + unsigned reserved71:7;
246 + unsigned halt:1;
247 +};
248 +
249 +struct DSPI_CTAR {
250 + unsigned dbr:1;
251 + unsigned fmsz:4;
252 + unsigned cpol:1;
253 + unsigned cpha:1;
254 + unsigned lsbfe:1;
255 + unsigned pcssck:2;
256 + unsigned pasc:2;
257 + unsigned pdt:2;
258 + unsigned pbr:2;
259 + unsigned cssck:4;
260 + unsigned asc:4;
261 + unsigned dt:4;
262 + unsigned br:4;
263 +};
264 +
265 +struct chip_data {
266 + /* dspi data */
267 + union {
268 + u32 mcr_val;
269 + struct DSPI_MCR mcr;
270 + };
271 + union {
272 + u32 ctar_val;
273 + struct DSPI_CTAR ctar;
274 + };
275 + u16 void_write_data;
276 +};
277 +
278 +
279 +struct driver_data {
280 + /* Driver model hookup */
281 + struct platform_device *pdev;
282 +
283 + /* SPI framework hookup */
284 + struct spi_master *master;
285 +
286 + /* Driver message queue */
287 + struct workqueue_struct *workqueue;
288 + struct work_struct pump_messages;
289 + spinlock_t lock; /* lock */
290 + struct list_head queue;
291 + int busy;
292 + int run;
293 +
294 + /* Message Transfer pump */
295 + struct tasklet_struct pump_transfers;
296 +
297 + /* Current message transfer state info */
298 + struct spi_message *cur_msg;
299 + struct spi_transfer *cur_transfer;
300 + struct chip_data *cur_chip;
301 + size_t len;
302 + void *tx;
303 + void *tx_end;
304 + void *rx;
305 + void *rx_end;
306 + char flags;
307 + u8 cs;
308 + u16 void_write_data;
309 + unsigned cs_change:1;
310 +
311 + u32 trans_cnt;
312 + u32 wce_cnt;
313 + u32 abrt_cnt;
314 + volatile u32 *mcr; /* DSPI MCR register */
315 + volatile u32 *ctar; /* DSPI CTAR register */
316 + volatile u32 *dspi_dtfr; /* DSPI DTFR register */
317 + volatile u32 *dspi_drfr; /* DSPI DRFR register */
318 + volatile u32 *dspi_rser; /* DSPI RSER register */
319 + volatile u32 *dspi_sr; /* DSPI status register */
320 +
321 +#if defined(SPI_DSPI_EDMA)
322 + volatile void *edma_tx_buf;
323 + volatile void *edma_rx_buf;
324 + dma_addr_t edma_tx_buf_pa;
325 + dma_addr_t edma_rx_buf_pa;
326 +#endif
327 +
328 +#if defined(CONFIG_M5301x)
329 + u8 *parh;
330 + u8 *parl;
331 +#else
332 + u8 *par; /* Pin assignment register */
333 +#endif
334 + u8 *int_icr; /* Interrupt level and priority register */
335 + u32 *int_mr; /* Interrupt mask register */
336 + void (*cs_control)(u8 cs, u8 command);
337 +};
338 +
339 +#define DSPI_CS(cs) ((1<<(cs))<<16)
340 +
341 +/****************************************************************************/
342 +
343 +/*
344 + * SPI local functions
345 + */
346 +
347 +static void *next_transfer(struct driver_data *drv_data)
348 +{
349 + struct spi_message *msg = drv_data->cur_msg;
350 + struct spi_transfer *trans = drv_data->cur_transfer;
351 +
352 + DBG("\n");
353 + /* Move to next transfer */
354 + if (trans->transfer_list.next != &msg->transfers) {
355 + drv_data->cur_transfer = list_entry(trans->transfer_list.next,
356 + struct spi_transfer,
357 + transfer_list);
358 +
359 + if (drv_data->cur_transfer->transfer_list.next
360 + == &msg->transfers) /* last transfer */
361 + drv_data->cur_transfer->cs_change = 1;
362 +
363 + return RUNNING_STATE;
364 + } else
365 + return DONE_STATE;
366 +}
367 +
368 +
369 +static inline int is_word_transfer(struct driver_data *drv_data)
370 +{
371 + return ((*(volatile u32 *)(drv_data->ctar+drv_data->cs) & DSPI_BITS_16)
372 + == DSPI_BITS_8) ? 0 : 1;
373 +}
374 +
375 +static inline void set_8bit_transfer_mode(struct driver_data *drv_data)
376 +{
377 + DBG("\n");
378 + *(volatile u32 *)(drv_data->ctar+drv_data->cs) =
379 + ((*(volatile u32 *)(drv_data->ctar + drv_data->cs)) & ~DSPI_BITS)
380 + | DSPI_BITS_8;
381 +}
382 +
383 +static inline void set_16bit_transfer_mode(struct driver_data *drv_data)
384 +{
385 + DBG("\n");
386 + (*(volatile u32 *)(drv_data->ctar+drv_data->cs)) =
387 + ((*(volatile u32 *)(drv_data->ctar + drv_data->cs)) & ~DSPI_BITS)
388 + | DSPI_BITS_16;
389 +}
390 +
391 +static unsigned char hz_to_spi_baud(int pbr, int dbr, int speed_hz)
392 +{
393 + int pbr_tbl[4] = {2, 3, 5, 7}; /* Valid baud rate pre-scaler values */
394 + int brs[16] = { 2, 4, 6, 8,
395 + 16, 32, 64, 128,
396 + 256, 512, 1024, 2048,
397 + 4096, 8192, 16384, 32768 };
398 + int temp, index = 0;
399 +
400 + if ((pbr < 0) || (pbr > 3) ||
401 + (dbr < 0) || (dbr > 1))
402 + return 15; /* table indexes out of range, go slow */
403 +
404 + temp = ((((MCF_CLK / 2) / pbr_tbl[pbr]) * (1 + dbr)) / speed_hz);
405 +
406 + while (temp > brs[index])
407 + if (index++ >= 15)
408 + break;
409 +
410 + DBG("baud rate scaler = 0x%x - %d\n", index, brs[index]);
411 + return index;
412 +}
413 +
414 +static int write(struct driver_data *drv_data)
415 +{
416 + int tx_count = 0;
417 + int tx_word = is_word_transfer(drv_data);
418 + u16 d16;
419 + u8 d8;
420 + u32 dspi_pushr = 0;
421 + int first = 1;
422 +#if defined(SPI_DSPI_EDMA)
423 + volatile u32 *edma_wr = (volatile u32 *)(drv_data->edma_tx_buf);
424 +#endif
425 +
426 + /* If we are in word mode, but only have a single byte to transfer
427 + * then switch to byte mode temporarily. Will switch back at the
428 + * end of the transfer. */
429 + if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) {
430 + drv_data->flags |= TRAN_STATE_WORD_ODD_NUM;
431 + set_8bit_transfer_mode(drv_data);
432 + tx_word = 0;
433 + }
434 + while ((drv_data->tx < drv_data->tx_end)
435 + && (tx_count < DSPI_FIFO_SIZE)) {
436 + if (tx_word) {
437 + if ((drv_data->tx_end - drv_data->tx) == 1)
438 + break;
439 +
440 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
441 + d16 = *(u16 *)drv_data->tx;
442 + else
443 + d16 = drv_data->void_write_data;
444 +
445 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16) |
446 + DSPI_CS(drv_data->cs) |
447 + MCF_DSPI_DTFR_CTAS(drv_data->cs) |
448 + MCF_DSPI_DTFR_CONT;
449 +
450 + drv_data->tx += 2;
451 + } else {
452 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
453 + d8 = *(u8 *)drv_data->tx;
454 + else
455 + d8 = (u8)drv_data->void_write_data;
456 +
457 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8) |
458 + DSPI_CS(drv_data->cs) |
459 + MCF_DSPI_DTFR_CTAS(drv_data->cs) |
460 + MCF_DSPI_DTFR_CONT;
461 +
462 + drv_data->tx++;
463 + }
464 +#ifdef NEW_DMA_METHOD
465 + if ((drv_data->cs_change)
466 + && (drv_data->tx == drv_data->tx_end))
467 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
468 +#else
469 + if (drv_data->tx == drv_data->tx_end
470 + || tx_count == DSPI_FIFO_SIZE-1) {
471 + /* last transfer in the queue */
472 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
473 + if ((drv_data->cs_change)
474 + && (drv_data->tx == drv_data->tx_end))
475 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
476 +#ifdef CONFIG_M547X_8X
477 + /* EOQ gets missed if we don't delay */
478 + udelay(100);
479 +#endif
480 + } else if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1))
481 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
482 +#endif
483 +#if 1
484 + /*
485 + * we don't need this count in NEW_DMA_METHOD,
486 + * so let is be.(2009-09-11)
487 + */
488 + if (first) {
489 + first = 0;
490 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
491 + }
492 +#endif
493 +#if defined(SPI_DSPI_EDMA)
494 + *(volatile u32 *)edma_wr = dspi_pushr;
495 + edma_wr++;
496 +#else
497 + *drv_data->dspi_dtfr = dspi_pushr;
498 +#endif
499 + tx_count++;
500 + }
501 +
502 +#if defined(SPI_DSPI_EDMA)
503 +#ifdef NEW_DMA_METHOD
504 +
505 + if (tx_count > 0) {
506 + mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD,
507 + /*virt_to_phys((void *)drv_data->edma_tx_buf),*/
508 + (u32)drv_data->edma_tx_buf_pa,
509 + (u32)drv_data->dspi_dtfr,
510 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
511 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
512 + 4, /* soff */
513 + 4, /* nbytes */
514 + 0, /* slast */
515 + tx_count, /* citer */
516 + tx_count, /* biter */
517 + 0, /* doff */
518 + 0, /* dlastsga */
519 + 0, /* major_int */
520 + 1); /* disable_req */
521 +
522 + mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD,
523 + (u32)drv_data->dspi_drfr,
524 + /*virt_to_phys((void *)drv_data->edma_rx_buf),*/
525 + (u32)drv_data->edma_rx_buf_pa,
526 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
527 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
528 + 0, /* soff */
529 + 4, /* nbytes */
530 + 0, /* slast */
531 + tx_count, /* citer */
532 + tx_count, /* biter */
533 + 4, /* doff */
534 + 0, /* dlastsga */
535 + 1, /* major_int */
536 + 1); /* disable_req */
537 +
538 + mcf_edma_enable_transfer(DSPI_DMA_RX_TCD);
539 + mcf_edma_enable_transfer(DSPI_DMA_TX_TCD);
540 + }
541 +#else
542 + if (tx_count > 0) {
543 +
544 + mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD,
545 + virt_to_phys((void *)drv_data->edma_tx_buf),
546 + (u32)drv_data->dspi_dtfr,
547 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
548 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
549 + 4, /* soff */
550 + 4 * tx_count, /* nbytes */
551 + 0, /* slast */
552 + 1, /* citer */
553 + 1, /* biter */
554 + 0, /* doff */
555 + 0, /* dlastsga */
556 + 0, /* major_int */
557 + 1); /* disable_req */
558 +
559 + mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD,
560 + (u32)drv_data->dspi_drfr,
561 + virt_to_phys((void *)drv_data->edma_rx_buf),
562 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
563 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
564 + 0, /* soff */
565 + 4 * tx_count, /* nbytes */
566 + 0, /* slast */
567 + 1, /* citer */
568 + 1, /* biter */
569 + 4, /* doff */
570 + 0, /* dlastsga */
571 + 0, /* major_int */
572 + 1); /* disable_req */
573 +
574 + mcf_edma_start_transfer(DSPI_DMA_TX_TCD);
575 + }
576 +#endif
577 +#endif
578 + DBG(" send %d[%d]\n", tx_count, tx_count*(tx_word + 1));
579 + return tx_count * (tx_word + 1);
580 +}
581 +
582 +static int read(struct driver_data *drv_data)
583 +{
584 + int rx_count = 0;
585 + int rx_word = is_word_transfer(drv_data);
586 + u16 d;
587 +#if defined(SPI_DSPI_EDMA)
588 + u32 *rx_edma = (u32 *) drv_data->edma_rx_buf;
589 +
590 + /* receive SPI data */
591 + udelay(10);
592 + mcf_edma_start_transfer(DSPI_DMA_RX_TCD);
593 + udelay(10);
594 +#endif
595 + while ((drv_data->rx < drv_data->rx_end)
596 + && (rx_count < DSPI_FIFO_SIZE)) {
597 +
598 + if (rx_word) {
599 + if ((drv_data->rx_end - drv_data->rx) == 1)
600 + break;
601 +#if defined(SPI_DSPI_EDMA)
602 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
603 + rx_edma++;
604 +#else
605 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
606 +#endif
607 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
608 + *(u16 *)drv_data->rx = d;
609 + drv_data->rx += 2;
610 +
611 + } else {
612 +#if defined(SPI_DSPI_EDMA)
613 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
614 + rx_edma++;
615 +#else
616 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
617 +#endif
618 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
619 + *(u8 *)drv_data->rx = d;
620 + drv_data->rx++;
621 + }
622 + rx_count++;
623 + DBG("rxd=0x%x\n", d);
624 + }
625 + return rx_count;
626 +}
627 +
628 +
629 +static inline void dspi_setup_chip(struct driver_data *drv_data)
630 +{
631 + struct chip_data *chip = drv_data->cur_chip;
632 +
633 + DBG("\n");
634 + (*(volatile u32 *)drv_data->mcr) = chip->mcr_val;
635 + (*(volatile u32 *)(drv_data->ctar+drv_data->cs)) = chip->ctar_val;
636 +#ifdef NEW_DMA_METHOD
637 + /* enable DSPI DMA request function */
638 + (*(volatile u32 *)drv_data->dspi_rser) = MCF_DSPI_DRSER_TFFFE
639 + | MCF_DSPI_DRSER_TFFFS | MCF_DSPI_DRSER_RFDFE
640 + | MCF_DSPI_DRSER_RFDFS;
641 +#else
642 + *drv_data->dspi_rser = MCF_DSPI_DRSER_EOQFE;
643 +#endif
644 +}
645 +
646 +#if defined(SPI_DSPI_EDMA)
647 +static irqreturn_t edma_tx_handler(int channel, void *dev)
648 +{
649 + DBG("\n");
650 + if (channel == DSPI_DMA_TX_TCD)
651 + mcf_edma_stop_transfer(DSPI_DMA_TX_TCD);
652 + return IRQ_HANDLED;
653 +}
654 +
655 +static struct driver_data *dspi_drv_data;
656 +
657 +static irqreturn_t edma_rx_handler(int channel, void *dev)
658 +{
659 + struct driver_data *drv_data = dspi_drv_data;
660 +#if 1
661 + int rx_count = 0;
662 + int rx_word = is_word_transfer(drv_data);
663 + u16 d;
664 + volatile u32 *rx_edma = (volatile u32 *) drv_data->edma_rx_buf;
665 + struct spi_message *msg = drv_data->cur_msg;
666 +#endif
667 + DBG("\n");
668 + if (channel == DSPI_DMA_RX_TCD) {
669 + mcf_edma_stop_transfer(DSPI_DMA_TX_TCD);
670 + mcf_edma_stop_transfer(DSPI_DMA_RX_TCD);
671 + }
672 +
673 +#if 1
674 + if (!(drv_data->flags & TRAN_STATE_RX_VOID)) {
675 + while ((drv_data->rx < drv_data->rx_end)
676 + && (rx_count < DSPI_FIFO_SIZE)) {
677 + if (rx_word) {
678 + if ((drv_data->rx_end - drv_data->rx) == 1)
679 + break;
680 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
681 + rx_edma++;
682 + *(u16 *)drv_data->rx = d;
683 + drv_data->rx += 2;
684 +
685 + } else {
686 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
687 + rx_edma++;
688 + *(u8 *)drv_data->rx = d;
689 + drv_data->rx++;
690 + }
691 + rx_count++;
692 + }
693 + } else { /* rx void by upper */
694 + if ((drv_data->rx_end - drv_data->rx) > DSPI_FIFO_SIZE)
695 + drv_data->rx += DSPI_FIFO_SIZE;
696 + else
697 + drv_data->rx = drv_data->rx_end -
698 + (drv_data->tx_end - drv_data->tx);
699 + }
700 + if (drv_data->rx == drv_data->rx_end) {
701 + /*
702 + * * Finished now - fall through and schedule next
703 + * * transfer tasklet
704 + * */
705 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM)
706 + set_16bit_transfer_mode(drv_data);
707 +
708 + msg->state = next_transfer(drv_data);
709 + } else {
710 + /* not finished yet - keep going */
711 + msg->actual_length += write(drv_data);
712 +
713 + return IRQ_HANDLED;
714 + }
715 +
716 +#endif
717 + tasklet_schedule(&drv_data->pump_transfers);
718 +
719 + return IRQ_HANDLED;
720 +}
721 +#endif
722 +
723 +static irqreturn_t dspi_interrupt(int irq, void *dev_id)
724 +{
725 + struct driver_data *drv_data = (struct driver_data *)dev_id;
726 + struct spi_message *msg = drv_data->cur_msg;
727 +
728 + /* Clear all flags immediately */
729 + *drv_data->dspi_sr = MCF_DSPI_DSR_EOQF;
730 +
731 + if (!drv_data->cur_msg || !drv_data->cur_msg->state) {
732 +#if !defined(SPI_DSPI_EDMA)
733 + u32 irq_status = *drv_data->dspi_sr;
734 + /* if eDMA is used it happens some time (at least once)*/
735 + printk(KERN_ERR "Bad message or transfer state handler. \
736 + IRQ status = %x\n", irq_status);
737 +#endif
738 + return IRQ_NONE;
739 + }
740 +
741 + DBG("\n");
742 + /*
743 + * Read the data into the buffer and reload and start
744 + * queue with new data if not finished. If finished
745 + * then setup the next transfer
746 + */
747 +#if defined(SPI_DSPI_EDMA)
748 + mcf_edma_start_transfer(DSPI_DMA_RX_TCD);
749 +#endif
750 + read(drv_data);
751 +
752 + if (drv_data->rx == drv_data->rx_end) {
753 + /*
754 + * Finished now - fall through and schedule next
755 + * transfer tasklet
756 + */
757 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM)
758 + set_16bit_transfer_mode(drv_data);
759 +
760 + msg->state = next_transfer(drv_data);
761 + } else {
762 + /* not finished yet - keep going */
763 + msg->actual_length += write(drv_data);
764 + return IRQ_HANDLED;
765 + }
766 +
767 + tasklet_schedule(&drv_data->pump_transfers);
768 +
769 + return IRQ_HANDLED;
770 +}
771 +
772 +/* caller already set message->status; dma and pio irqs are blocked */
773 +static void giveback(struct driver_data *drv_data)
774 +{
775 + struct spi_transfer *last_transfer;
776 + unsigned long flags;
777 + struct spi_message *msg;
778 + DBG("\n");
779 +
780 + spin_lock_irqsave(&drv_data->lock, flags);
781 + msg = drv_data->cur_msg;
782 + drv_data->cur_msg = NULL;
783 + drv_data->cur_transfer = NULL;
784 + drv_data->cur_chip = NULL;
785 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
786 + spin_unlock_irqrestore(&drv_data->lock, flags);
787 +
788 + last_transfer = list_entry(msg->transfers.prev,
789 + struct spi_transfer, transfer_list);
790 +
791 + if (!last_transfer->cs_change)
792 + drv_data->cs_control(drv_data->cs, QSPI_CS_DROP);
793 +
794 + msg->state = NULL;
795 + if (msg->complete)
796 + msg->complete(msg->context);
797 +}
798 +
799 +
800 +static void pump_transfers(unsigned long data)
801 +{
802 + struct driver_data *drv_data = (struct driver_data *)data;
803 + struct spi_message *message = NULL;
804 + struct spi_transfer *transfer = NULL;
805 + struct spi_transfer *previous = NULL;
806 + struct chip_data *chip = NULL;
807 + unsigned long flags;
808 +#if 0
809 + int rx_count = 0;
810 + int rx_word = is_word_transfer(drv_data);
811 + u16 d;
812 + volatile u32 *rx_edma = (volatile u32 *) drv_data->edma_rx_buf;
813 + struct spi_message *msg = drv_data->cur_msg;
814 +#endif
815 + DBG("\n");
816 +
817 +#if 0
818 + if (!first_in_transfer) {
819 + if (!(drv_data->flags & TRAN_STATE_RX_VOID)) {
820 + while ((drv_data->rx < drv_data->rx_end)
821 + && (rx_count < DSPI_FIFO_SIZE)) {
822 + if (rx_word) {
823 + if ((drv_data->rx_end - drv_data->rx)
824 + == 1)
825 + break;
826 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
827 + rx_edma++;
828 + *(u16 *)drv_data->rx = d;
829 + drv_data->rx += 2;
830 +
831 + } else {
832 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
833 + rx_edma++;
834 + *(u8 *)drv_data->rx = d;
835 + drv_data->rx++;
836 + }
837 + rx_count++;
838 + }
839 + } else { /* rx void by upper */
840 + if ((drv_data->rx_end - drv_data->rx) > DSPI_FIFO_SIZE)
841 + drv_data->rx += DSPI_FIFO_SIZE;
842 + else
843 + drv_data->rx = drv_data->rx_end -
844 + (drv_data->tx_end - drv_data->tx);
845 + }
846 + if (drv_data->rx == drv_data->rx_end) {
847 + /*
848 + * * Finished now - fall through and schedule next
849 + * * transfer tasklet
850 + * */
851 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM)
852 + set_16bit_transfer_mode(drv_data);
853 +
854 + msg->state = next_transfer(drv_data);
855 + } else {
856 + /* not finished yet - keep going */
857 + local_irq_save(flags);
858 + msg->actual_length += write(drv_data);
859 + local_irq_restore(flags);
860 + return;
861 + }
862 + } else {
863 + first_in_transfer = 0;
864 + }
865 +#endif
866 +
867 +
868 + /* Get current state information */
869 + message = drv_data->cur_msg;
870 + transfer = drv_data->cur_transfer;
871 + chip = drv_data->cur_chip;
872 +
873 + /* Handle for abort */
874 + if (message->state == ERROR_STATE) {
875 + message->status = -EIO;
876 + giveback(drv_data);
877 + return;
878 + }
879 +
880 + /* Handle end of message */
881 + if (message->state == DONE_STATE) {
882 + message->status = 0;
883 + giveback(drv_data);
884 + return;
885 + }
886 +#if 1
887 + drv_data->cs = message->spi->chip_select;
888 + drv_data->cs_change = transfer->cs_change;
889 + drv_data->void_write_data = chip->void_write_data;
890 +#endif
891 +
892 + if (message->state == START_STATE) {
893 +#if 0
894 + drv_data->cs = message->spi->chip_select;
895 + drv_data->cs_change = transfer->cs_change;
896 + drv_data->void_write_data = chip->void_write_data;
897 +#endif
898 +
899 + dspi_setup_chip(drv_data);
900 +
901 + if (drv_data->cs_control)
902 + drv_data->cs_control(message->spi->chip_select,
903 + QSPI_CS_ASSERT);
904 + }
905 +
906 + /* Delay if requested at end of transfer*/
907 + if (message->state == RUNNING_STATE) {
908 + previous = list_entry(transfer->transfer_list.prev,
909 + struct spi_transfer,
910 + transfer_list);
911 +
912 + if (drv_data->cs_control && transfer->cs_change)
913 + drv_data->cs_control(message->spi->chip_select,
914 + QSPI_CS_DROP);
915 +
916 + if (previous->delay_usecs)
917 + udelay(previous->delay_usecs);
918 +
919 + if (drv_data->cs_control && transfer->cs_change)
920 + drv_data->cs_control(message->spi->chip_select,
921 + QSPI_CS_ASSERT);
922 + }
923 +
924 + drv_data->flags = 0;
925 + drv_data->tx = (void *)transfer->tx_buf;
926 + drv_data->tx_end = drv_data->tx + transfer->len;
927 + drv_data->rx = transfer->rx_buf;
928 + drv_data->rx_end = drv_data->rx + transfer->len;
929 +
930 + if (!drv_data->rx)
931 + drv_data->flags |= TRAN_STATE_RX_VOID;
932 +
933 + if (!drv_data->tx)
934 + drv_data->flags |= TRAN_STATE_TX_VOID;
935 +
936 +#if 0
937 + drv_data->cs = message->spi->chip_select;
938 + drv_data->cs_change = transfer->cs_change;
939 + drv_data->void_write_data = chip->void_write_data;
940 +#endif
941 + if (transfer->speed_hz) {
942 + *(drv_data->ctar + drv_data->cs) = \
943 + ((chip->ctar_val & ~0xF) | \
944 + hz_to_spi_baud(chip->ctar.pbr, \
945 + chip->ctar.dbr, \
946 + transfer->speed_hz));
947 + }
948 +
949 + message->state = RUNNING_STATE;
950 +
951 + /* Go baby, go */
952 + local_irq_save(flags);
953 + message->actual_length += write(drv_data);
954 + local_irq_restore(flags);
955 +}
956 +
957 +
958 +static void pump_messages(struct work_struct *work)
959 +{
960 + struct driver_data *drv_data;
961 + unsigned long flags;
962 + DBG("\n");
963 +
964 + drv_data = container_of(work, struct driver_data, pump_messages);
965 +
966 + /* Lock queue and check for queue work */
967 + spin_lock_irqsave(&drv_data->lock, flags);
968 + if (list_empty(&drv_data->queue)
969 + || drv_data->run == QUEUE_STOPPED) {
970 + drv_data->busy = 0;
971 + spin_unlock_irqrestore(&drv_data->lock, flags);
972 + return;
973 + }
974 +
975 + /* Make sure we are not already running a message */
976 + if (drv_data->cur_msg) {
977 + spin_unlock_irqrestore(&drv_data->lock, flags);
978 + return;
979 + }
980 +
981 + /* Extract head of queue */
982 + drv_data->cur_msg = list_entry(drv_data->queue.next,
983 + struct spi_message, queue);
984 + list_del_init(&drv_data->cur_msg->queue);
985 +
986 + /* Initial message state*/
987 + drv_data->cur_msg->state = START_STATE;
988 + drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
989 + struct spi_transfer,
990 + transfer_list);
991 +
992 + if (drv_data->cur_transfer->transfer_list.next
993 + == &drv_data->cur_msg->transfers)
994 + drv_data->cur_transfer->cs_change = 1; /* last */
995 +
996 +#ifdef NEW_DMA_METHOD
997 + mcf_edma_stop_transfer(DSPI_DMA_TX_TCD);
998 + mcf_edma_stop_transfer(DSPI_DMA_RX_TCD);
999 + first_in_transfer = 1;
1000 +#endif
1001 + /* Setup the SPI Registers using the per chip configuration */
1002 + drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1003 +
1004 + /* Mark as busy and launch transfers */
1005 + tasklet_schedule(&drv_data->pump_transfers);
1006 +
1007 + drv_data->busy = 1;
1008 + spin_unlock_irqrestore(&drv_data->lock, flags);
1009 +}
1010 +
1011 +/****************************************************************************/
1012 +
1013 +/*
1014 + * SPI master implementation
1015 + */
1016 +
1017 +static int transfer(struct spi_device *spi, struct spi_message *msg)
1018 +{
1019 + struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1020 + unsigned long flags;
1021 +
1022 + DBG("\n");
1023 + spin_lock_irqsave(&drv_data->lock, flags);
1024 +
1025 + if (drv_data->run == QUEUE_STOPPED) {
1026 + spin_unlock_irqrestore(&drv_data->lock, flags);
1027 + return -ESHUTDOWN;
1028 + }
1029 +
1030 + msg->actual_length = 0;
1031 + msg->status = -EINPROGRESS;
1032 + msg->state = START_STATE;
1033 +
1034 + list_add_tail(&msg->queue, &drv_data->queue);
1035 +
1036 + if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1037 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
1038 +
1039 + spin_unlock_irqrestore(&drv_data->lock, flags);
1040 +
1041 + return 0;
1042 +}
1043 +
1044 +
1045 +static int setup(struct spi_device *spi)
1046 +{
1047 + struct chip_data *chip;
1048 + struct coldfire_dspi_chip *chip_info
1049 + = (struct coldfire_dspi_chip *)spi->controller_data;
1050 + DBG("\n");
1051 +
1052 + /* Only alloc on first setup */
1053 + chip = spi_get_ctldata(spi);
1054 + if (chip == NULL) {
1055 + chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
1056 + if (!chip)
1057 + return -ENOMEM;
1058 + spi->mode = chip_info->mode;
1059 + spi->bits_per_word = chip_info->bits_per_word;
1060 + }
1061 +
1062 + chip->mcr.master = 1;
1063 + chip->mcr.cont_scke = 0;
1064 + chip->mcr.dconf = 0;
1065 + chip->mcr.frz = 0;
1066 + chip->mcr.mtfe = 0;
1067 + chip->mcr.pcsse = 0;
1068 + chip->mcr.rooe = 0;
1069 + chip->mcr.pcsis = 0xFF;
1070 + chip->mcr.reserved15 = 0;
1071 + chip->mcr.mdis = 0;
1072 + chip->mcr.dis_tx = 0;
1073 + chip->mcr.dis_rxf = 0;
1074 + chip->mcr.clr_tx = 1;
1075 + chip->mcr.clr_rxf = 1;
1076 + chip->mcr.smpl_pt = 0;
1077 + chip->mcr.reserved71 = 0;
1078 + chip->mcr.halt = 0;
1079 +
1080 + if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
1081 + chip->ctar.fmsz = spi->bits_per_word-1;
1082 + } else {
1083 + printk(KERN_ERR "Invalid wordsize\n");
1084 + kfree(chip);
1085 + return -ENODEV;
1086 + }
1087 +
1088 + chip->void_write_data = chip_info->void_write_data;
1089 +
1090 + if (spi->max_speed_hz != 0)
1091 + chip_info->br = hz_to_spi_baud(chip_info->pbr, chip_info->dbr, \
1092 + spi->max_speed_hz);
1093 +
1094 + chip->ctar.cpha = (spi->mode & SPI_CPHA) ? 1 : 0;
1095 + chip->ctar.cpol = (spi->mode & SPI_CPOL) ? 1 : 0;
1096 + chip->ctar.lsbfe = (spi->mode & SPI_LSB_FIRST) ? 1 : 0;
1097 + chip->ctar.dbr = chip_info->dbr;
1098 + chip->ctar.pbr = chip_info->pbr;
1099 + chip->ctar.br = chip_info->br;
1100 + chip->ctar.pcssck = chip_info->pcssck;
1101 + chip->ctar.pasc = chip_info->pasc;
1102 + chip->ctar.pdt = chip_info->pdt;
1103 + chip->ctar.cssck = chip_info->cssck;
1104 + chip->ctar.asc = chip_info->asc;
1105 + chip->ctar.dt = chip_info->dt;
1106 +
1107 + spi_set_ctldata(spi, chip);
1108 +
1109 + return 0;
1110 +}
1111 +
1112 +static int init_queue(struct driver_data *drv_data)
1113 +{
1114 + INIT_LIST_HEAD(&drv_data->queue);
1115 + spin_lock_init(&drv_data->lock);
1116 +
1117 + drv_data->run = QUEUE_STOPPED;
1118 + drv_data->busy = 0;
1119 +
1120 + tasklet_init(&drv_data->pump_transfers,
1121 + pump_transfers, (unsigned long)drv_data);
1122 +
1123 + INIT_WORK(&drv_data->pump_messages, pump_messages);
1124 +
1125 + drv_data->workqueue = create_singlethread_workqueue(
1126 + dev_name(drv_data->master->dev.parent));
1127 + if (drv_data->workqueue == NULL)
1128 + return -EBUSY;
1129 +
1130 + return 0;
1131 +}
1132 +
1133 +static int start_queue(struct driver_data *drv_data)
1134 +{
1135 + unsigned long flags;
1136 +
1137 + spin_lock_irqsave(&drv_data->lock, flags);
1138 +
1139 + if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1140 + spin_unlock_irqrestore(&drv_data->lock, flags);
1141 + return -EBUSY;
1142 + }
1143 +
1144 + drv_data->run = QUEUE_RUNNING;
1145 + drv_data->cur_msg = NULL;
1146 + drv_data->cur_transfer = NULL;
1147 + drv_data->cur_chip = NULL;
1148 + spin_unlock_irqrestore(&drv_data->lock, flags);
1149 +
1150 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
1151 +
1152 + return 0;
1153 +}
1154 +
1155 +static int stop_queue(struct driver_data *drv_data)
1156 +{
1157 + unsigned long flags;
1158 + unsigned limit = 500;
1159 + int status = 0;
1160 +
1161 + spin_lock_irqsave(&drv_data->lock, flags);
1162 +
1163 + /* This is a bit lame, but is optimized for the common execution path.
1164 + * A wait_queue on the drv_data->busy could be used, but then the common
1165 + * execution path (pump_messages) would be required to call wake_up or
1166 + * friends on every SPI message. Do this instead */
1167 + drv_data->run = QUEUE_STOPPED;
1168 + while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1169 + spin_unlock_irqrestore(&drv_data->lock, flags);
1170 + msleep(20);
1171 + spin_lock_irqsave(&drv_data->lock, flags);
1172 + }
1173 +
1174 + if (!list_empty(&drv_data->queue) || drv_data->busy)
1175 + status = -EBUSY;
1176 +
1177 + spin_unlock_irqrestore(&drv_data->lock, flags);
1178 +
1179 + return status;
1180 +}
1181 +
1182 +static int destroy_queue(struct driver_data *drv_data)
1183 +{
1184 + int status;
1185 +
1186 + status = stop_queue(drv_data);
1187 + if (status != 0)
1188 + return status;
1189 +
1190 + destroy_workqueue(drv_data->workqueue);
1191 +
1192 + return 0;
1193 +}
1194 +
1195 +
1196 +static void cleanup(struct spi_device *spi)
1197 +{
1198 + struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1199 +
1200 + dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1201 + spi->master->bus_num, spi->chip_select);
1202 +
1203 + kfree(chip);
1204 +}
1205 +
1206 +
1207 +/****************************************************************************/
1208 +
1209 +/*
1210 + * Generic Device driver routines and interface implementation
1211 + */
1212 +
1213 +static int coldfire_spi_probe(struct platform_device *pdev)
1214 +{
1215 + struct device *dev = &pdev->dev;
1216 + struct coldfire_spi_master *platform_info;
1217 + struct spi_master *master;
1218 + struct driver_data *drv_data = 0;
1219 + struct resource *memory_resource;
1220 + int irq;
1221 + int status = 0;
1222 + int i;
1223 +
1224 + platform_info = (struct coldfire_spi_master *)dev->platform_data;
1225 +
1226 + master = spi_alloc_master(dev, sizeof(struct driver_data));
1227 + if (!master)
1228 + return -ENOMEM;
1229 +
1230 + drv_data = spi_master_get_devdata(master);
1231 + drv_data->master = master;
1232 +
1233 + INIT_LIST_HEAD(&drv_data->queue);
1234 + spin_lock_init(&drv_data->lock);
1235 +
1236 + master->bus_num = platform_info->bus_num;
1237 + master->num_chipselect = platform_info->num_chipselect;
1238 + master->cleanup = cleanup;
1239 + master->setup = setup;
1240 + master->transfer = transfer;
1241 +
1242 + drv_data->cs_control = platform_info->cs_control;
1243 + if (drv_data->cs_control)
1244 + for (i = 0; i < master->num_chipselect; i++)
1245 + drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP);
1246 +
1247 + /* Setup register addresses */
1248 + memory_resource = platform_get_resource_byname(pdev,
1249 + IORESOURCE_MEM, "spi-module");
1250 + if (!memory_resource) {
1251 + dev_dbg(dev, "can not find platform module memory\n");
1252 + goto out_error_master_alloc;
1253 + }
1254 +
1255 +#if defined(SPI_DSPI_EDMA)
1256 + drv_data->edma_tx_buf = (volatile void *)dma_alloc_coherent(NULL,
1257 + EDMA_BUFSIZE_KMALLOC,
1258 + &drv_data->edma_tx_buf_pa,
1259 + GFP_DMA);
1260 + if (!drv_data->edma_tx_buf) {
1261 + dev_dbg(dev, "cannot allocate eDMA TX memory\n");
1262 + goto out_error_master_alloc;
1263 + }
1264 + drv_data->edma_rx_buf = (volatile void *)dma_alloc_coherent(NULL,
1265 + EDMA_BUFSIZE_KMALLOC,
1266 + &drv_data->edma_rx_buf_pa,
1267 + GFP_DMA);
1268 + if (!drv_data->edma_rx_buf) {
1269 + dma_free_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
1270 + (void *)drv_data->edma_tx_buf,
1271 + drv_data->edma_tx_buf_pa);
1272 + dev_dbg(dev, "cannot allocate eDMA RX memory\n");
1273 + goto out_error_master_alloc;
1274 + }
1275 + printk(KERN_INFO "Coldfire DSPI DMA addr: Tx-0x%p[0x%x],"
1276 + " Rx-0x%p[0x%x]\n",
1277 + drv_data->edma_tx_buf, drv_data->edma_tx_buf_pa,
1278 + drv_data->edma_rx_buf, drv_data->edma_rx_buf_pa);
1279 +#endif
1280 +#if defined(CONFIG_DSPI0)
1281 + drv_data->mcr = (volatile u32 *)&MCF_DSPI_DMCR;
1282 + drv_data->ctar = (volatile u32 *)&MCF_DSPI_DCTAR0;
1283 + drv_data->dspi_sr = (volatile u32 *)&MCF_DSPI_DSR;
1284 + drv_data->dspi_rser = (volatile u32 *)&MCF_DSPI_DRSER;
1285 + drv_data->dspi_dtfr = (volatile u32 *)&MCF_DSPI_DTFR;
1286 + drv_data->dspi_drfr = (volatile u32 *)&MCF_DSPI_DRFR;
1287 +#elif defined(CONFIG_DSPI1)
1288 + drv_data->mcr = (volatile u32 *)&MCF_DSPI1_DMCR;
1289 + drv_data->ctar = (volatile u32 *)&MCF_DSPI1_DCTAR0;
1290 + drv_data->dspi_sr = (volatile u32 *)&MCF_DSPI1_DSR;
1291 + drv_data->dspi_rser = (volatile u32 *)&MCF_DSPI1_DRSER;
1292 + drv_data->dspi_dtfr = (volatile u32 *)&MCF_DSPI1_DTFR;
1293 + drv_data->dspi_drfr = (volatile u32 *)&MCF_DSPI1_DRFR;
1294 +#else
1295 + drv_data->mcr = (volatile u32 *)&MCF_DSPI_DMCR;
1296 + drv_data->ctar = (volatile u32 *)&MCF_DSPI_DCTAR0;
1297 + drv_data->dspi_sr = (volatile u32 *)&MCF_DSPI_DSR;
1298 + drv_data->dspi_rser = (volatile u32 *)&MCF_DSPI_DRSER;
1299 + drv_data->dspi_dtfr = (volatile u32 *)&MCF_DSPI_DTFR;
1300 + drv_data->dspi_drfr = (volatile u32 *)&MCF_DSPI_DRFR;
1301 +#endif
1302 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1303 + "spi-par");
1304 + if (!memory_resource) {
1305 + dev_dbg(dev, "No spi-par memory\n");
1306 + goto out_error_master_alloc;
1307 + }
1308 +#ifdef CONFIG_M5301x
1309 + drv_data->parh = (void *)memory_resource->start;
1310 + drv_data->parl = (void *)memory_resource->end;
1311 +#elif defined(CONFIG_M5441X)
1312 + /* This configuration has been set at arch scource*/
1313 +#else
1314 + drv_data->par = (void *)memory_resource->start;
1315 +#endif
1316 +
1317 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1318 + "spi-int-level");
1319 + if (!memory_resource) {
1320 + dev_dbg(dev, "No spi-int-level memory\n");
1321 + goto out_error_master_alloc;
1322 + }
1323 + drv_data->int_icr = (void *)memory_resource->start;
1324 +
1325 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1326 + "spi-int-mask");
1327 + if (!memory_resource) {
1328 + dev_dbg(dev, "No spi-int-mask memory\n");
1329 + goto out_error_master_alloc;
1330 + }
1331 + drv_data->int_mr = (void *)memory_resource->start;
1332 +#ifndef NEW_DMA_METHOD
1333 + /*
1334 + * PIO mode
1335 + */
1336 + if (platform_info->irq_list) {
1337 + /* multiple IRQs */
1338 + int *irqlist = platform_info->irq_list;
1339 + while ((irq = *irqlist++)) {
1340 + int off = *irqlist++;
1341 + int lvl = *irqlist++;
1342 + int msk = *irqlist++;
1343 + status = request_irq(irq, dspi_interrupt, IRQF_DISABLED,
1344 + pdev->name, drv_data);
1345 + if (status < 0) {
1346 + dev_err(&pdev->dev,
1347 + "Unable to attach ColdFire DSPI interrupt\n");
1348 + goto out_error_master_alloc;
1349 + }
1350 +
1351 + if (lvl)
1352 + *(drv_data->int_icr + off) = lvl;
1353 +
1354 + if (msk)
1355 + *drv_data->int_mr &= ~msk;
1356 + }
1357 + } else {
1358 + irq = platform_info->irq_vector;
1359 +
1360 + status = request_irq(platform_info->irq_vector, dspi_interrupt,
1361 + IRQF_DISABLED, pdev->name, drv_data);
1362 + if (status < 0) {
1363 + dev_err(&pdev->dev,
1364 + "Unable to attach ColdFire DSPI interrupt\n");
1365 + goto out_error_master_alloc;
1366 + }
1367 +
1368 + *drv_data->int_icr = platform_info->irq_lp;
1369 + *drv_data->int_mr &= ~platform_info->irq_mask;
1370 + }
1371 +#endif
1372 + /* Now that we have all the addresses etc. Let's set it up */
1373 +#ifdef CONFIG_M5301x
1374 + *drv_data->parh = (u8) (platform_info->par_val16 >> 8);
1375 + *drv_data->parl = (u8) (platform_info->par_val16 & 0xff);
1376 +#elif defined(CONFIG_M5441X)
1377 + /* This configuration has been set at arch source */
1378 +#else
1379 + *drv_data->par = platform_info->par_val;
1380 +#endif
1381 +
1382 + /* Initial and start queue */
1383 + status = init_queue(drv_data);
1384 + if (status != 0) {
1385 + dev_err(&pdev->dev, "Problem initializing DSPI queue\n");
1386 + goto out_error_irq_alloc;
1387 + }
1388 + status = start_queue(drv_data);
1389 + if (status != 0) {
1390 + dev_err(&pdev->dev, "Problem starting DSPI queue\n");
1391 + goto out_error_irq_alloc;
1392 + }
1393 +
1394 +#if defined(SPI_DSPI_EDMA)
1395 + DBG("MCF edma request channel for SPI\n");
1396 +
1397 + if (mcf_edma_request_channel(DSPI_DMA_TX_TCD,
1398 + edma_tx_handler,
1399 + NULL,
1400 + 0x00,
1401 + pdev,
1402 + NULL, /* spinlock */
1403 + DRIVER_NAME) < 0){
1404 + dev_err(&pdev->dev, "eDMA transmit channel request\n");
1405 + status = -EINVAL;
1406 + goto out_error_queue_alloc;
1407 + }
1408 +/*
1409 + * we only need RX eDMA interrupt to sync a spi transfer,
1410 + * the Tx eDMA interrupt can be ignored, this is determined
1411 + * by SPI communicate machnisim, i.e, is half duplex mode, that is
1412 + * whether read or write, we need write data out to get we wanted.
1413 + */
1414 + if (mcf_edma_request_channel(DSPI_DMA_RX_TCD,
1415 + edma_rx_handler,
1416 + NULL,
1417 + 0x06,
1418 + pdev,
1419 + NULL, /* spinlock */
1420 + DRIVER_NAME) < 0){
1421 + dev_err(&pdev->dev, "eDAM receive channel request\n");
1422 + status = -EINVAL;
1423 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
1424 + goto out_error_queue_alloc;
1425 + }
1426 +
1427 + dspi_drv_data = drv_data;
1428 +#endif
1429 +
1430 + /* Register with the SPI framework */
1431 + platform_set_drvdata(pdev, drv_data);
1432 + status = spi_register_master(master);
1433 + if (status != 0) {
1434 + dev_err(&pdev->dev, "Problem registering DSPI master\n");
1435 + status = -EINVAL;
1436 + goto out_error_queue_alloc;
1437 + }
1438 +
1439 +#ifdef NEW_DMA_METHOD
1440 + printk(KERN_INFO "Coldfire DSPI: Using Highspeed eDMA transfer method!\n");
1441 +#endif
1442 + printk(KERN_INFO "DSPI: Coldfire master initialized\n");
1443 + return status;
1444 +
1445 +out_error_queue_alloc:
1446 + destroy_queue(drv_data);
1447 +
1448 +out_error_irq_alloc:
1449 + free_irq(platform_info->irq_vector, drv_data);
1450 +
1451 +out_error_master_alloc:
1452 + spi_master_put(master);
1453 + return status;
1454 +
1455 +}
1456 +
1457 +static int coldfire_spi_remove(struct platform_device *pdev)
1458 +{
1459 + struct driver_data *drv_data = platform_get_drvdata(pdev);
1460 + int irq;
1461 + int status = 0;
1462 +
1463 + if (!drv_data)
1464 + return 0;
1465 +
1466 +#if defined(SPI_DSPI_EDMA)
1467 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
1468 + mcf_edma_free_channel(DSPI_DMA_RX_TCD, pdev);
1469 +#endif
1470 +
1471 + /* Remove the queue */
1472 + status = destroy_queue(drv_data);
1473 + if (status != 0)
1474 + return status;
1475 +
1476 + /* Release IRQ */
1477 + irq = platform_get_irq(pdev, 0);
1478 + if (irq >= 0)
1479 + free_irq(irq, drv_data);
1480 +
1481 + /* Disconnect from the SPI framework */
1482 + spi_unregister_master(drv_data->master);
1483 +
1484 + /* Prevent double remove */
1485 + platform_set_drvdata(pdev, NULL);
1486 +
1487 + return 0;
1488 +}
1489 +
1490 +static void coldfire_spi_shutdown(struct platform_device *pdev)
1491 +{
1492 + int status = coldfire_spi_remove(pdev);
1493 +
1494 + if (status != 0)
1495 + dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1496 +}
1497 +
1498 +
1499 +#ifdef CONFIG_PM
1500 +static int suspend_devices(struct device *dev, void *pm_message)
1501 +{
1502 + pm_message_t *state = pm_message;
1503 +
1504 + if (dev->power.power_state.event != state->event) {
1505 + dev_warn(dev, "pm state does not match request\n");
1506 + return -1;
1507 + }
1508 +
1509 + return 0;
1510 +}
1511 +
1512 +static int coldfire_spi_suspend(struct platform_device *pdev,
1513 + pm_message_t state)
1514 +{
1515 + struct driver_data *drv_data = platform_get_drvdata(pdev);
1516 + int status = 0;
1517 +
1518 + /* Check all childern for current power state */
1519 + if (device_for_each_child(&pdev->dev,
1520 + &state, suspend_devices) != 0) {
1521 + dev_warn(&pdev->dev, "suspend aborted\n");
1522 + return -1;
1523 + }
1524 +
1525 + status = stop_queue(drv_data);
1526 + if (status != 0)
1527 + return status;
1528 +
1529 + return 0;
1530 +}
1531 +
1532 +static int coldfire_spi_resume(struct platform_device *pdev)
1533 +{
1534 + struct driver_data *drv_data = platform_get_drvdata(pdev);
1535 + int status = 0;
1536 +
1537 + /* Start the queue running */
1538 + status = start_queue(drv_data);
1539 + if (status != 0) {
1540 + dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1541 + return status;
1542 + }
1543 +
1544 + return 0;
1545 +}
1546 +#else
1547 +#define coldfire_spi_suspend NULL
1548 +#define coldfire_spi_resume NULL
1549 +#endif /* CONFIG_PM */
1550 +
1551 +static struct platform_driver driver = {
1552 + .driver = {
1553 + .name = "spi_coldfire",
1554 + .bus = &platform_bus_type,
1555 + .owner = THIS_MODULE,
1556 + },
1557 + .probe = coldfire_spi_probe,
1558 + .remove = __devexit_p(coldfire_spi_remove),
1559 + .shutdown = coldfire_spi_shutdown,
1560 + .suspend = coldfire_spi_suspend,
1561 + .resume = coldfire_spi_resume,
1562 +};
1563 +
1564 +static int __init coldfire_spi_init(void)
1565 +{
1566 + platform_driver_register(&driver);
1567 +
1568 + return 0;
1569 +}
1570 +module_init(coldfire_spi_init);
1571 +
1572 +static void __exit coldfire_spi_exit(void)
1573 +{
1574 + platform_driver_unregister(&driver);
1575 +}
1576 +module_exit(coldfire_spi_exit);
1577 +
1578 +MODULE_AUTHOR("Matt Waddel");
1579 +MODULE_DESCRIPTION("ColdFire DSPI Contoller");
1580 +MODULE_LICENSE("GPL");
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