target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch

   1 From d09357656ae3985095f562cf005fa94fd61ebfe6 Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Tue, 1 Feb 2022 21:50:16 -0600
   4 Subject: [PATCH 038/117] crypto: sun8i-ce - Add TRNG clock to D1 variant
   5
   6 At least the D1 variant requires a separate clock for the TRNG.
   7 Without this clock enabled, reading from /dev/hwrng reports:
   8
   9    sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3
  10
  11 Experimentation shows that the necessary clock is the SoC's internal
  12 RC oscillator. This makes sense, as the oscillator's frequency
  13 variations can be used as a source of randomness.
  14
  15 Since D1 does not yet have a device tree, we can update this variant
  16 without breaking anything.
  17
  18 Series-changes: 2
  19  - New patch
  20
  21 Signed-off-by: Samuel Holland <samuel@sholland.org>
  22 ---
  23  drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 +
  24  drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h      | 2 +-
  25  2 files changed, 2 insertions(+), 1 deletion(-)
  26
  27 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
  28 +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
  29 @@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_var
  30                 { "bus", 0, 200000000 },
  31                 { "mod", 300000000, 0 },
  32                 { "ram", 0, 400000000 },
  33 +               { "trng", 0, 0 },
  34                 },
  35         .esr = ESR_D1,
  36         .prng = CE_ALG_PRNG,
  37 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
  38 +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
  39 @@ -105,7 +105,7 @@
  40
  41  #define MAX_SG 8
  42
  43 -#define CE_MAX_CLOCKS 3
  44 +#define CE_MAX_CLOCKS 4
  45
  46  #define MAXFLOW 4
  47