1 /*!**********************************************************************
5 *! DESCRIPTION: Shadow register and initiated flag variables,
6 *! and a function for initialization of these variables.
9 *! FUNCTIONS: void init_shadow__hwregs( void )
11 *! NOTE: This file is automatically generated, do _not_ edit.
12 *! Created: Thu Oct 3 01:21:27 2002
13 *! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp
14 *! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168
15 *! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3
17 *! NOTE: init_shadow__hwregs() initiate all write only registers
18 *! described in /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd.
19 *! Since one physical register may have several logical names you
20 *! must choose which of the logical registers to initiate.
21 *! This is done by the 'USE_GROUP__group-name' macro in the
24 *! As an example, in Etrax100 the following logical registers are
25 *! all the same physical register at address 0xb0000044:
32 *!----------------------------------------------------------------------
37 *! Apr 01 1998 Jan Bengtsson Initial version
38 *!----------------------------------------------------------------------
40 *! (C) Copyright 1998, Axis Communications AB, LUND, SWEDEN
42 *!**********************************************************************/
45 /********************** INCLUDE FILES SECTION **************************/
54 /********************** CONSTANT AND MACRO SECTION *********************/
56 /********************** TYPE DEFINITION SECTION ************************/
58 /********************** LOCAL FUNCTION DECLARATION SECTION *************/
60 /********************** GLOBAL VARIABLE DECLARATION SECTION ************/
63 /* Shadows for write only registers. */
64 reg_shadow_type__hwregs reg_shadow__hwregs
;
66 /* Use constant zero as shadow when there isn't a shadow register. */
67 reg_shadow_type__hwregs reg_shadow__hwregs
= 0;
72 /* Initiated flags for shadow registers. */
73 reg_initiated_type__hwregs reg_initiated__hwregs
;
75 /* No need for initiated flags when there isn't a shadow register. */
76 reg_initiated_type__hwregs reg_initiated__hwregs
= 0;
80 /********************** FUNCTION DEFINITION SECTION ********************/
82 /*#**********************************************************************
84 *# FUNCTION NAME: init_shadow__hwregs
90 *# SIDE EFFECTS : Writes initial values to all write only registers
91 *# and their associated shadow registers. If REG_DEBUG
92 *# is non zero the reg_initiated struct is also initiated.
94 *# DESCRIPTION : Initiate write only registers, their shadows, and in
95 *# debug mode the initiated flags. Default values for
96 *# the initialization are defined in hwregs_def.h.
98 *# Note that one physical register may have several
99 *# logical names, and that you have to modify this
100 *# function to only initiate the physical register once!
102 *#----------------------------------------------------------------------
107 *# Apr 01 1998 Jan Bengtsson Initial version
109 *#**********************************************************************/
111 void init_shadow__hwregs( void )
113 #if REG_DEBUG && !defined(REG_NO_SHADOW)
114 /* Initiate reg_initiated__hwregs struct to 0xff. */
115 memset( ®_initiated__hwregs
, 0xff, sizeof(reg_initiated_type__hwregs
) );
118 #ifndef REG_NO_INIT_SHADOW
120 #if USE_GROUP__Serial_port_registers
121 REG_SET__R_ALT_SER_BAUDRATE(
122 ser3_tr
, R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT
,
123 ser3_rec
, R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT
,
124 ser2_tr
, R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT
,
125 ser2_rec
, R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT
,
126 ser1_tr
, R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT
,
127 ser1_rec
, R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT
,
128 ser0_tr
, R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT
,
129 ser0_rec
, R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT
133 #if USE_GROUP__ATA_interface_registers
134 REG_SET__R_ATA_CONFIG(
135 enable
, R_ATA_CONFIG__enable__DEFAULT
,
136 dma_strobe
, R_ATA_CONFIG__dma_strobe__DEFAULT
,
137 dma_hold
, R_ATA_CONFIG__dma_hold__DEFAULT
,
138 pio_setup
, R_ATA_CONFIG__pio_setup__DEFAULT
,
139 pio_strobe
, R_ATA_CONFIG__pio_strobe__DEFAULT
,
140 pio_hold
, R_ATA_CONFIG__pio_hold__DEFAULT
144 #if USE_GROUP__ATA_interface_registers
145 REG_SET__R_ATA_CTRL_DATA(
146 sel
, R_ATA_CTRL_DATA__sel__DEFAULT
,
147 cs1
, R_ATA_CTRL_DATA__cs1__DEFAULT
,
148 cs0
, R_ATA_CTRL_DATA__cs0__DEFAULT
,
149 addr
, R_ATA_CTRL_DATA__addr__DEFAULT
,
150 rw
, R_ATA_CTRL_DATA__rw__DEFAULT
,
151 src_dst
, R_ATA_CTRL_DATA__src_dst__DEFAULT
,
152 handsh
, R_ATA_CTRL_DATA__handsh__DEFAULT
,
153 multi
, R_ATA_CTRL_DATA__multi__DEFAULT
,
154 dma_size
, R_ATA_CTRL_DATA__dma_size__DEFAULT
,
155 data
, R_ATA_CTRL_DATA__data__DEFAULT
159 #if USE_GROUP__Bus_interface_configuration_registers
160 REG_SET__R_BUS_CONFIG(
161 sram_type
, R_BUS_CONFIG__sram_type__DEFAULT
,
162 dma_burst
, R_BUS_CONFIG__dma_burst__DEFAULT
,
163 pcs4_7_wr
, R_BUS_CONFIG__pcs4_7_wr__DEFAULT
,
164 pcs0_3_wr
, R_BUS_CONFIG__pcs0_3_wr__DEFAULT
,
165 sram_wr
, R_BUS_CONFIG__sram_wr__DEFAULT
,
166 flash_wr
, R_BUS_CONFIG__flash_wr__DEFAULT
,
167 pcs4_7_bw
, R_BUS_CONFIG__pcs4_7_bw__DEFAULT
,
168 pcs0_3_bw
, R_BUS_CONFIG__pcs0_3_bw__DEFAULT
,
169 sram_bw
, R_BUS_CONFIG__sram_bw__DEFAULT
,
170 flash_bw
, R_BUS_CONFIG__flash_bw__DEFAULT
174 #if USE_GROUP__Timer_registers
175 REG_SET__R_CLOCK_PRESCALE(
176 ser_presc
, R_CLOCK_PRESCALE__ser_presc__DEFAULT
,
177 tim_presc
, R_CLOCK_PRESCALE__tim_presc__DEFAULT
181 #if USE_GROUP__DMA_registers
182 REG_SET__R_DMA_CH0_CLR_INTR(
183 clr_eop
, R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT
,
184 clr_descr
, R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT
188 #if USE_GROUP__DMA_registers
189 REG_SET__R_DMA_CH1_CLR_INTR(
190 clr_eop
, R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT
,
191 clr_descr
, R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT
195 #if USE_GROUP__DMA_registers
196 REG_SET__R_DMA_CH2_CLR_INTR(
197 clr_eop
, R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT
,
198 clr_descr
, R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT
202 #if USE_GROUP__DMA_registers
203 REG_SET__R_DMA_CH3_CLR_INTR(
204 clr_eop
, R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT
,
205 clr_descr
, R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT
209 #if USE_GROUP__DMA_registers
210 REG_SET__R_DMA_CH4_CLR_INTR(
211 clr_eop
, R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT
,
212 clr_descr
, R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT
216 #if USE_GROUP__DMA_registers
217 REG_SET__R_DMA_CH5_CLR_INTR(
218 clr_eop
, R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT
,
219 clr_descr
, R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT
223 #if USE_GROUP__DMA_registers
224 REG_SET__R_DMA_CH6_CLR_INTR(
225 clr_eop
, R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT
,
226 clr_descr
, R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT
230 #if USE_GROUP__DMA_registers
231 REG_SET__R_DMA_CH7_CLR_INTR(
232 clr_eop
, R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT
,
233 clr_descr
, R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT
237 #if USE_GROUP__DMA_registers
238 REG_SET__R_DMA_CH8_CLR_INTR(
239 clr_eop
, R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT
,
240 clr_descr
, R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT
244 #if USE_GROUP__DMA_registers
245 REG_SET__R_DMA_CH8_SUB0_CLR_INTR(
246 clr_descr
, R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT
250 #if USE_GROUP__DMA_registers
251 REG_SET__R_DMA_CH8_SUB1_CLR_INTR(
252 clr_descr
, R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT
256 #if USE_GROUP__DMA_registers
257 REG_SET__R_DMA_CH8_SUB2_CLR_INTR(
258 clr_descr
, R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT
262 #if USE_GROUP__DMA_registers
263 REG_SET__R_DMA_CH8_SUB3_CLR_INTR(
264 clr_descr
, R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT
268 #if USE_GROUP__DMA_registers
269 REG_SET__R_DMA_CH9_CLR_INTR(
270 clr_eop
, R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT
,
271 clr_descr
, R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT
275 #if USE_GROUP__Bus_interface_configuration_registers
276 REG_SET__R_DRAM_CONFIG(
277 wmm1
, R_DRAM_CONFIG__wmm1__DEFAULT
,
278 wmm0
, R_DRAM_CONFIG__wmm0__DEFAULT
,
279 sh1
, R_DRAM_CONFIG__sh1__DEFAULT
,
280 sh0
, R_DRAM_CONFIG__sh0__DEFAULT
,
281 w
, R_DRAM_CONFIG__w__DEFAULT
,
282 c
, R_DRAM_CONFIG__c__DEFAULT
,
283 e
, R_DRAM_CONFIG__e__DEFAULT
,
284 group_sel
, R_DRAM_CONFIG__group_sel__DEFAULT
,
285 ca1
, R_DRAM_CONFIG__ca1__DEFAULT
,
286 bank23sel
, R_DRAM_CONFIG__bank23sel__DEFAULT
,
287 ca0
, R_DRAM_CONFIG__ca0__DEFAULT
,
288 bank01sel
, R_DRAM_CONFIG__bank01sel__DEFAULT
292 #if USE_GROUP__Bus_interface_configuration_registers
293 REG_SET__R_DRAM_TIMING(
294 sdram
, R_DRAM_TIMING__sdram__DEFAULT
,
295 ref
, R_DRAM_TIMING__ref__DEFAULT
,
296 rp
, R_DRAM_TIMING__rp__DEFAULT
,
297 rs
, R_DRAM_TIMING__rs__DEFAULT
,
298 rh
, R_DRAM_TIMING__rh__DEFAULT
,
299 w
, R_DRAM_TIMING__w__DEFAULT
,
300 c
, R_DRAM_TIMING__c__DEFAULT
,
301 cz
, R_DRAM_TIMING__cz__DEFAULT
,
302 cp
, R_DRAM_TIMING__cp__DEFAULT
,
303 cw
, R_DRAM_TIMING__cw__DEFAULT
307 #if USE_GROUP__External_DMA_registers
308 REG_SET__R_EXT_DMA_0_ADDR(
309 ext0_addr
, R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT
313 #if USE_GROUP__External_DMA_registers
314 REG_SET__R_EXT_DMA_0_CMD(
315 cnt
, R_EXT_DMA_0_CMD__cnt__DEFAULT
,
316 rqpol
, R_EXT_DMA_0_CMD__rqpol__DEFAULT
,
317 apol
, R_EXT_DMA_0_CMD__apol__DEFAULT
,
318 rq_ack
, R_EXT_DMA_0_CMD__rq_ack__DEFAULT
,
319 wid
, R_EXT_DMA_0_CMD__wid__DEFAULT
,
320 dir
, R_EXT_DMA_0_CMD__dir__DEFAULT
,
321 run
, R_EXT_DMA_0_CMD__run__DEFAULT
,
322 trf_count
, R_EXT_DMA_0_CMD__trf_count__DEFAULT
326 #if USE_GROUP__External_DMA_registers
327 REG_SET__R_EXT_DMA_1_ADDR(
328 ext0_addr
, R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT
332 #if USE_GROUP__External_DMA_registers
333 REG_SET__R_EXT_DMA_1_CMD(
334 cnt
, R_EXT_DMA_1_CMD__cnt__DEFAULT
,
335 rqpol
, R_EXT_DMA_1_CMD__rqpol__DEFAULT
,
336 apol
, R_EXT_DMA_1_CMD__apol__DEFAULT
,
337 rq_ack
, R_EXT_DMA_1_CMD__rq_ack__DEFAULT
,
338 wid
, R_EXT_DMA_1_CMD__wid__DEFAULT
,
339 dir
, R_EXT_DMA_1_CMD__dir__DEFAULT
,
340 run
, R_EXT_DMA_1_CMD__run__DEFAULT
,
341 trf_count
, R_EXT_DMA_1_CMD__trf_count__DEFAULT
345 #if USE_GROUP__General_config_registers
346 REG_SET__R_GEN_CONFIG(
347 par_w
, R_GEN_CONFIG__par_w__DEFAULT
,
348 usb2
, R_GEN_CONFIG__usb2__DEFAULT
,
349 usb1
, R_GEN_CONFIG__usb1__DEFAULT
,
350 g24dir
, R_GEN_CONFIG__g24dir__DEFAULT
,
351 g16_23dir
, R_GEN_CONFIG__g16_23dir__DEFAULT
,
352 g8_15dir
, R_GEN_CONFIG__g8_15dir__DEFAULT
,
353 g0dir
, R_GEN_CONFIG__g0dir__DEFAULT
,
354 dma9
, R_GEN_CONFIG__dma9__DEFAULT
,
355 dma8
, R_GEN_CONFIG__dma8__DEFAULT
,
356 dma7
, R_GEN_CONFIG__dma7__DEFAULT
,
357 dma6
, R_GEN_CONFIG__dma6__DEFAULT
,
358 dma5
, R_GEN_CONFIG__dma5__DEFAULT
,
359 dma4
, R_GEN_CONFIG__dma4__DEFAULT
,
360 dma3
, R_GEN_CONFIG__dma3__DEFAULT
,
361 dma2
, R_GEN_CONFIG__dma2__DEFAULT
,
362 mio_w
, R_GEN_CONFIG__mio_w__DEFAULT
,
363 ser3
, R_GEN_CONFIG__ser3__DEFAULT
,
364 par1
, R_GEN_CONFIG__par1__DEFAULT
,
365 scsi0w
, R_GEN_CONFIG__scsi0w__DEFAULT
,
366 scsi1
, R_GEN_CONFIG__scsi1__DEFAULT
,
367 mio
, R_GEN_CONFIG__mio__DEFAULT
,
368 ser2
, R_GEN_CONFIG__ser2__DEFAULT
,
369 par0
, R_GEN_CONFIG__par0__DEFAULT
,
370 ata
, R_GEN_CONFIG__ata__DEFAULT
,
371 scsi0
, R_GEN_CONFIG__scsi0__DEFAULT
375 #if USE_GROUP__General_config_registers
376 REG_SET__R_GEN_CONFIG_II(
377 sermode3
, R_GEN_CONFIG_II__sermode3__DEFAULT
,
378 sermode1
, R_GEN_CONFIG_II__sermode1__DEFAULT
,
379 ext_clk
, R_GEN_CONFIG_II__ext_clk__DEFAULT
,
380 ser3
, R_GEN_CONFIG_II__ser3__DEFAULT
,
381 ser2
, R_GEN_CONFIG_II__ser2__DEFAULT
385 #if USE_GROUP__Interrupt_mask_and_status_registers
386 REG_SET__R_IRQ_MASK0_CLR(
387 nmi_pin
, R_IRQ_MASK0_CLR__nmi_pin__DEFAULT
,
388 watchdog_nmi
, R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT
,
389 sqe_test_error
, R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT
,
390 carrier_loss
, R_IRQ_MASK0_CLR__carrier_loss__DEFAULT
,
391 deferred
, R_IRQ_MASK0_CLR__deferred__DEFAULT
,
392 late_col
, R_IRQ_MASK0_CLR__late_col__DEFAULT
,
393 multiple_col
, R_IRQ_MASK0_CLR__multiple_col__DEFAULT
,
394 single_col
, R_IRQ_MASK0_CLR__single_col__DEFAULT
,
395 congestion
, R_IRQ_MASK0_CLR__congestion__DEFAULT
,
396 oversize
, R_IRQ_MASK0_CLR__oversize__DEFAULT
,
397 alignment_error
, R_IRQ_MASK0_CLR__alignment_error__DEFAULT
,
398 crc_error
, R_IRQ_MASK0_CLR__crc_error__DEFAULT
,
399 overrun
, R_IRQ_MASK0_CLR__overrun__DEFAULT
,
400 underrun
, R_IRQ_MASK0_CLR__underrun__DEFAULT
,
401 excessive_col
, R_IRQ_MASK0_CLR__excessive_col__DEFAULT
,
402 mdio
, R_IRQ_MASK0_CLR__mdio__DEFAULT
,
403 ata_drq3
, R_IRQ_MASK0_CLR__ata_drq3__DEFAULT
,
404 ata_drq2
, R_IRQ_MASK0_CLR__ata_drq2__DEFAULT
,
405 ata_drq1
, R_IRQ_MASK0_CLR__ata_drq1__DEFAULT
,
406 ata_drq0
, R_IRQ_MASK0_CLR__ata_drq0__DEFAULT
,
407 par0_ecp_cmd
, R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT
,
408 par0_peri
, R_IRQ_MASK0_CLR__par0_peri__DEFAULT
,
409 par0_data
, R_IRQ_MASK0_CLR__par0_data__DEFAULT
,
410 par0_ready
, R_IRQ_MASK0_CLR__par0_ready__DEFAULT
,
411 ata_dmaend
, R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT
,
412 irq_ext_vector_nr
, R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT
,
413 irq_int_vector_nr
, R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT
,
414 ext_dma1
, R_IRQ_MASK0_CLR__ext_dma1__DEFAULT
,
415 ext_dma0
, R_IRQ_MASK0_CLR__ext_dma0__DEFAULT
,
416 timer1
, R_IRQ_MASK0_CLR__timer1__DEFAULT
,
417 timer0
, R_IRQ_MASK0_CLR__timer0__DEFAULT
421 #if USE_GROUP__Interrupt_mask_and_status_registers
422 REG_SET__R_IRQ_MASK0_SET(
423 nmi_pin
, R_IRQ_MASK0_SET__nmi_pin__DEFAULT
,
424 watchdog_nmi
, R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT
,
425 sqe_test_error
, R_IRQ_MASK0_SET__sqe_test_error__DEFAULT
,
426 carrier_loss
, R_IRQ_MASK0_SET__carrier_loss__DEFAULT
,
427 deferred
, R_IRQ_MASK0_SET__deferred__DEFAULT
,
428 late_col
, R_IRQ_MASK0_SET__late_col__DEFAULT
,
429 multiple_col
, R_IRQ_MASK0_SET__multiple_col__DEFAULT
,
430 single_col
, R_IRQ_MASK0_SET__single_col__DEFAULT
,
431 congestion
, R_IRQ_MASK0_SET__congestion__DEFAULT
,
432 oversize
, R_IRQ_MASK0_SET__oversize__DEFAULT
,
433 alignment_error
, R_IRQ_MASK0_SET__alignment_error__DEFAULT
,
434 crc_error
, R_IRQ_MASK0_SET__crc_error__DEFAULT
,
435 overrun
, R_IRQ_MASK0_SET__overrun__DEFAULT
,
436 underrun
, R_IRQ_MASK0_SET__underrun__DEFAULT
,
437 excessive_col
, R_IRQ_MASK0_SET__excessive_col__DEFAULT
,
438 mdio
, R_IRQ_MASK0_SET__mdio__DEFAULT
,
439 ata_drq3
, R_IRQ_MASK0_SET__ata_drq3__DEFAULT
,
440 ata_drq2
, R_IRQ_MASK0_SET__ata_drq2__DEFAULT
,
441 ata_drq1
, R_IRQ_MASK0_SET__ata_drq1__DEFAULT
,
442 ata_drq0
, R_IRQ_MASK0_SET__ata_drq0__DEFAULT
,
443 par0_ecp_cmd
, R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT
,
444 par0_peri
, R_IRQ_MASK0_SET__par0_peri__DEFAULT
,
445 par0_data
, R_IRQ_MASK0_SET__par0_data__DEFAULT
,
446 par0_ready
, R_IRQ_MASK0_SET__par0_ready__DEFAULT
,
447 ata_dmaend
, R_IRQ_MASK0_SET__ata_dmaend__DEFAULT
,
448 irq_ext_vector_nr
, R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT
,
449 irq_int_vector_nr
, R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT
,
450 ext_dma1
, R_IRQ_MASK0_SET__ext_dma1__DEFAULT
,
451 ext_dma0
, R_IRQ_MASK0_SET__ext_dma0__DEFAULT
,
452 timer1
, R_IRQ_MASK0_SET__timer1__DEFAULT
,
453 timer0
, R_IRQ_MASK0_SET__timer0__DEFAULT
457 #if USE_GROUP__Interrupt_mask_and_status_registers
458 REG_SET__R_IRQ_MASK1_CLR(
459 sw_int7
, R_IRQ_MASK1_CLR__sw_int7__DEFAULT
,
460 sw_int6
, R_IRQ_MASK1_CLR__sw_int6__DEFAULT
,
461 sw_int5
, R_IRQ_MASK1_CLR__sw_int5__DEFAULT
,
462 sw_int4
, R_IRQ_MASK1_CLR__sw_int4__DEFAULT
,
463 sw_int3
, R_IRQ_MASK1_CLR__sw_int3__DEFAULT
,
464 sw_int2
, R_IRQ_MASK1_CLR__sw_int2__DEFAULT
,
465 sw_int1
, R_IRQ_MASK1_CLR__sw_int1__DEFAULT
,
466 sw_int0
, R_IRQ_MASK1_CLR__sw_int0__DEFAULT
,
467 par1_ecp_cmd
, R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT
,
468 par1_peri
, R_IRQ_MASK1_CLR__par1_peri__DEFAULT
,
469 par1_data
, R_IRQ_MASK1_CLR__par1_data__DEFAULT
,
470 par1_ready
, R_IRQ_MASK1_CLR__par1_ready__DEFAULT
,
471 ser3_ready
, R_IRQ_MASK1_CLR__ser3_ready__DEFAULT
,
472 ser3_data
, R_IRQ_MASK1_CLR__ser3_data__DEFAULT
,
473 ser2_ready
, R_IRQ_MASK1_CLR__ser2_ready__DEFAULT
,
474 ser2_data
, R_IRQ_MASK1_CLR__ser2_data__DEFAULT
,
475 ser1_ready
, R_IRQ_MASK1_CLR__ser1_ready__DEFAULT
,
476 ser1_data
, R_IRQ_MASK1_CLR__ser1_data__DEFAULT
,
477 ser0_ready
, R_IRQ_MASK1_CLR__ser0_ready__DEFAULT
,
478 ser0_data
, R_IRQ_MASK1_CLR__ser0_data__DEFAULT
,
479 pa7
, R_IRQ_MASK1_CLR__pa7__DEFAULT
,
480 pa6
, R_IRQ_MASK1_CLR__pa6__DEFAULT
,
481 pa5
, R_IRQ_MASK1_CLR__pa5__DEFAULT
,
482 pa4
, R_IRQ_MASK1_CLR__pa4__DEFAULT
,
483 pa3
, R_IRQ_MASK1_CLR__pa3__DEFAULT
,
484 pa2
, R_IRQ_MASK1_CLR__pa2__DEFAULT
,
485 pa1
, R_IRQ_MASK1_CLR__pa1__DEFAULT
,
486 pa0
, R_IRQ_MASK1_CLR__pa0__DEFAULT
490 #if USE_GROUP__Interrupt_mask_and_status_registers
491 REG_SET__R_IRQ_MASK1_SET(
492 sw_int7
, R_IRQ_MASK1_SET__sw_int7__DEFAULT
,
493 sw_int6
, R_IRQ_MASK1_SET__sw_int6__DEFAULT
,
494 sw_int5
, R_IRQ_MASK1_SET__sw_int5__DEFAULT
,
495 sw_int4
, R_IRQ_MASK1_SET__sw_int4__DEFAULT
,
496 sw_int3
, R_IRQ_MASK1_SET__sw_int3__DEFAULT
,
497 sw_int2
, R_IRQ_MASK1_SET__sw_int2__DEFAULT
,
498 sw_int1
, R_IRQ_MASK1_SET__sw_int1__DEFAULT
,
499 sw_int0
, R_IRQ_MASK1_SET__sw_int0__DEFAULT
,
500 par1_ecp_cmd
, R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT
,
501 par1_peri
, R_IRQ_MASK1_SET__par1_peri__DEFAULT
,
502 par1_data
, R_IRQ_MASK1_SET__par1_data__DEFAULT
,
503 par1_ready
, R_IRQ_MASK1_SET__par1_ready__DEFAULT
,
504 ser3_ready
, R_IRQ_MASK1_SET__ser3_ready__DEFAULT
,
505 ser3_data
, R_IRQ_MASK1_SET__ser3_data__DEFAULT
,
506 ser2_ready
, R_IRQ_MASK1_SET__ser2_ready__DEFAULT
,
507 ser2_data
, R_IRQ_MASK1_SET__ser2_data__DEFAULT
,
508 ser1_ready
, R_IRQ_MASK1_SET__ser1_ready__DEFAULT
,
509 ser1_data
, R_IRQ_MASK1_SET__ser1_data__DEFAULT
,
510 ser0_ready
, R_IRQ_MASK1_SET__ser0_ready__DEFAULT
,
511 ser0_data
, R_IRQ_MASK1_SET__ser0_data__DEFAULT
,
512 pa7
, R_IRQ_MASK1_SET__pa7__DEFAULT
,
513 pa6
, R_IRQ_MASK1_SET__pa6__DEFAULT
,
514 pa5
, R_IRQ_MASK1_SET__pa5__DEFAULT
,
515 pa4
, R_IRQ_MASK1_SET__pa4__DEFAULT
,
516 pa3
, R_IRQ_MASK1_SET__pa3__DEFAULT
,
517 pa2
, R_IRQ_MASK1_SET__pa2__DEFAULT
,
518 pa1
, R_IRQ_MASK1_SET__pa1__DEFAULT
,
519 pa0
, R_IRQ_MASK1_SET__pa0__DEFAULT
523 #if USE_GROUP__Interrupt_mask_and_status_registers
524 REG_SET__R_IRQ_MASK2_CLR(
525 dma8_sub3_descr
, R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT
,
526 dma8_sub2_descr
, R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT
,
527 dma8_sub1_descr
, R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT
,
528 dma8_sub0_descr
, R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT
,
529 dma9_eop
, R_IRQ_MASK2_CLR__dma9_eop__DEFAULT
,
530 dma9_descr
, R_IRQ_MASK2_CLR__dma9_descr__DEFAULT
,
531 dma8_eop
, R_IRQ_MASK2_CLR__dma8_eop__DEFAULT
,
532 dma8_descr
, R_IRQ_MASK2_CLR__dma8_descr__DEFAULT
,
533 dma7_eop
, R_IRQ_MASK2_CLR__dma7_eop__DEFAULT
,
534 dma7_descr
, R_IRQ_MASK2_CLR__dma7_descr__DEFAULT
,
535 dma6_eop
, R_IRQ_MASK2_CLR__dma6_eop__DEFAULT
,
536 dma6_descr
, R_IRQ_MASK2_CLR__dma6_descr__DEFAULT
,
537 dma5_eop
, R_IRQ_MASK2_CLR__dma5_eop__DEFAULT
,
538 dma5_descr
, R_IRQ_MASK2_CLR__dma5_descr__DEFAULT
,
539 dma4_eop
, R_IRQ_MASK2_CLR__dma4_eop__DEFAULT
,
540 dma4_descr
, R_IRQ_MASK2_CLR__dma4_descr__DEFAULT
,
541 dma3_eop
, R_IRQ_MASK2_CLR__dma3_eop__DEFAULT
,
542 dma3_descr
, R_IRQ_MASK2_CLR__dma3_descr__DEFAULT
,
543 dma2_eop
, R_IRQ_MASK2_CLR__dma2_eop__DEFAULT
,
544 dma2_descr
, R_IRQ_MASK2_CLR__dma2_descr__DEFAULT
,
545 dma1_eop
, R_IRQ_MASK2_CLR__dma1_eop__DEFAULT
,
546 dma1_descr
, R_IRQ_MASK2_CLR__dma1_descr__DEFAULT
,
547 dma0_eop
, R_IRQ_MASK2_CLR__dma0_eop__DEFAULT
,
548 dma0_descr
, R_IRQ_MASK2_CLR__dma0_descr__DEFAULT
552 #if USE_GROUP__Interrupt_mask_and_status_registers
553 REG_SET__R_IRQ_MASK2_SET(
554 dma8_sub3_descr
, R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT
,
555 dma8_sub2_descr
, R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT
,
556 dma8_sub1_descr
, R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT
,
557 dma8_sub0_descr
, R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT
,
558 dma9_eop
, R_IRQ_MASK2_SET__dma9_eop__DEFAULT
,
559 dma9_descr
, R_IRQ_MASK2_SET__dma9_descr__DEFAULT
,
560 dma8_eop
, R_IRQ_MASK2_SET__dma8_eop__DEFAULT
,
561 dma8_descr
, R_IRQ_MASK2_SET__dma8_descr__DEFAULT
,
562 dma7_eop
, R_IRQ_MASK2_SET__dma7_eop__DEFAULT
,
563 dma7_descr
, R_IRQ_MASK2_SET__dma7_descr__DEFAULT
,
564 dma6_eop
, R_IRQ_MASK2_SET__dma6_eop__DEFAULT
,
565 dma6_descr
, R_IRQ_MASK2_SET__dma6_descr__DEFAULT
,
566 dma5_eop
, R_IRQ_MASK2_SET__dma5_eop__DEFAULT
,
567 dma5_descr
, R_IRQ_MASK2_SET__dma5_descr__DEFAULT
,
568 dma4_eop
, R_IRQ_MASK2_SET__dma4_eop__DEFAULT
,
569 dma4_descr
, R_IRQ_MASK2_SET__dma4_descr__DEFAULT
,
570 dma3_eop
, R_IRQ_MASK2_SET__dma3_eop__DEFAULT
,
571 dma3_descr
, R_IRQ_MASK2_SET__dma3_descr__DEFAULT
,
572 dma2_eop
, R_IRQ_MASK2_SET__dma2_eop__DEFAULT
,
573 dma2_descr
, R_IRQ_MASK2_SET__dma2_descr__DEFAULT
,
574 dma1_eop
, R_IRQ_MASK2_SET__dma1_eop__DEFAULT
,
575 dma1_descr
, R_IRQ_MASK2_SET__dma1_descr__DEFAULT
,
576 dma0_eop
, R_IRQ_MASK2_SET__dma0_eop__DEFAULT
,
577 dma0_descr
, R_IRQ_MASK2_SET__dma0_descr__DEFAULT
581 #if USE_GROUP__MMU_registers
582 REG_SET__R_MMU_CONFIG(
583 mmu_enable
, R_MMU_CONFIG__mmu_enable__DEFAULT
,
584 inv_excp
, R_MMU_CONFIG__inv_excp__DEFAULT
,
585 acc_excp
, R_MMU_CONFIG__acc_excp__DEFAULT
,
586 we_excp
, R_MMU_CONFIG__we_excp__DEFAULT
,
587 seg_f
, R_MMU_CONFIG__seg_f__DEFAULT
,
588 seg_e
, R_MMU_CONFIG__seg_e__DEFAULT
,
589 seg_d
, R_MMU_CONFIG__seg_d__DEFAULT
,
590 seg_c
, R_MMU_CONFIG__seg_c__DEFAULT
,
591 seg_b
, R_MMU_CONFIG__seg_b__DEFAULT
,
592 seg_a
, R_MMU_CONFIG__seg_a__DEFAULT
,
593 seg_9
, R_MMU_CONFIG__seg_9__DEFAULT
,
594 seg_8
, R_MMU_CONFIG__seg_8__DEFAULT
,
595 seg_7
, R_MMU_CONFIG__seg_7__DEFAULT
,
596 seg_6
, R_MMU_CONFIG__seg_6__DEFAULT
,
597 seg_5
, R_MMU_CONFIG__seg_5__DEFAULT
,
598 seg_4
, R_MMU_CONFIG__seg_4__DEFAULT
,
599 seg_3
, R_MMU_CONFIG__seg_3__DEFAULT
,
600 seg_2
, R_MMU_CONFIG__seg_2__DEFAULT
,
601 seg_1
, R_MMU_CONFIG__seg_1__DEFAULT
,
602 seg_0
, R_MMU_CONFIG__seg_0__DEFAULT
606 #if USE_GROUP__MMU_registers
608 inv_excp
, R_MMU_CTRL__inv_excp__DEFAULT
,
609 acc_excp
, R_MMU_CTRL__acc_excp__DEFAULT
,
610 we_excp
, R_MMU_CTRL__we_excp__DEFAULT
614 #if USE_GROUP__MMU_registers
615 REG_SET__R_MMU_ENABLE(
616 mmu_enable
, R_MMU_ENABLE__mmu_enable__DEFAULT
620 #if USE_GROUP__MMU_registers
621 REG_SET__R_MMU_KBASE_HI(
622 base_f
, R_MMU_KBASE_HI__base_f__DEFAULT
,
623 base_e
, R_MMU_KBASE_HI__base_e__DEFAULT
,
624 base_d
, R_MMU_KBASE_HI__base_d__DEFAULT
,
625 base_c
, R_MMU_KBASE_HI__base_c__DEFAULT
,
626 base_b
, R_MMU_KBASE_HI__base_b__DEFAULT
,
627 base_a
, R_MMU_KBASE_HI__base_a__DEFAULT
,
628 base_9
, R_MMU_KBASE_HI__base_9__DEFAULT
,
629 base_8
, R_MMU_KBASE_HI__base_8__DEFAULT
633 #if USE_GROUP__MMU_registers
634 REG_SET__R_MMU_KBASE_LO(
635 base_7
, R_MMU_KBASE_LO__base_7__DEFAULT
,
636 base_6
, R_MMU_KBASE_LO__base_6__DEFAULT
,
637 base_5
, R_MMU_KBASE_LO__base_5__DEFAULT
,
638 base_4
, R_MMU_KBASE_LO__base_4__DEFAULT
,
639 base_3
, R_MMU_KBASE_LO__base_3__DEFAULT
,
640 base_2
, R_MMU_KBASE_LO__base_2__DEFAULT
,
641 base_1
, R_MMU_KBASE_LO__base_1__DEFAULT
,
642 base_0
, R_MMU_KBASE_LO__base_0__DEFAULT
646 #if USE_GROUP__MMU_registers
648 seg_f
, R_MMU_KSEG__seg_f__DEFAULT
,
649 seg_e
, R_MMU_KSEG__seg_e__DEFAULT
,
650 seg_d
, R_MMU_KSEG__seg_d__DEFAULT
,
651 seg_c
, R_MMU_KSEG__seg_c__DEFAULT
,
652 seg_b
, R_MMU_KSEG__seg_b__DEFAULT
,
653 seg_a
, R_MMU_KSEG__seg_a__DEFAULT
,
654 seg_9
, R_MMU_KSEG__seg_9__DEFAULT
,
655 seg_8
, R_MMU_KSEG__seg_8__DEFAULT
,
656 seg_7
, R_MMU_KSEG__seg_7__DEFAULT
,
657 seg_6
, R_MMU_KSEG__seg_6__DEFAULT
,
658 seg_5
, R_MMU_KSEG__seg_5__DEFAULT
,
659 seg_4
, R_MMU_KSEG__seg_4__DEFAULT
,
660 seg_3
, R_MMU_KSEG__seg_3__DEFAULT
,
661 seg_2
, R_MMU_KSEG__seg_2__DEFAULT
,
662 seg_1
, R_MMU_KSEG__seg_1__DEFAULT
,
663 seg_0
, R_MMU_KSEG__seg_0__DEFAULT
667 #if USE_GROUP__Network_interface_registers
668 REG_SET__R_NETWORK_GA_0(
669 ga_low
, R_NETWORK_GA_0__ga_low__DEFAULT
673 #if USE_GROUP__Network_interface_registers
674 REG_SET__R_NETWORK_GA_1(
675 ga_high
, R_NETWORK_GA_1__ga_high__DEFAULT
679 #if USE_GROUP__Network_interface_registers
680 REG_SET__R_NETWORK_GEN_CONFIG(
681 loopback
, R_NETWORK_GEN_CONFIG__loopback__DEFAULT
,
682 frame
, R_NETWORK_GEN_CONFIG__frame__DEFAULT
,
683 vg
, R_NETWORK_GEN_CONFIG__vg__DEFAULT
,
684 phy
, R_NETWORK_GEN_CONFIG__phy__DEFAULT
,
685 enable
, R_NETWORK_GEN_CONFIG__enable__DEFAULT
689 #if USE_GROUP__Network_interface_registers
690 REG_SET__R_NETWORK_MGM_CTRL(
691 txd_pins
, R_NETWORK_MGM_CTRL__txd_pins__DEFAULT
,
692 txer_pin
, R_NETWORK_MGM_CTRL__txer_pin__DEFAULT
,
693 mdck
, R_NETWORK_MGM_CTRL__mdck__DEFAULT
,
694 mdoe
, R_NETWORK_MGM_CTRL__mdoe__DEFAULT
,
695 mdio
, R_NETWORK_MGM_CTRL__mdio__DEFAULT
699 #if USE_GROUP__Network_interface_registers
700 REG_SET__R_NETWORK_REC_CONFIG(
701 max_size
, R_NETWORK_REC_CONFIG__max_size__DEFAULT
,
702 duplex
, R_NETWORK_REC_CONFIG__duplex__DEFAULT
,
703 bad_crc
, R_NETWORK_REC_CONFIG__bad_crc__DEFAULT
,
704 oversize
, R_NETWORK_REC_CONFIG__oversize__DEFAULT
,
705 undersize
, R_NETWORK_REC_CONFIG__undersize__DEFAULT
,
706 all_roots
, R_NETWORK_REC_CONFIG__all_roots__DEFAULT
,
707 tr_broadcast
, R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT
,
708 broadcast
, R_NETWORK_REC_CONFIG__broadcast__DEFAULT
,
709 individual
, R_NETWORK_REC_CONFIG__individual__DEFAULT
,
710 ma1
, R_NETWORK_REC_CONFIG__ma1__DEFAULT
,
711 ma0
, R_NETWORK_REC_CONFIG__ma0__DEFAULT
715 #if USE_GROUP__Network_interface_registers
716 REG_SET__R_NETWORK_SA_0(
717 ma0_low
, R_NETWORK_SA_0__ma0_low__DEFAULT
721 #if USE_GROUP__Network_interface_registers
722 REG_SET__R_NETWORK_SA_1(
723 ma1_low
, R_NETWORK_SA_1__ma1_low__DEFAULT
,
724 ma0_high
, R_NETWORK_SA_1__ma0_high__DEFAULT
728 #if USE_GROUP__Network_interface_registers
729 REG_SET__R_NETWORK_SA_2(
730 ma1_high
, R_NETWORK_SA_2__ma1_high__DEFAULT
734 #if USE_GROUP__Network_interface_registers
735 REG_SET__R_NETWORK_TR_CTRL(
736 clr_error
, R_NETWORK_TR_CTRL__clr_error__DEFAULT
,
737 delay
, R_NETWORK_TR_CTRL__delay__DEFAULT
,
738 cancel
, R_NETWORK_TR_CTRL__cancel__DEFAULT
,
739 cd
, R_NETWORK_TR_CTRL__cd__DEFAULT
,
740 retry
, R_NETWORK_TR_CTRL__retry__DEFAULT
,
741 pad
, R_NETWORK_TR_CTRL__pad__DEFAULT
,
742 crc
, R_NETWORK_TR_CTRL__crc__DEFAULT
746 #if USE_GROUP__Parallel_printer_port_registers
747 REG_SET__R_PAR0_CONFIG(
748 ioe
, R_PAR0_CONFIG__ioe__DEFAULT
,
749 iseli
, R_PAR0_CONFIG__iseli__DEFAULT
,
750 iautofd
, R_PAR0_CONFIG__iautofd__DEFAULT
,
751 istrb
, R_PAR0_CONFIG__istrb__DEFAULT
,
752 iinit
, R_PAR0_CONFIG__iinit__DEFAULT
,
753 iperr
, R_PAR0_CONFIG__iperr__DEFAULT
,
754 iack
, R_PAR0_CONFIG__iack__DEFAULT
,
755 ibusy
, R_PAR0_CONFIG__ibusy__DEFAULT
,
756 ifault
, R_PAR0_CONFIG__ifault__DEFAULT
,
757 isel
, R_PAR0_CONFIG__isel__DEFAULT
,
758 ext_mode
, R_PAR0_CONFIG__ext_mode__DEFAULT
,
759 wide
, R_PAR0_CONFIG__wide__DEFAULT
,
760 dma
, R_PAR0_CONFIG__dma__DEFAULT
,
761 rle_in
, R_PAR0_CONFIG__rle_in__DEFAULT
,
762 rle_out
, R_PAR0_CONFIG__rle_out__DEFAULT
,
763 enable
, R_PAR0_CONFIG__enable__DEFAULT
,
764 force
, R_PAR0_CONFIG__force__DEFAULT
,
765 ign_ack
, R_PAR0_CONFIG__ign_ack__DEFAULT
,
766 oe_ack
, R_PAR0_CONFIG__oe_ack__DEFAULT
,
767 mode
, R_PAR0_CONFIG__mode__DEFAULT
771 #if USE_GROUP__Parallel_printer_port_registers
772 REG_SET__R_PAR0_CTRL(
773 ctrl
, R_PAR0_CTRL__ctrl__DEFAULT
777 #if USE_GROUP__Parallel_printer_port_registers
778 REG_SET__R_PAR0_CTRL_DATA(
779 peri_int
, R_PAR0_CTRL_DATA__peri_int__DEFAULT
,
780 oe
, R_PAR0_CTRL_DATA__oe__DEFAULT
,
781 seli
, R_PAR0_CTRL_DATA__seli__DEFAULT
,
782 autofd
, R_PAR0_CTRL_DATA__autofd__DEFAULT
,
783 strb
, R_PAR0_CTRL_DATA__strb__DEFAULT
,
784 init
, R_PAR0_CTRL_DATA__init__DEFAULT
,
785 ecp_cmd
, R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT
,
786 data
, R_PAR0_CTRL_DATA__data__DEFAULT
790 #if USE_GROUP__Parallel_printer_port_registers
791 REG_SET__R_PAR0_DELAY(
792 fine_hold
, R_PAR0_DELAY__fine_hold__DEFAULT
,
793 hold
, R_PAR0_DELAY__hold__DEFAULT
,
794 fine_strb
, R_PAR0_DELAY__fine_strb__DEFAULT
,
795 strobe
, R_PAR0_DELAY__strobe__DEFAULT
,
796 fine_setup
, R_PAR0_DELAY__fine_setup__DEFAULT
,
797 setup
, R_PAR0_DELAY__setup__DEFAULT
801 #if USE_GROUP__Parallel_printer_port_registers
802 REG_SET__R_PAR1_CONFIG(
803 ioe
, R_PAR1_CONFIG__ioe__DEFAULT
,
804 iseli
, R_PAR1_CONFIG__iseli__DEFAULT
,
805 iautofd
, R_PAR1_CONFIG__iautofd__DEFAULT
,
806 istrb
, R_PAR1_CONFIG__istrb__DEFAULT
,
807 iinit
, R_PAR1_CONFIG__iinit__DEFAULT
,
808 iperr
, R_PAR1_CONFIG__iperr__DEFAULT
,
809 iack
, R_PAR1_CONFIG__iack__DEFAULT
,
810 ibusy
, R_PAR1_CONFIG__ibusy__DEFAULT
,
811 ifault
, R_PAR1_CONFIG__ifault__DEFAULT
,
812 isel
, R_PAR1_CONFIG__isel__DEFAULT
,
813 ext_mode
, R_PAR1_CONFIG__ext_mode__DEFAULT
,
814 dma
, R_PAR1_CONFIG__dma__DEFAULT
,
815 rle_in
, R_PAR1_CONFIG__rle_in__DEFAULT
,
816 rle_out
, R_PAR1_CONFIG__rle_out__DEFAULT
,
817 enable
, R_PAR1_CONFIG__enable__DEFAULT
,
818 force
, R_PAR1_CONFIG__force__DEFAULT
,
819 ign_ack
, R_PAR1_CONFIG__ign_ack__DEFAULT
,
820 oe_ack
, R_PAR1_CONFIG__oe_ack__DEFAULT
,
821 mode
, R_PAR1_CONFIG__mode__DEFAULT
825 #if USE_GROUP__Parallel_printer_port_registers
826 REG_SET__R_PAR1_CTRL(
827 ctrl
, R_PAR1_CTRL__ctrl__DEFAULT
831 #if USE_GROUP__Parallel_printer_port_registers
832 REG_SET__R_PAR1_CTRL_DATA(
833 peri_int
, R_PAR1_CTRL_DATA__peri_int__DEFAULT
,
834 oe
, R_PAR1_CTRL_DATA__oe__DEFAULT
,
835 seli
, R_PAR1_CTRL_DATA__seli__DEFAULT
,
836 autofd
, R_PAR1_CTRL_DATA__autofd__DEFAULT
,
837 strb
, R_PAR1_CTRL_DATA__strb__DEFAULT
,
838 init
, R_PAR1_CTRL_DATA__init__DEFAULT
,
839 ecp_cmd
, R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT
,
840 data
, R_PAR1_CTRL_DATA__data__DEFAULT
844 #if USE_GROUP__Parallel_printer_port_registers
845 REG_SET__R_PAR1_DELAY(
846 fine_hold
, R_PAR1_DELAY__fine_hold__DEFAULT
,
847 hold
, R_PAR1_DELAY__hold__DEFAULT
,
848 fine_strb
, R_PAR1_DELAY__fine_strb__DEFAULT
,
849 strobe
, R_PAR1_DELAY__strobe__DEFAULT
,
850 fine_setup
, R_PAR1_DELAY__fine_setup__DEFAULT
,
851 setup
, R_PAR1_DELAY__setup__DEFAULT
855 #if USE_GROUP__General_port_configuration_registers
856 REG_SET__R_PORT_PA_DATA(
857 data_out
, R_PORT_PA_DATA__data_out__DEFAULT
861 #if USE_GROUP__General_port_configuration_registers
862 REG_SET__R_PORT_PA_DIR(
863 dir7
, R_PORT_PA_DIR__dir7__DEFAULT
,
864 dir6
, R_PORT_PA_DIR__dir6__DEFAULT
,
865 dir5
, R_PORT_PA_DIR__dir5__DEFAULT
,
866 dir4
, R_PORT_PA_DIR__dir4__DEFAULT
,
867 dir3
, R_PORT_PA_DIR__dir3__DEFAULT
,
868 dir2
, R_PORT_PA_DIR__dir2__DEFAULT
,
869 dir1
, R_PORT_PA_DIR__dir1__DEFAULT
,
870 dir0
, R_PORT_PA_DIR__dir0__DEFAULT
874 #if USE_GROUP__General_port_configuration_registers
875 REG_SET__R_PORT_PA_SET(
876 dir7
, R_PORT_PA_SET__dir7__DEFAULT
,
877 dir6
, R_PORT_PA_SET__dir6__DEFAULT
,
878 dir5
, R_PORT_PA_SET__dir5__DEFAULT
,
879 dir4
, R_PORT_PA_SET__dir4__DEFAULT
,
880 dir3
, R_PORT_PA_SET__dir3__DEFAULT
,
881 dir2
, R_PORT_PA_SET__dir2__DEFAULT
,
882 dir1
, R_PORT_PA_SET__dir1__DEFAULT
,
883 dir0
, R_PORT_PA_SET__dir0__DEFAULT
,
884 data_out
, R_PORT_PA_SET__data_out__DEFAULT
888 #if USE_GROUP__General_port_configuration_registers
889 REG_SET__R_PORT_PB_CONFIG(
890 cs7
, R_PORT_PB_CONFIG__cs7__DEFAULT
,
891 cs6
, R_PORT_PB_CONFIG__cs6__DEFAULT
,
892 cs5
, R_PORT_PB_CONFIG__cs5__DEFAULT
,
893 cs4
, R_PORT_PB_CONFIG__cs4__DEFAULT
,
894 cs3
, R_PORT_PB_CONFIG__cs3__DEFAULT
,
895 cs2
, R_PORT_PB_CONFIG__cs2__DEFAULT
,
896 scsi1
, R_PORT_PB_CONFIG__scsi1__DEFAULT
,
897 scsi0
, R_PORT_PB_CONFIG__scsi0__DEFAULT
901 #if USE_GROUP__General_port_configuration_registers
902 REG_SET__R_PORT_PB_DATA(
903 data_out
, R_PORT_PB_DATA__data_out__DEFAULT
907 #if USE_GROUP__General_port_configuration_registers
908 REG_SET__R_PORT_PB_DIR(
909 dir7
, R_PORT_PB_DIR__dir7__DEFAULT
,
910 dir6
, R_PORT_PB_DIR__dir6__DEFAULT
,
911 dir5
, R_PORT_PB_DIR__dir5__DEFAULT
,
912 dir4
, R_PORT_PB_DIR__dir4__DEFAULT
,
913 dir3
, R_PORT_PB_DIR__dir3__DEFAULT
,
914 dir2
, R_PORT_PB_DIR__dir2__DEFAULT
,
915 dir1
, R_PORT_PB_DIR__dir1__DEFAULT
,
916 dir0
, R_PORT_PB_DIR__dir0__DEFAULT
920 #if USE_GROUP__General_port_configuration_registers
921 REG_SET__R_PORT_PB_I2C(
922 syncser3
, R_PORT_PB_I2C__syncser3__DEFAULT
,
923 syncser1
, R_PORT_PB_I2C__syncser1__DEFAULT
,
924 i2c_en
, R_PORT_PB_I2C__i2c_en__DEFAULT
,
925 i2c_d
, R_PORT_PB_I2C__i2c_d__DEFAULT
,
926 i2c_clk
, R_PORT_PB_I2C__i2c_clk__DEFAULT
,
927 i2c_oe_
, R_PORT_PB_I2C__i2c_oe___DEFAULT
931 #if USE_GROUP__General_port_configuration_registers
932 REG_SET__R_PORT_PB_SET(
933 syncser3
, R_PORT_PB_SET__syncser3__DEFAULT
,
934 syncser1
, R_PORT_PB_SET__syncser1__DEFAULT
,
935 i2c_en
, R_PORT_PB_SET__i2c_en__DEFAULT
,
936 i2c_d
, R_PORT_PB_SET__i2c_d__DEFAULT
,
937 i2c_clk
, R_PORT_PB_SET__i2c_clk__DEFAULT
,
938 i2c_oe_
, R_PORT_PB_SET__i2c_oe___DEFAULT
,
939 cs7
, R_PORT_PB_SET__cs7__DEFAULT
,
940 cs6
, R_PORT_PB_SET__cs6__DEFAULT
,
941 cs5
, R_PORT_PB_SET__cs5__DEFAULT
,
942 cs4
, R_PORT_PB_SET__cs4__DEFAULT
,
943 cs3
, R_PORT_PB_SET__cs3__DEFAULT
,
944 cs2
, R_PORT_PB_SET__cs2__DEFAULT
,
945 scsi1
, R_PORT_PB_SET__scsi1__DEFAULT
,
946 scsi0
, R_PORT_PB_SET__scsi0__DEFAULT
,
947 dir7
, R_PORT_PB_SET__dir7__DEFAULT
,
948 dir6
, R_PORT_PB_SET__dir6__DEFAULT
,
949 dir5
, R_PORT_PB_SET__dir5__DEFAULT
,
950 dir4
, R_PORT_PB_SET__dir4__DEFAULT
,
951 dir3
, R_PORT_PB_SET__dir3__DEFAULT
,
952 dir2
, R_PORT_PB_SET__dir2__DEFAULT
,
953 dir1
, R_PORT_PB_SET__dir1__DEFAULT
,
954 dir0
, R_PORT_PB_SET__dir0__DEFAULT
,
955 data_out
, R_PORT_PB_SET__data_out__DEFAULT
959 #if USE_GROUP__SCSI_registers
960 REG_SET__R_SCSI0_CMD(
961 asynch_setup
, R_SCSI0_CMD__asynch_setup__DEFAULT
,
962 command
, R_SCSI0_CMD__command__DEFAULT
966 #if USE_GROUP__SCSI_registers
967 REG_SET__R_SCSI0_CMD_DATA(
968 parity_in
, R_SCSI0_CMD_DATA__parity_in__DEFAULT
,
969 skip
, R_SCSI0_CMD_DATA__skip__DEFAULT
,
970 clr_status
, R_SCSI0_CMD_DATA__clr_status__DEFAULT
,
971 asynch_setup
, R_SCSI0_CMD_DATA__asynch_setup__DEFAULT
,
972 command
, R_SCSI0_CMD_DATA__command__DEFAULT
,
973 data_out
, R_SCSI0_CMD_DATA__data_out__DEFAULT
977 #if USE_GROUP__SCSI_registers
978 REG_SET__R_SCSI0_CTRL(
979 id_type
, R_SCSI0_CTRL__id_type__DEFAULT
,
980 sel_timeout
, R_SCSI0_CTRL__sel_timeout__DEFAULT
,
981 synch_per
, R_SCSI0_CTRL__synch_per__DEFAULT
,
982 rst
, R_SCSI0_CTRL__rst__DEFAULT
,
983 atn
, R_SCSI0_CTRL__atn__DEFAULT
,
984 my_id
, R_SCSI0_CTRL__my_id__DEFAULT
,
985 target_id
, R_SCSI0_CTRL__target_id__DEFAULT
,
986 fast_20
, R_SCSI0_CTRL__fast_20__DEFAULT
,
987 bus_width
, R_SCSI0_CTRL__bus_width__DEFAULT
,
988 synch
, R_SCSI0_CTRL__synch__DEFAULT
,
989 enable
, R_SCSI0_CTRL__enable__DEFAULT
993 #if USE_GROUP__SCSI_registers
994 REG_SET__R_SCSI0_DATA(
995 data_out
, R_SCSI0_DATA__data_out__DEFAULT
999 #if USE_GROUP__SCSI_registers
1000 REG_SET__R_SCSI0_STATUS_CTRL(
1001 parity_in
, R_SCSI0_STATUS_CTRL__parity_in__DEFAULT
,
1002 skip
, R_SCSI0_STATUS_CTRL__skip__DEFAULT
,
1003 clr_status
, R_SCSI0_STATUS_CTRL__clr_status__DEFAULT
1007 #if USE_GROUP__SCSI_registers
1008 REG_SET__R_SCSI1_CMD(
1009 asynch_setup
, R_SCSI1_CMD__asynch_setup__DEFAULT
,
1010 command
, R_SCSI1_CMD__command__DEFAULT
1014 #if USE_GROUP__SCSI_registers
1015 REG_SET__R_SCSI1_CMD_DATA(
1016 parity_in
, R_SCSI1_CMD_DATA__parity_in__DEFAULT
,
1017 skip
, R_SCSI1_CMD_DATA__skip__DEFAULT
,
1018 clr_status
, R_SCSI1_CMD_DATA__clr_status__DEFAULT
,
1019 asynch_setup
, R_SCSI1_CMD_DATA__asynch_setup__DEFAULT
,
1020 command
, R_SCSI1_CMD_DATA__command__DEFAULT
,
1021 data_out
, R_SCSI1_CMD_DATA__data_out__DEFAULT
1025 #if USE_GROUP__SCSI_registers
1026 REG_SET__R_SCSI1_CTRL(
1027 id_type
, R_SCSI1_CTRL__id_type__DEFAULT
,
1028 sel_timeout
, R_SCSI1_CTRL__sel_timeout__DEFAULT
,
1029 synch_per
, R_SCSI1_CTRL__synch_per__DEFAULT
,
1030 rst
, R_SCSI1_CTRL__rst__DEFAULT
,
1031 atn
, R_SCSI1_CTRL__atn__DEFAULT
,
1032 my_id
, R_SCSI1_CTRL__my_id__DEFAULT
,
1033 target_id
, R_SCSI1_CTRL__target_id__DEFAULT
,
1034 fast_20
, R_SCSI1_CTRL__fast_20__DEFAULT
,
1035 bus_width
, R_SCSI1_CTRL__bus_width__DEFAULT
,
1036 synch
, R_SCSI1_CTRL__synch__DEFAULT
,
1037 enable
, R_SCSI1_CTRL__enable__DEFAULT
1041 #if USE_GROUP__SCSI_registers
1042 REG_SET__R_SCSI1_DATA(
1043 data_out
, R_SCSI1_DATA__data_out__DEFAULT
1047 #if USE_GROUP__SCSI_registers
1048 REG_SET__R_SCSI1_STATUS_CTRL(
1049 parity_in
, R_SCSI1_STATUS_CTRL__parity_in__DEFAULT
,
1050 skip
, R_SCSI1_STATUS_CTRL__skip__DEFAULT
,
1051 clr_status
, R_SCSI1_STATUS_CTRL__clr_status__DEFAULT
1055 #if USE_GROUP__Bus_interface_configuration_registers
1056 REG_SET__R_SDRAM_CONFIG(
1057 wmm1
, R_SDRAM_CONFIG__wmm1__DEFAULT
,
1058 wmm0
, R_SDRAM_CONFIG__wmm0__DEFAULT
,
1059 sh1
, R_SDRAM_CONFIG__sh1__DEFAULT
,
1060 sh0
, R_SDRAM_CONFIG__sh0__DEFAULT
,
1061 w
, R_SDRAM_CONFIG__w__DEFAULT
,
1062 type1
, R_SDRAM_CONFIG__type1__DEFAULT
,
1063 type0
, R_SDRAM_CONFIG__type0__DEFAULT
,
1064 group_sel
, R_SDRAM_CONFIG__group_sel__DEFAULT
,
1065 ca1
, R_SDRAM_CONFIG__ca1__DEFAULT
,
1066 bank_sel1
, R_SDRAM_CONFIG__bank_sel1__DEFAULT
,
1067 ca0
, R_SDRAM_CONFIG__ca0__DEFAULT
,
1068 bank_sel0
, R_SDRAM_CONFIG__bank_sel0__DEFAULT
1072 #if USE_GROUP__Bus_interface_configuration_registers
1073 REG_SET__R_SDRAM_TIMING(
1074 sdram
, R_SDRAM_TIMING__sdram__DEFAULT
,
1075 mrs_data
, R_SDRAM_TIMING__mrs_data__DEFAULT
,
1076 ref
, R_SDRAM_TIMING__ref__DEFAULT
,
1077 ddr
, R_SDRAM_TIMING__ddr__DEFAULT
,
1078 clk100
, R_SDRAM_TIMING__clk100__DEFAULT
,
1079 ps
, R_SDRAM_TIMING__ps__DEFAULT
,
1080 cmd
, R_SDRAM_TIMING__cmd__DEFAULT
,
1081 pde
, R_SDRAM_TIMING__pde__DEFAULT
,
1082 rc
, R_SDRAM_TIMING__rc__DEFAULT
,
1083 rp
, R_SDRAM_TIMING__rp__DEFAULT
,
1084 rcd
, R_SDRAM_TIMING__rcd__DEFAULT
,
1085 cl
, R_SDRAM_TIMING__cl__DEFAULT
1089 #if USE_GROUP__Serial_port_registers
1090 REG_SET__R_SERIAL0_BAUD(
1091 tr_baud
, R_SERIAL0_BAUD__tr_baud__DEFAULT
,
1092 rec_baud
, R_SERIAL0_BAUD__rec_baud__DEFAULT
1096 #if USE_GROUP__Serial_port_registers
1097 REG_SET__R_SERIAL0_CTRL(
1098 tr_baud
, R_SERIAL0_CTRL__tr_baud__DEFAULT
,
1099 rec_baud
, R_SERIAL0_CTRL__rec_baud__DEFAULT
,
1100 dma_err
, R_SERIAL0_CTRL__dma_err__DEFAULT
,
1101 rec_enable
, R_SERIAL0_CTRL__rec_enable__DEFAULT
,
1102 rts_
, R_SERIAL0_CTRL__rts___DEFAULT
,
1103 sampling
, R_SERIAL0_CTRL__sampling__DEFAULT
,
1104 rec_stick_par
, R_SERIAL0_CTRL__rec_stick_par__DEFAULT
,
1105 rec_par
, R_SERIAL0_CTRL__rec_par__DEFAULT
,
1106 rec_par_en
, R_SERIAL0_CTRL__rec_par_en__DEFAULT
,
1107 rec_bitnr
, R_SERIAL0_CTRL__rec_bitnr__DEFAULT
,
1108 txd
, R_SERIAL0_CTRL__txd__DEFAULT
,
1109 tr_enable
, R_SERIAL0_CTRL__tr_enable__DEFAULT
,
1110 auto_cts
, R_SERIAL0_CTRL__auto_cts__DEFAULT
,
1111 stop_bits
, R_SERIAL0_CTRL__stop_bits__DEFAULT
,
1112 tr_stick_par
, R_SERIAL0_CTRL__tr_stick_par__DEFAULT
,
1113 tr_par
, R_SERIAL0_CTRL__tr_par__DEFAULT
,
1114 tr_par_en
, R_SERIAL0_CTRL__tr_par_en__DEFAULT
,
1115 tr_bitnr
, R_SERIAL0_CTRL__tr_bitnr__DEFAULT
,
1116 data_out
, R_SERIAL0_CTRL__data_out__DEFAULT
1120 #if USE_GROUP__Serial_port_registers
1121 REG_SET__R_SERIAL0_REC_CTRL(
1122 dma_err
, R_SERIAL0_REC_CTRL__dma_err__DEFAULT
,
1123 rec_enable
, R_SERIAL0_REC_CTRL__rec_enable__DEFAULT
,
1124 rts_
, R_SERIAL0_REC_CTRL__rts___DEFAULT
,
1125 sampling
, R_SERIAL0_REC_CTRL__sampling__DEFAULT
,
1126 rec_stick_par
, R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT
,
1127 rec_par
, R_SERIAL0_REC_CTRL__rec_par__DEFAULT
,
1128 rec_par_en
, R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT
,
1129 rec_bitnr
, R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT
1133 #if USE_GROUP__Serial_port_registers
1134 REG_SET__R_SERIAL0_TR_CTRL(
1135 txd
, R_SERIAL0_TR_CTRL__txd__DEFAULT
,
1136 tr_enable
, R_SERIAL0_TR_CTRL__tr_enable__DEFAULT
,
1137 auto_cts
, R_SERIAL0_TR_CTRL__auto_cts__DEFAULT
,
1138 stop_bits
, R_SERIAL0_TR_CTRL__stop_bits__DEFAULT
,
1139 tr_stick_par
, R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT
,
1140 tr_par
, R_SERIAL0_TR_CTRL__tr_par__DEFAULT
,
1141 tr_par_en
, R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT
,
1142 tr_bitnr
, R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT
1146 #if USE_GROUP__Serial_port_registers
1147 REG_SET__R_SERIAL0_TR_DATA(
1148 data_out
, R_SERIAL0_TR_DATA__data_out__DEFAULT
1152 #if USE_GROUP__Serial_port_registers
1153 REG_SET__R_SERIAL0_XOFF(
1154 tx_stop
, R_SERIAL0_XOFF__tx_stop__DEFAULT
,
1155 auto_xoff
, R_SERIAL0_XOFF__auto_xoff__DEFAULT
,
1156 xoff_char
, R_SERIAL0_XOFF__xoff_char__DEFAULT
1160 #if USE_GROUP__Serial_port_registers
1161 REG_SET__R_SERIAL1_BAUD(
1162 tr_baud
, R_SERIAL1_BAUD__tr_baud__DEFAULT
,
1163 rec_baud
, R_SERIAL1_BAUD__rec_baud__DEFAULT
1167 #if USE_GROUP__Serial_port_registers
1168 REG_SET__R_SERIAL1_CTRL(
1169 tr_baud
, R_SERIAL1_CTRL__tr_baud__DEFAULT
,
1170 rec_baud
, R_SERIAL1_CTRL__rec_baud__DEFAULT
,
1171 dma_err
, R_SERIAL1_CTRL__dma_err__DEFAULT
,
1172 rec_enable
, R_SERIAL1_CTRL__rec_enable__DEFAULT
,
1173 rts_
, R_SERIAL1_CTRL__rts___DEFAULT
,
1174 sampling
, R_SERIAL1_CTRL__sampling__DEFAULT
,
1175 rec_stick_par
, R_SERIAL1_CTRL__rec_stick_par__DEFAULT
,
1176 rec_par
, R_SERIAL1_CTRL__rec_par__DEFAULT
,
1177 rec_par_en
, R_SERIAL1_CTRL__rec_par_en__DEFAULT
,
1178 rec_bitnr
, R_SERIAL1_CTRL__rec_bitnr__DEFAULT
,
1179 txd
, R_SERIAL1_CTRL__txd__DEFAULT
,
1180 tr_enable
, R_SERIAL1_CTRL__tr_enable__DEFAULT
,
1181 auto_cts
, R_SERIAL1_CTRL__auto_cts__DEFAULT
,
1182 stop_bits
, R_SERIAL1_CTRL__stop_bits__DEFAULT
,
1183 tr_stick_par
, R_SERIAL1_CTRL__tr_stick_par__DEFAULT
,
1184 tr_par
, R_SERIAL1_CTRL__tr_par__DEFAULT
,
1185 tr_par_en
, R_SERIAL1_CTRL__tr_par_en__DEFAULT
,
1186 tr_bitnr
, R_SERIAL1_CTRL__tr_bitnr__DEFAULT
,
1187 data_out
, R_SERIAL1_CTRL__data_out__DEFAULT
1191 #if USE_GROUP__Serial_port_registers
1192 REG_SET__R_SERIAL1_REC_CTRL(
1193 dma_err
, R_SERIAL1_REC_CTRL__dma_err__DEFAULT
,
1194 rec_enable
, R_SERIAL1_REC_CTRL__rec_enable__DEFAULT
,
1195 rts_
, R_SERIAL1_REC_CTRL__rts___DEFAULT
,
1196 sampling
, R_SERIAL1_REC_CTRL__sampling__DEFAULT
,
1197 rec_stick_par
, R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT
,
1198 rec_par
, R_SERIAL1_REC_CTRL__rec_par__DEFAULT
,
1199 rec_par_en
, R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT
,
1200 rec_bitnr
, R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT
1204 #if USE_GROUP__Serial_port_registers
1205 REG_SET__R_SERIAL1_TR_CTRL(
1206 txd
, R_SERIAL1_TR_CTRL__txd__DEFAULT
,
1207 tr_enable
, R_SERIAL1_TR_CTRL__tr_enable__DEFAULT
,
1208 auto_cts
, R_SERIAL1_TR_CTRL__auto_cts__DEFAULT
,
1209 stop_bits
, R_SERIAL1_TR_CTRL__stop_bits__DEFAULT
,
1210 tr_stick_par
, R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT
,
1211 tr_par
, R_SERIAL1_TR_CTRL__tr_par__DEFAULT
,
1212 tr_par_en
, R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT
,
1213 tr_bitnr
, R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT
1217 #if USE_GROUP__Serial_port_registers
1218 REG_SET__R_SERIAL1_TR_DATA(
1219 data_out
, R_SERIAL1_TR_DATA__data_out__DEFAULT
1223 #if USE_GROUP__Serial_port_registers
1224 REG_SET__R_SERIAL1_XOFF(
1225 tx_stop
, R_SERIAL1_XOFF__tx_stop__DEFAULT
,
1226 auto_xoff
, R_SERIAL1_XOFF__auto_xoff__DEFAULT
,
1227 xoff_char
, R_SERIAL1_XOFF__xoff_char__DEFAULT
1231 #if USE_GROUP__Serial_port_registers
1232 REG_SET__R_SERIAL2_BAUD(
1233 tr_baud
, R_SERIAL2_BAUD__tr_baud__DEFAULT
,
1234 rec_baud
, R_SERIAL2_BAUD__rec_baud__DEFAULT
1238 #if USE_GROUP__Serial_port_registers
1239 REG_SET__R_SERIAL2_CTRL(
1240 tr_baud
, R_SERIAL2_CTRL__tr_baud__DEFAULT
,
1241 rec_baud
, R_SERIAL2_CTRL__rec_baud__DEFAULT
,
1242 dma_err
, R_SERIAL2_CTRL__dma_err__DEFAULT
,
1243 rec_enable
, R_SERIAL2_CTRL__rec_enable__DEFAULT
,
1244 rts_
, R_SERIAL2_CTRL__rts___DEFAULT
,
1245 sampling
, R_SERIAL2_CTRL__sampling__DEFAULT
,
1246 rec_stick_par
, R_SERIAL2_CTRL__rec_stick_par__DEFAULT
,
1247 rec_par
, R_SERIAL2_CTRL__rec_par__DEFAULT
,
1248 rec_par_en
, R_SERIAL2_CTRL__rec_par_en__DEFAULT
,
1249 rec_bitnr
, R_SERIAL2_CTRL__rec_bitnr__DEFAULT
,
1250 txd
, R_SERIAL2_CTRL__txd__DEFAULT
,
1251 tr_enable
, R_SERIAL2_CTRL__tr_enable__DEFAULT
,
1252 auto_cts
, R_SERIAL2_CTRL__auto_cts__DEFAULT
,
1253 stop_bits
, R_SERIAL2_CTRL__stop_bits__DEFAULT
,
1254 tr_stick_par
, R_SERIAL2_CTRL__tr_stick_par__DEFAULT
,
1255 tr_par
, R_SERIAL2_CTRL__tr_par__DEFAULT
,
1256 tr_par_en
, R_SERIAL2_CTRL__tr_par_en__DEFAULT
,
1257 tr_bitnr
, R_SERIAL2_CTRL__tr_bitnr__DEFAULT
,
1258 data_out
, R_SERIAL2_CTRL__data_out__DEFAULT
1262 #if USE_GROUP__Serial_port_registers
1263 REG_SET__R_SERIAL2_REC_CTRL(
1264 dma_err
, R_SERIAL2_REC_CTRL__dma_err__DEFAULT
,
1265 rec_enable
, R_SERIAL2_REC_CTRL__rec_enable__DEFAULT
,
1266 rts_
, R_SERIAL2_REC_CTRL__rts___DEFAULT
,
1267 sampling
, R_SERIAL2_REC_CTRL__sampling__DEFAULT
,
1268 rec_stick_par
, R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT
,
1269 rec_par
, R_SERIAL2_REC_CTRL__rec_par__DEFAULT
,
1270 rec_par_en
, R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT
,
1271 rec_bitnr
, R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT
1275 #if USE_GROUP__Serial_port_registers
1276 REG_SET__R_SERIAL2_TR_CTRL(
1277 txd
, R_SERIAL2_TR_CTRL__txd__DEFAULT
,
1278 tr_enable
, R_SERIAL2_TR_CTRL__tr_enable__DEFAULT
,
1279 auto_cts
, R_SERIAL2_TR_CTRL__auto_cts__DEFAULT
,
1280 stop_bits
, R_SERIAL2_TR_CTRL__stop_bits__DEFAULT
,
1281 tr_stick_par
, R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT
,
1282 tr_par
, R_SERIAL2_TR_CTRL__tr_par__DEFAULT
,
1283 tr_par_en
, R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT
,
1284 tr_bitnr
, R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT
1288 #if USE_GROUP__Serial_port_registers
1289 REG_SET__R_SERIAL2_TR_DATA(
1290 data_out
, R_SERIAL2_TR_DATA__data_out__DEFAULT
1294 #if USE_GROUP__Serial_port_registers
1295 REG_SET__R_SERIAL2_XOFF(
1296 tx_stop
, R_SERIAL2_XOFF__tx_stop__DEFAULT
,
1297 auto_xoff
, R_SERIAL2_XOFF__auto_xoff__DEFAULT
,
1298 xoff_char
, R_SERIAL2_XOFF__xoff_char__DEFAULT
1302 #if USE_GROUP__Serial_port_registers
1303 REG_SET__R_SERIAL3_BAUD(
1304 tr_baud
, R_SERIAL3_BAUD__tr_baud__DEFAULT
,
1305 rec_baud
, R_SERIAL3_BAUD__rec_baud__DEFAULT
1309 #if USE_GROUP__Serial_port_registers
1310 REG_SET__R_SERIAL3_CTRL(
1311 tr_baud
, R_SERIAL3_CTRL__tr_baud__DEFAULT
,
1312 rec_baud
, R_SERIAL3_CTRL__rec_baud__DEFAULT
,
1313 dma_err
, R_SERIAL3_CTRL__dma_err__DEFAULT
,
1314 rec_enable
, R_SERIAL3_CTRL__rec_enable__DEFAULT
,
1315 rts_
, R_SERIAL3_CTRL__rts___DEFAULT
,
1316 sampling
, R_SERIAL3_CTRL__sampling__DEFAULT
,
1317 rec_stick_par
, R_SERIAL3_CTRL__rec_stick_par__DEFAULT
,
1318 rec_par
, R_SERIAL3_CTRL__rec_par__DEFAULT
,
1319 rec_par_en
, R_SERIAL3_CTRL__rec_par_en__DEFAULT
,
1320 rec_bitnr
, R_SERIAL3_CTRL__rec_bitnr__DEFAULT
,
1321 txd
, R_SERIAL3_CTRL__txd__DEFAULT
,
1322 tr_enable
, R_SERIAL3_CTRL__tr_enable__DEFAULT
,
1323 auto_cts
, R_SERIAL3_CTRL__auto_cts__DEFAULT
,
1324 stop_bits
, R_SERIAL3_CTRL__stop_bits__DEFAULT
,
1325 tr_stick_par
, R_SERIAL3_CTRL__tr_stick_par__DEFAULT
,
1326 tr_par
, R_SERIAL3_CTRL__tr_par__DEFAULT
,
1327 tr_par_en
, R_SERIAL3_CTRL__tr_par_en__DEFAULT
,
1328 tr_bitnr
, R_SERIAL3_CTRL__tr_bitnr__DEFAULT
,
1329 data_out
, R_SERIAL3_CTRL__data_out__DEFAULT
1333 #if USE_GROUP__Serial_port_registers
1334 REG_SET__R_SERIAL3_REC_CTRL(
1335 dma_err
, R_SERIAL3_REC_CTRL__dma_err__DEFAULT
,
1336 rec_enable
, R_SERIAL3_REC_CTRL__rec_enable__DEFAULT
,
1337 rts_
, R_SERIAL3_REC_CTRL__rts___DEFAULT
,
1338 sampling
, R_SERIAL3_REC_CTRL__sampling__DEFAULT
,
1339 rec_stick_par
, R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT
,
1340 rec_par
, R_SERIAL3_REC_CTRL__rec_par__DEFAULT
,
1341 rec_par_en
, R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT
,
1342 rec_bitnr
, R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT
1346 #if USE_GROUP__Serial_port_registers
1347 REG_SET__R_SERIAL3_TR_CTRL(
1348 txd
, R_SERIAL3_TR_CTRL__txd__DEFAULT
,
1349 tr_enable
, R_SERIAL3_TR_CTRL__tr_enable__DEFAULT
,
1350 auto_cts
, R_SERIAL3_TR_CTRL__auto_cts__DEFAULT
,
1351 stop_bits
, R_SERIAL3_TR_CTRL__stop_bits__DEFAULT
,
1352 tr_stick_par
, R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT
,
1353 tr_par
, R_SERIAL3_TR_CTRL__tr_par__DEFAULT
,
1354 tr_par_en
, R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT
,
1355 tr_bitnr
, R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT
1359 #if USE_GROUP__Serial_port_registers
1360 REG_SET__R_SERIAL3_TR_DATA(
1361 data_out
, R_SERIAL3_TR_DATA__data_out__DEFAULT
1365 #if USE_GROUP__Serial_port_registers
1366 REG_SET__R_SERIAL3_XOFF(
1367 tx_stop
, R_SERIAL3_XOFF__tx_stop__DEFAULT
,
1368 auto_xoff
, R_SERIAL3_XOFF__auto_xoff__DEFAULT
,
1369 xoff_char
, R_SERIAL3_XOFF__xoff_char__DEFAULT
1373 #if USE_GROUP__Timer_registers
1374 REG_SET__R_SERIAL_PRESCALE(
1375 ser_presc
, R_SERIAL_PRESCALE__ser_presc__DEFAULT
1379 #if USE_GROUP__DMA_registers
1381 ch9_eop
, R_SET_EOP__ch9_eop__DEFAULT
,
1382 ch7_eop
, R_SET_EOP__ch7_eop__DEFAULT
,
1383 ch5_eop
, R_SET_EOP__ch5_eop__DEFAULT
,
1384 ch3_eop
, R_SET_EOP__ch3_eop__DEFAULT
1388 #if USE_GROUP__Shared_RAM_interface_registers
1389 REG_SET__R_SHARED_RAM_ADDR(
1390 base_addr
, R_SHARED_RAM_ADDR__base_addr__DEFAULT
1394 #if USE_GROUP__Shared_RAM_interface_registers
1395 REG_SET__R_SHARED_RAM_CONFIG(
1396 width
, R_SHARED_RAM_CONFIG__width__DEFAULT
,
1397 enable
, R_SHARED_RAM_CONFIG__enable__DEFAULT
,
1398 pint
, R_SHARED_RAM_CONFIG__pint__DEFAULT
,
1399 clri
, R_SHARED_RAM_CONFIG__clri__DEFAULT
1403 #if USE_GROUP__Test_mode_registers
1404 REG_SET__R_SINGLE_STEP(
1405 single_step
, R_SINGLE_STEP__single_step__DEFAULT
,
1406 step_wr
, R_SINGLE_STEP__step_wr__DEFAULT
,
1407 step_rd
, R_SINGLE_STEP__step_rd__DEFAULT
,
1408 step_fetch
, R_SINGLE_STEP__step_fetch__DEFAULT
1412 #if USE_GROUP__Syncrounous_serial_port_registers
1413 REG_SET__R_SYNC_SERIAL1_CTRL(
1414 tr_baud
, R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT
,
1415 dma_enable
, R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT
,
1416 mode
, R_SYNC_SERIAL1_CTRL__mode__DEFAULT
,
1417 error
, R_SYNC_SERIAL1_CTRL__error__DEFAULT
,
1418 rec_enable
, R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT
,
1419 f_synctype
, R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT
,
1420 f_syncsize
, R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT
,
1421 f_sync
, R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT
,
1422 clk_mode
, R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT
,
1423 clk_halt
, R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT
,
1424 bitorder
, R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT
,
1425 tr_enable
, R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT
,
1426 wordsize
, R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT
,
1427 buf_empty
, R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT
,
1428 buf_full
, R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT
,
1429 flow_ctrl
, R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT
,
1430 clk_polarity
, R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT
,
1431 frame_polarity
, R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT
,
1432 status_polarity
, R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT
,
1433 clk_driver
, R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT
,
1434 frame_driver
, R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT
,
1435 status_driver
, R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT
,
1436 def_out0
, R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT
1440 #if USE_GROUP__Syncrounous_serial_port_registers
1441 REG_SET__R_SYNC_SERIAL1_TR_BYTE(
1442 data_out
, R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT
1446 #if USE_GROUP__Syncrounous_serial_port_registers
1447 REG_SET__R_SYNC_SERIAL1_TR_DATA(
1448 data_out
, R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT
1452 #if USE_GROUP__Syncrounous_serial_port_registers
1453 REG_SET__R_SYNC_SERIAL1_TR_WORD(
1454 data_out
, R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT
1458 #if USE_GROUP__Syncrounous_serial_port_registers
1459 REG_SET__R_SYNC_SERIAL3_CTRL(
1460 tr_baud
, R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT
,
1461 dma_enable
, R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT
,
1462 mode
, R_SYNC_SERIAL3_CTRL__mode__DEFAULT
,
1463 error
, R_SYNC_SERIAL3_CTRL__error__DEFAULT
,
1464 rec_enable
, R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT
,
1465 f_synctype
, R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT
,
1466 f_syncsize
, R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT
,
1467 f_sync
, R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT
,
1468 clk_mode
, R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT
,
1469 clk_halt
, R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT
,
1470 bitorder
, R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT
,
1471 tr_enable
, R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT
,
1472 wordsize
, R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT
,
1473 buf_empty
, R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT
,
1474 buf_full
, R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT
,
1475 flow_ctrl
, R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT
,
1476 clk_polarity
, R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT
,
1477 frame_polarity
, R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT
,
1478 status_polarity
, R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT
,
1479 clk_driver
, R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT
,
1480 frame_driver
, R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT
,
1481 status_driver
, R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT
,
1482 def_out0
, R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT
1486 #if USE_GROUP__Syncrounous_serial_port_registers
1487 REG_SET__R_SYNC_SERIAL3_TR_BYTE(
1488 data_out
, R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT
1492 #if USE_GROUP__Syncrounous_serial_port_registers
1493 REG_SET__R_SYNC_SERIAL3_TR_DATA(
1494 data_out
, R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT
1498 #if USE_GROUP__Syncrounous_serial_port_registers
1499 REG_SET__R_SYNC_SERIAL3_TR_WORD(
1500 data_out
, R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT
1504 #if USE_GROUP__Timer_registers
1505 REG_SET__R_SYNC_SERIAL_PRESCALE(
1506 clk_sel_u3
, R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT
,
1507 word_stb_sel_u3
, R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT
,
1508 clk_sel_u1
, R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT
,
1509 word_stb_sel_u1
, R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT
,
1510 prescaler
, R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT
,
1511 warp_mode
, R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT
,
1512 frame_rate
, R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT
,
1513 word_rate
, R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT
1517 #if USE_GROUP__Test_mode_registers
1518 REG_SET__R_TEST_MODE(
1519 single_step
, R_TEST_MODE__single_step__DEFAULT
,
1520 step_wr
, R_TEST_MODE__step_wr__DEFAULT
,
1521 step_rd
, R_TEST_MODE__step_rd__DEFAULT
,
1522 step_fetch
, R_TEST_MODE__step_fetch__DEFAULT
,
1523 mmu_test
, R_TEST_MODE__mmu_test__DEFAULT
,
1524 usb_test
, R_TEST_MODE__usb_test__DEFAULT
,
1525 scsi_timer_test
, R_TEST_MODE__scsi_timer_test__DEFAULT
,
1526 backoff
, R_TEST_MODE__backoff__DEFAULT
,
1527 snmp_test
, R_TEST_MODE__snmp_test__DEFAULT
,
1528 snmp_inc
, R_TEST_MODE__snmp_inc__DEFAULT
,
1529 ser_loop
, R_TEST_MODE__ser_loop__DEFAULT
,
1530 baudrate
, R_TEST_MODE__baudrate__DEFAULT
,
1531 timer
, R_TEST_MODE__timer__DEFAULT
,
1532 cache_test
, R_TEST_MODE__cache_test__DEFAULT
,
1533 tag_test
, R_TEST_MODE__tag_test__DEFAULT
,
1534 cache_enable
, R_TEST_MODE__cache_enable__DEFAULT
1538 #if USE_GROUP__Timer_registers
1539 REG_SET__R_TIMER_CTRL(
1540 timerdiv1
, R_TIMER_CTRL__timerdiv1__DEFAULT
,
1541 timerdiv0
, R_TIMER_CTRL__timerdiv0__DEFAULT
,
1542 presc_timer1
, R_TIMER_CTRL__presc_timer1__DEFAULT
,
1543 i1
, R_TIMER_CTRL__i1__DEFAULT
,
1544 tm1
, R_TIMER_CTRL__tm1__DEFAULT
,
1545 clksel1
, R_TIMER_CTRL__clksel1__DEFAULT
,
1546 presc_ext
, R_TIMER_CTRL__presc_ext__DEFAULT
,
1547 i0
, R_TIMER_CTRL__i0__DEFAULT
,
1548 tm0
, R_TIMER_CTRL__tm0__DEFAULT
,
1549 clksel0
, R_TIMER_CTRL__clksel0__DEFAULT
1553 #if USE_GROUP__Timer_registers
1554 REG_SET__R_TIMER_PRESCALE(
1555 tim_presc
, R_TIMER_PRESCALE__tim_presc__DEFAULT
1559 #if USE_GROUP__USB_interface_control_registers
1560 REG_SET__R_USB_IRQ_MASK_CLR(
1561 iso_eof
, R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT
,
1562 intr_eof
, R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT
,
1563 iso_eot
, R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT
,
1564 intr_eot
, R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT
,
1565 ctl_eot
, R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT
,
1566 bulk_eot
, R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT
,
1567 epid_attn
, R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT
,
1568 sof
, R_USB_IRQ_MASK_CLR__sof__DEFAULT
,
1569 port_status
, R_USB_IRQ_MASK_CLR__port_status__DEFAULT
,
1570 ctl_status
, R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT
1574 #if USE_GROUP__USB_interface_control_registers
1575 REG_SET__R_USB_IRQ_MASK_CLR_DEV(
1576 out_eot
, R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT
,
1577 ep3_in_eot
, R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT
,
1578 ep2_in_eot
, R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT
,
1579 ep1_in_eot
, R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT
,
1580 ep0_in_eot
, R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT
,
1581 epid_attn
, R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT
,
1582 sof
, R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT
,
1583 port_status
, R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT
,
1584 ctl_status
, R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT
1588 #if USE_GROUP__USB_interface_control_registers
1589 REG_SET__R_USB_IRQ_MASK_SET(
1590 iso_eof
, R_USB_IRQ_MASK_SET__iso_eof__DEFAULT
,
1591 intr_eof
, R_USB_IRQ_MASK_SET__intr_eof__DEFAULT
,
1592 iso_eot
, R_USB_IRQ_MASK_SET__iso_eot__DEFAULT
,
1593 intr_eot
, R_USB_IRQ_MASK_SET__intr_eot__DEFAULT
,
1594 ctl_eot
, R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT
,
1595 bulk_eot
, R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT
,
1596 epid_attn
, R_USB_IRQ_MASK_SET__epid_attn__DEFAULT
,
1597 sof
, R_USB_IRQ_MASK_SET__sof__DEFAULT
,
1598 port_status
, R_USB_IRQ_MASK_SET__port_status__DEFAULT
,
1599 ctl_status
, R_USB_IRQ_MASK_SET__ctl_status__DEFAULT
1603 #if USE_GROUP__USB_interface_control_registers
1604 REG_SET__R_USB_IRQ_MASK_SET_DEV(
1605 out_eot
, R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT
,
1606 ep3_in_eot
, R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT
,
1607 ep2_in_eot
, R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT
,
1608 ep1_in_eot
, R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT
,
1609 ep0_in_eot
, R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT
,
1610 epid_attn
, R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT
,
1611 sof
, R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT
,
1612 port_status
, R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT
,
1613 ctl_status
, R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT
1617 #if USE_GROUP__USB_interface_control_registers
1618 REG_SET__R_USB_PORT1_DISABLE(
1619 disable
, R_USB_PORT1_DISABLE__disable__DEFAULT
1623 #if USE_GROUP__USB_interface_control_registers
1624 REG_SET__R_USB_PORT2_DISABLE(
1625 disable
, R_USB_PORT2_DISABLE__disable__DEFAULT
1629 #if USE_GROUP__Interrupt_mask_and_status_registers
1630 REG_SET__R_VECT_MASK_CLR(
1631 usb
, R_VECT_MASK_CLR__usb__DEFAULT
,
1632 dma9
, R_VECT_MASK_CLR__dma9__DEFAULT
,
1633 dma8
, R_VECT_MASK_CLR__dma8__DEFAULT
,
1634 dma7
, R_VECT_MASK_CLR__dma7__DEFAULT
,
1635 dma6
, R_VECT_MASK_CLR__dma6__DEFAULT
,
1636 dma5
, R_VECT_MASK_CLR__dma5__DEFAULT
,
1637 dma4
, R_VECT_MASK_CLR__dma4__DEFAULT
,
1638 dma3
, R_VECT_MASK_CLR__dma3__DEFAULT
,
1639 dma2
, R_VECT_MASK_CLR__dma2__DEFAULT
,
1640 dma1
, R_VECT_MASK_CLR__dma1__DEFAULT
,
1641 dma0
, R_VECT_MASK_CLR__dma0__DEFAULT
,
1642 ext_dma1
, R_VECT_MASK_CLR__ext_dma1__DEFAULT
,
1643 ext_dma0
, R_VECT_MASK_CLR__ext_dma0__DEFAULT
,
1644 pa
, R_VECT_MASK_CLR__pa__DEFAULT
,
1645 irq_intnr
, R_VECT_MASK_CLR__irq_intnr__DEFAULT
,
1646 sw
, R_VECT_MASK_CLR__sw__DEFAULT
,
1647 serial
, R_VECT_MASK_CLR__serial__DEFAULT
,
1648 snmp
, R_VECT_MASK_CLR__snmp__DEFAULT
,
1649 network
, R_VECT_MASK_CLR__network__DEFAULT
,
1650 scsi1
, R_VECT_MASK_CLR__scsi1__DEFAULT
,
1651 scsi0
, R_VECT_MASK_CLR__scsi0__DEFAULT
,
1652 timer1
, R_VECT_MASK_CLR__timer1__DEFAULT
,
1653 timer0
, R_VECT_MASK_CLR__timer0__DEFAULT
,
1654 nmi
, R_VECT_MASK_CLR__nmi__DEFAULT
,
1655 some
, R_VECT_MASK_CLR__some__DEFAULT
1659 #if USE_GROUP__Interrupt_mask_and_status_registers
1660 REG_SET__R_VECT_MASK_SET(
1661 usb
, R_VECT_MASK_SET__usb__DEFAULT
,
1662 dma9
, R_VECT_MASK_SET__dma9__DEFAULT
,
1663 dma8
, R_VECT_MASK_SET__dma8__DEFAULT
,
1664 dma7
, R_VECT_MASK_SET__dma7__DEFAULT
,
1665 dma6
, R_VECT_MASK_SET__dma6__DEFAULT
,
1666 dma5
, R_VECT_MASK_SET__dma5__DEFAULT
,
1667 dma4
, R_VECT_MASK_SET__dma4__DEFAULT
,
1668 dma3
, R_VECT_MASK_SET__dma3__DEFAULT
,
1669 dma2
, R_VECT_MASK_SET__dma2__DEFAULT
,
1670 dma1
, R_VECT_MASK_SET__dma1__DEFAULT
,
1671 dma0
, R_VECT_MASK_SET__dma0__DEFAULT
,
1672 ext_dma1
, R_VECT_MASK_SET__ext_dma1__DEFAULT
,
1673 ext_dma0
, R_VECT_MASK_SET__ext_dma0__DEFAULT
,
1674 pa
, R_VECT_MASK_SET__pa__DEFAULT
,
1675 irq_intnr
, R_VECT_MASK_SET__irq_intnr__DEFAULT
,
1676 sw
, R_VECT_MASK_SET__sw__DEFAULT
,
1677 serial
, R_VECT_MASK_SET__serial__DEFAULT
,
1678 snmp
, R_VECT_MASK_SET__snmp__DEFAULT
,
1679 network
, R_VECT_MASK_SET__network__DEFAULT
,
1680 scsi1
, R_VECT_MASK_SET__scsi1__DEFAULT
,
1681 scsi0
, R_VECT_MASK_SET__scsi0__DEFAULT
,
1682 timer1
, R_VECT_MASK_SET__timer1__DEFAULT
,
1683 timer0
, R_VECT_MASK_SET__timer0__DEFAULT
,
1684 nmi
, R_VECT_MASK_SET__nmi__DEFAULT
,
1685 some
, R_VECT_MASK_SET__some__DEFAULT
1689 #if USE_GROUP__Bus_interface_configuration_registers
1690 REG_SET__R_WAITSTATES(
1691 pcs4_7_zw
, R_WAITSTATES__pcs4_7_zw__DEFAULT
,
1692 pcs4_7_ew
, R_WAITSTATES__pcs4_7_ew__DEFAULT
,
1693 pcs4_7_lw
, R_WAITSTATES__pcs4_7_lw__DEFAULT
,
1694 pcs0_3_zw
, R_WAITSTATES__pcs0_3_zw__DEFAULT
,
1695 pcs0_3_ew
, R_WAITSTATES__pcs0_3_ew__DEFAULT
,
1696 pcs0_3_lw
, R_WAITSTATES__pcs0_3_lw__DEFAULT
,
1697 sram_zw
, R_WAITSTATES__sram_zw__DEFAULT
,
1698 sram_ew
, R_WAITSTATES__sram_ew__DEFAULT
,
1699 sram_lw
, R_WAITSTATES__sram_lw__DEFAULT
,
1700 flash_zw
, R_WAITSTATES__flash_zw__DEFAULT
,
1701 flash_ew
, R_WAITSTATES__flash_ew__DEFAULT
,
1702 flash_lw
, R_WAITSTATES__flash_lw__DEFAULT
1706 #if USE_GROUP__Timer_registers
1707 REG_SET__R_WATCHDOG(
1708 key
, R_WATCHDOG__key__DEFAULT
,
1709 enable
, R_WATCHDOG__enable__DEFAULT
1713 } /* init_shadow__hwregs */