target/linux/generic/backport-4.14/403-v4.15-0002-mtd-spi-nor-add-support-for-GD25Q256.patch

   1 From 65153846b18c486ce3c90477c467d53915114e3f Mon Sep 17 00:00:00 2001
   2 From: Andy Yan <andy.yan@rock-chips.com>
   3 Date: Mon, 28 Aug 2017 10:00:46 +0800
   4 Subject: [PATCH 2/2] mtd: spi-nor: add support for GD25Q256
   5
   6 Add support for GD25Q256, a 32MiB SPI Nor flash
   7 from GigaDevice.
   8
   9 Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
  10 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
  11
  12 --- a/drivers/mtd/spi-nor/spi-nor.c
  13 +++ b/drivers/mtd/spi-nor/spi-nor.c
  14 @@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_
  15         return ret;
  16  }
  17
  18 +static int macronix_quad_enable(struct spi_nor *nor);
  19 +
  20  /* Used when the "_ext_id" is two bytes at most */
  21  #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)     \
  22                 .id = {                                                 \
  23 @@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_i
  24                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  25                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  26         },
  27 +       {
  28 +               "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
  29 +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  30 +                       SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  31 +                       .quad_enable = macronix_quad_enable,
  32 +       },
  33
  34         /* Intel/Numonyx -- xxxs33b */
  35         { "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },