1 From e7439e7fd384f55f55837f7e4866e74d8dca3827 Mon Sep 17 00:00:00 2001
2 From: Hayes Wang <hayeswang@realtek.com>
3 Date: Fri, 16 Apr 2021 16:04:35 +0800
4 Subject: [PATCH] r8152: support new chips
6 commit 195aae321c829dd1945900d75561e6aa79cce208 upstream.
8 Support RTL8153C, RTL8153D, RTL8156A, and RTL8156B. The RTL8156A
9 and RTL8156B are the 2.5G ethernet.
11 Signed-off-by: Hayes Wang <hayeswang@realtek.com>
12 Signed-off-by: David S. Miller <davem@davemloft.net>
14 drivers/net/usb/r8152.c | 2634 +++++++++++++++++++++++++++++++++++----
15 1 file changed, 2359 insertions(+), 275 deletions(-)
17 --- a/drivers/net/usb/r8152.c
18 +++ b/drivers/net/usb/r8152.c
21 #define PLA_IDR 0xc000
22 #define PLA_RCR 0xc010
23 +#define PLA_RCR1 0xc012
24 #define PLA_RMS 0xc016
25 #define PLA_RXFIFO_CTRL0 0xc0a0
26 +#define PLA_RXFIFO_FULL 0xc0a2
27 #define PLA_RXFIFO_CTRL1 0xc0a4
28 +#define PLA_RX_FIFO_FULL 0xc0a6
29 #define PLA_RXFIFO_CTRL2 0xc0a8
30 +#define PLA_RX_FIFO_EMPTY 0xc0aa
31 #define PLA_DMY_REG0 0xc0b0
32 #define PLA_FMC 0xc0b4
33 #define PLA_CFG_WOL 0xc0b6
35 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
36 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
37 #define PLA_EXTRA_STATUS 0xd398
38 +#define PLA_GPHY_CTRL 0xd3ae
39 +#define PLA_POL_GPIO_CTRL 0xdc6a
40 #define PLA_EFUSE_DATA 0xdd00
41 #define PLA_EFUSE_CMD 0xdd02
42 #define PLA_LEDSEL 0xdd90
44 #define PLA_LWAKE_CTRL_REG 0xe007
45 #define PLA_GPHY_INTR_IMR 0xe022
46 #define PLA_EEE_CR 0xe040
47 +#define PLA_EEE_TXTWSYS 0xe04c
48 +#define PLA_EEE_TXTWSYS_2P5G 0xe058
49 #define PLA_EEEP_CR 0xe080
50 #define PLA_MAC_PWR_CTRL 0xe0c0
51 #define PLA_MAC_PWR_CTRL2 0xe0ca
53 #define PLA_TCR1 0xe612
54 #define PLA_MTPS 0xe615
55 #define PLA_TXFIFO_CTRL 0xe618
56 +#define PLA_TXFIFO_FULL 0xe61a
57 #define PLA_RSTTALLY 0xe800
59 #define PLA_CRWECR 0xe81c
61 #define PLA_SFF_STS_7 0xe8de
62 #define PLA_PHYSTATUS 0xe908
63 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
64 +#define PLA_USB_CFG 0xe952
65 #define PLA_BP_BA 0xfc26
66 #define PLA_BP_0 0xfc28
67 #define PLA_BP_1 0xfc2a
69 #define USB_USB2PHY 0xb41e
70 #define USB_SSPHYLINK1 0xb426
71 #define USB_SSPHYLINK2 0xb428
72 +#define USB_L1_CTRL 0xb45e
73 #define USB_U2P3_CTRL 0xb460
74 #define USB_CSR_DUMMY1 0xb464
75 #define USB_CSR_DUMMY2 0xb466
77 #define USB_FW_FIX_EN0 0xcfca
78 #define USB_FW_FIX_EN1 0xcfcc
79 #define USB_LPM_CONFIG 0xcfd8
80 +#define USB_ECM_OPTION 0xcfee
81 #define USB_CSTMR 0xcfef /* RTL8153A */
82 +#define USB_MISC_2 0xcfff
83 +#define USB_ECM_OP 0xd26b
84 +#define USB_GPHY_CTRL 0xd284
85 +#define USB_SPEED_OPTION 0xd32a
86 #define USB_FW_CTRL 0xd334 /* RTL8153B */
87 #define USB_FC_TIMER 0xd340
88 #define USB_USB_CTRL 0xd406
90 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
91 #define USB_TX_DMA 0xd434
92 #define USB_UPT_RXDMA_OWN 0xd437
93 +#define USB_UPHY3_MDCMDIO 0xd480
94 #define USB_TOLERANCE 0xd490
95 #define USB_LPM_CTRL 0xd41a
96 #define USB_BMU_RESET 0xd4b0
97 +#define USB_BMU_CONFIG 0xd4b4
98 #define USB_U1U2_TIMER 0xd4da
99 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
100 +#define USB_RX_AGGR_NUM 0xd4ee
101 #define USB_UPS_CTRL 0xd800
102 #define USB_POWER_CUT 0xd80a
103 #define USB_MISC_0 0xd81a
104 #define USB_MISC_1 0xd81f
105 #define USB_AFE_CTRL2 0xd824
106 +#define USB_UPHY_XTAL 0xd826
107 #define USB_UPS_CFG 0xd842
108 #define USB_UPS_FLAGS 0xd848
109 #define USB_WDT1_CTRL 0xe404
111 #define OCP_EEE_ABLE 0xa5c4
112 #define OCP_EEE_ADV 0xa5d0
113 #define OCP_EEE_LPABLE 0xa5d2
114 +#define OCP_10GBT_CTRL 0xa5d4
115 +#define OCP_10GBT_STAT 0xa5d6
116 +#define OCP_EEE_ADV2 0xa6d4
117 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
118 #define OCP_PHY_PATCH_STAT 0xb800
119 #define OCP_PHY_PATCH_CMD 0xb820
122 #define SRAM_GREEN_CFG 0x8011
123 #define SRAM_LPF_CFG 0x8012
124 +#define SRAM_GPHY_FW_VER 0x801e
125 #define SRAM_10M_AMP1 0x8080
126 #define SRAM_10M_AMP2 0x8082
127 #define SRAM_IMPEDANCE 0x8084
128 @@ -210,11 +234,19 @@
129 #define RCR_AM 0x00000004
130 #define RCR_AB 0x00000008
131 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
132 +#define SLOT_EN BIT(11)
135 +#define OUTER_VLAN BIT(7)
136 +#define INNER_VLAN BIT(6)
138 /* PLA_RXFIFO_CTRL0 */
139 #define RXFIFO_THR1_NORMAL 0x00080002
140 #define RXFIFO_THR1_OOB 0x01800003
142 +/* PLA_RXFIFO_FULL */
143 +#define RXFIFO_FULL_MASK 0xfff
145 /* PLA_RXFIFO_CTRL1 */
146 #define RXFIFO_THR2_FULL 0x00000060
147 #define RXFIFO_THR2_HIGH 0x00000038
149 #define MCU_BORW_EN 0x4000
152 +#define FLOW_CTRL_EN BIT(0)
153 #define CPCR_RX_VLAN 0x0040
158 #define LANWAKE_CLR_EN BIT(0)
161 +#define EN_XG_LIP BIT(1)
162 +#define EN_G_LIP BIT(2)
165 #define BWF_EN 0x0040
166 #define MWF_EN 0x0020
168 /* PLA_MAC_PWR_CTRL2 */
169 #define EEE_SPDWN_RATIO 0x8007
170 #define MAC_CLK_SPDWN_EN BIT(15)
171 +#define EEE_SPDWN_RATIO_MASK 0xff
173 /* PLA_MAC_PWR_CTRL3 */
174 #define PLA_MCU_SPDWN_EN BIT(14)
176 #define PWRSAVE_SPDWN_EN 0x1000
177 #define RXDV_SPDWN_EN 0x0800
178 #define TX10MIDLE_EN 0x0100
179 +#define IDLE_SPDWN_EN BIT(6)
180 #define TP100_SPDWN_EN 0x0020
181 #define TP500_SPDWN_EN 0x0010
182 #define TP1000_SPDWN_EN 0x0008
184 #define LINK_CHANGE_FLAG BIT(8)
185 #define POLL_LINK_CHG BIT(0)
188 +#define GPHY_FLASH BIT(1)
190 +/* PLA_POL_GPIO_CTRL */
191 +#define DACK_DET_EN BIT(15)
192 +#define POL_GPHY_PATCH BIT(4)
195 #define USB2PHY_SUSPEND 0x0001
196 #define USB2PHY_L1 0x0002
198 #define BMU_RESET_EP_IN 0x01
199 #define BMU_RESET_EP_OUT 0x02
201 +/* USB_BMU_CONFIG */
202 +#define ACT_ODMA BIT(1)
204 /* USB_UPT_RXDMA_OWN */
205 #define OWN_UPDATE BIT(0)
206 #define OWN_CLEAR BIT(1)
207 @@ -440,27 +489,52 @@
209 #define FC_PATCH_TASK BIT(1)
211 +/* USB_RX_AGGR_NUM */
212 +#define RX_AGGR_NUM_MASK 0x1ff
215 #define POWER_CUT 0x0100
217 /* USB_PM_CTRL_STATUS */
218 #define RESUME_INDICATE 0x0001
220 +/* USB_ECM_OPTION */
221 +#define BYPASS_MAC_RESET BIT(5)
224 #define FORCE_SUPER BIT(0)
227 +#define UPS_FORCE_PWR_DOWN BIT(0)
230 +#define EN_ALL_SPEED BIT(0)
233 +#define GPHY_PATCH_DONE BIT(2)
234 +#define BYPASS_FLASH BIT(5)
235 +#define BACKUP_RESTRORE BIT(6)
237 +/* USB_SPEED_OPTION */
238 +#define RG_PWRDN_EN BIT(8)
239 +#define ALL_SPEED_OFF BIT(9)
242 #define FLOW_CTRL_PATCH_OPT BIT(1)
243 +#define AUTO_SPEEDUP BIT(3)
244 +#define FLOW_CTRL_PATCH_2 BIT(8)
247 #define CTRL_TIMER_EN BIT(15)
250 +#define CDC_ECM_EN BIT(3)
251 #define RX_AGG_DISABLE 0x0010
252 #define RX_ZERO_EN 0x0080
255 #define U2P3_ENABLE 0x0001
256 +#define RX_DETECT8 BIT(3)
259 #define PWR_EN 0x0001
261 #define SEN_VAL_NORMAL 0xa000
262 #define SEL_RXIDLE 0x0100
265 +#define OOBS_POLLING BIT(8)
268 #define SAW_CNT_1MS_MASK 0x0fff
269 +#define MID_REVERSE BIT(5) /* RTL8156A */
272 #define UPS_FLAGS_R_TUNE BIT(0)
274 #define UPS_FLAGS_250M_CKDIV BIT(2)
275 #define UPS_FLAGS_EN_ALDPS BIT(3)
276 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
277 +#define UPS_FLAGS_SPEED_MASK (0xf << 16)
278 #define ups_flags_speed(x) ((x) << 16)
279 #define UPS_FLAGS_EN_EEE BIT(20)
280 #define UPS_FLAGS_EN_500M_EEE BIT(21)
281 @@ -525,6 +604,8 @@ enum spd_duplex {
289 /* OCP_ALDPS_CONFIG */
290 @@ -589,6 +670,9 @@ enum spd_duplex {
291 #define EN_10M_CLKDIV BIT(11)
292 #define EN_10M_BGOFF 0x0080
294 +/* OCP_10GBT_CTRL */
295 +#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
298 #define TXDIS_STATE 0x01
299 #define ABD_STATE 0x02
300 @@ -608,7 +692,8 @@ enum spd_duplex {
301 #define EN_EMI_L 0x0040
304 -#define clk_div_expo(x) (min(x, 5) << 8)
305 +#define sysclk_div_expo(x) (min(x, 5) << 8)
306 +#define clk_div_expo(x) (min(x, 5) << 4)
309 #define GREEN_ETH_EN BIT(15)
310 @@ -639,6 +724,11 @@ enum spd_duplex {
311 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
313 enum rtl_register_content {
314 + _2500bps = BIT(10),
322 @@ -646,6 +736,9 @@ enum rtl_register_content {
326 +#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
327 +#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
329 #define RTL8152_MAX_TX 4
330 #define RTL8152_MAX_RX 10
332 @@ -660,7 +753,6 @@ enum rtl_register_content {
333 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
334 #define RTL8153_RMS RTL8153_MAX_PACKET
335 #define RTL8152_TX_TIMEOUT (5 * HZ)
336 -#define RTL8152_NAPI_WEIGHT 64
337 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
338 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
339 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
340 @@ -797,6 +889,7 @@ struct r8152 {
348 @@ -838,7 +931,9 @@ struct r8152 {
352 + u32 fc_pause_on, fc_pause_off;
354 + u32 support_2500full:1;
358 @@ -998,6 +1093,15 @@ enum rtl_version {
374 @@ -1013,6 +1117,7 @@ enum tx_csum_stat {
375 #define RTL_ADVERTISED_100_FULL BIT(3)
376 #define RTL_ADVERTISED_1000_HALF BIT(4)
377 #define RTL_ADVERTISED_1000_FULL BIT(5)
378 +#define RTL_ADVERTISED_2500_FULL BIT(6)
380 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
381 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
382 @@ -2606,7 +2711,7 @@ static netdev_tx_t rtl8152_start_xmit(st
384 static void r8152b_reset_packet_filter(struct r8152 *tp)
389 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
390 ocp_data &= ~FMC_FCR_MCU_EN;
391 @@ -2617,14 +2722,47 @@ static void r8152b_reset_packet_filter(s
393 static void rtl8152_nic_reset(struct r8152 *tp)
399 - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
400 + switch (tp->version) {
404 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
405 + ocp_data &= ~CR_TE;
406 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
408 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
409 + ocp_data &= ~BMU_RESET_EP_IN;
410 + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
412 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
413 + ocp_data |= CDC_ECM_EN;
414 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
416 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
417 + ocp_data &= ~CR_RE;
418 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
420 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
421 + ocp_data |= BMU_RESET_EP_IN;
422 + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
424 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
425 + ocp_data &= ~CDC_ECM_EN;
426 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
429 - for (i = 0; i < 1000; i++) {
430 - if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
432 - usleep_range(100, 400);
434 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
436 + for (i = 0; i < 1000; i++) {
437 + if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
439 + usleep_range(100, 400);
445 @@ -2633,9 +2771,9 @@ static void set_tx_qlen(struct r8152 *tp
446 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
449 -static inline u8 rtl8152_get_speed(struct r8152 *tp)
450 +static inline u16 rtl8152_get_speed(struct r8152 *tp)
452 - return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
453 + return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
456 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
457 @@ -2795,6 +2933,7 @@ static int rtl_enable(struct r8152 *tp)
458 switch (tp->version) {
462 r8153b_rx_agg_chg_indicate(tp);
465 @@ -2832,6 +2971,7 @@ static void r8153_set_rx_early_timeout(s
470 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
471 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
473 @@ -2841,6 +2981,18 @@ static void r8153_set_rx_early_timeout(s
482 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
484 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
486 + r8153b_rx_agg_chg_indicate(tp);
492 @@ -2860,8 +3012,19 @@ static void r8153_set_rx_early_size(stru
497 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
506 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
508 + r8153b_rx_agg_chg_indicate(tp);
512 @@ -2871,6 +3034,8 @@ static void r8153_set_rx_early_size(stru
514 static int rtl8153_enable(struct r8152 *tp)
518 if (test_bit(RTL8152_UNPLUG, &tp->flags))
521 @@ -2881,15 +3046,18 @@ static int rtl8153_enable(struct r8152 *
523 rtl_set_ifg(tp, rtl8152_get_speed(tp));
525 - if (tp->version == RTL_VER_09) {
528 + switch (tp->version) {
531 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
532 ocp_data &= ~FC_PATCH_TASK;
533 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
534 usleep_range(1000, 2000);
535 ocp_data |= FC_PATCH_TASK;
536 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
542 return rtl_enable(tp);
543 @@ -2954,12 +3122,40 @@ static void rtl_rx_vlan_en(struct r8152
547 - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
549 - ocp_data |= CPCR_RX_VLAN;
551 - ocp_data &= ~CPCR_RX_VLAN;
552 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
553 + switch (tp->version) {
564 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
566 + ocp_data |= CPCR_RX_VLAN;
568 + ocp_data &= ~CPCR_RX_VLAN;
569 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
579 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
581 + ocp_data |= OUTER_VLAN | INNER_VLAN;
583 + ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
584 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
589 static int rtl8152_set_features(struct net_device *dev,
590 @@ -3052,6 +3248,40 @@ static void __rtl_set_wol(struct r8152 *
591 device_set_wakeup_enable(&tp->udev->dev, false);
594 +static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
596 + u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
598 + /* MAC clock speed down */
600 + ocp_data |= MAC_CLK_SPDWN_EN;
602 + ocp_data &= ~MAC_CLK_SPDWN_EN;
604 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
607 +static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
611 + /* MAC clock speed down */
613 + /* aldps_spdwn_ratio, tp10_spdwn_ratio */
614 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
617 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
618 + ocp_data &= ~EEE_SPDWN_RATIO_MASK;
619 + ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
620 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
622 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
623 + ocp_data &= ~MAC_CLK_SPDWN_EN;
624 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
628 static void r8153_u1u2en(struct r8152 *tp, bool enable)
631 @@ -3111,6 +3341,9 @@ static void r8153b_ups_flags(struct r815
632 if (tp->ups_info.eee_cmod_lv)
633 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
635 + if (tp->ups_info.r_tune)
636 + ups_flags |= UPS_FLAGS_R_TUNE;
638 if (tp->ups_info._10m_ckdiv)
639 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
641 @@ -3161,6 +3394,88 @@ static void r8153b_ups_flags(struct r815
642 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
645 +static void r8156_ups_flags(struct r8152 *tp)
649 + if (tp->ups_info.green)
650 + ups_flags |= UPS_FLAGS_EN_GREEN;
652 + if (tp->ups_info.aldps)
653 + ups_flags |= UPS_FLAGS_EN_ALDPS;
655 + if (tp->ups_info.eee)
656 + ups_flags |= UPS_FLAGS_EN_EEE;
658 + if (tp->ups_info.flow_control)
659 + ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
661 + if (tp->ups_info.eee_ckdiv)
662 + ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
664 + if (tp->ups_info._10m_ckdiv)
665 + ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
667 + if (tp->ups_info.eee_plloff_100)
668 + ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
670 + if (tp->ups_info.eee_plloff_giga)
671 + ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
673 + if (tp->ups_info._250m_ckdiv)
674 + ups_flags |= UPS_FLAGS_250M_CKDIV;
676 + switch (tp->ups_info.speed_duplex) {
677 + case FORCE_10M_HALF:
678 + ups_flags |= ups_flags_speed(0);
680 + case FORCE_10M_FULL:
681 + ups_flags |= ups_flags_speed(1);
683 + case FORCE_100M_HALF:
684 + ups_flags |= ups_flags_speed(2);
686 + case FORCE_100M_FULL:
687 + ups_flags |= ups_flags_speed(3);
689 + case NWAY_10M_HALF:
690 + ups_flags |= ups_flags_speed(4);
692 + case NWAY_10M_FULL:
693 + ups_flags |= ups_flags_speed(5);
695 + case NWAY_100M_HALF:
696 + ups_flags |= ups_flags_speed(6);
698 + case NWAY_100M_FULL:
699 + ups_flags |= ups_flags_speed(7);
701 + case NWAY_1000M_FULL:
702 + ups_flags |= ups_flags_speed(8);
704 + case NWAY_2500M_FULL:
705 + ups_flags |= ups_flags_speed(9);
711 + switch (tp->ups_info.lite_mode) {
713 + ups_flags |= 0 << 5;
716 + ups_flags |= 2 << 5;
720 + ups_flags |= 1 << 5;
724 + ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
727 static void rtl_green_en(struct r8152 *tp, bool enable)
730 @@ -3224,16 +3539,16 @@ static void r8153b_ups_en(struct r8152 *
731 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
732 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
734 - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
735 - ocp_data |= BIT(0);
736 - ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
737 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
738 + ocp_data |= UPS_FORCE_PWR_DOWN;
739 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
741 ocp_data &= ~(UPS_EN | USP_PREWAKE);
742 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
744 - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
745 - ocp_data &= ~BIT(0);
746 - ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
747 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
748 + ocp_data &= ~UPS_FORCE_PWR_DOWN;
749 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
751 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
753 @@ -3253,6 +3568,95 @@ static void r8153b_ups_en(struct r8152 *
757 +static void r8153c_ups_en(struct r8152 *tp, bool enable)
759 + u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
762 + r8153b_ups_flags(tp);
764 + ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
765 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
767 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
768 + ocp_data |= UPS_FORCE_PWR_DOWN;
769 + ocp_data &= ~BIT(7);
770 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
772 + ocp_data &= ~(UPS_EN | USP_PREWAKE);
773 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
775 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
776 + ocp_data &= ~UPS_FORCE_PWR_DOWN;
777 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
779 + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
782 + for (i = 0; i < 500; i++) {
783 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
789 + tp->rtl_ops.hw_phy_cfg(tp);
791 + rtl8152_set_speed(tp, tp->autoneg, tp->speed,
792 + tp->duplex, tp->advertising);
795 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
797 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
798 + ocp_data |= BIT(8);
799 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
801 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
805 +static void r8156_ups_en(struct r8152 *tp, bool enable)
807 + u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
810 + r8156_ups_flags(tp);
812 + ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
813 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
815 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
816 + ocp_data |= UPS_FORCE_PWR_DOWN;
817 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
819 + switch (tp->version) {
822 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
823 + ocp_data &= ~OOBS_POLLING;
824 + ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
830 + ocp_data &= ~(UPS_EN | USP_PREWAKE);
831 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
833 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
834 + ocp_data &= ~UPS_FORCE_PWR_DOWN;
835 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
837 + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
838 + tp->rtl_ops.hw_phy_cfg(tp);
840 + rtl8152_set_speed(tp, tp->autoneg, tp->speed,
841 + tp->duplex, tp->advertising);
846 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
849 @@ -3382,6 +3786,38 @@ static void rtl8153b_runtime_enable(stru
853 +static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
856 + r8153_queue_wake(tp, true);
857 + r8153b_u1u2en(tp, false);
858 + r8153_u2p3en(tp, false);
859 + rtl_runtime_suspend_enable(tp, true);
860 + r8153c_ups_en(tp, true);
862 + r8153c_ups_en(tp, false);
863 + r8153_queue_wake(tp, false);
864 + rtl_runtime_suspend_enable(tp, false);
865 + r8153b_u1u2en(tp, true);
869 +static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
872 + r8153_queue_wake(tp, true);
873 + r8153b_u1u2en(tp, false);
874 + r8153_u2p3en(tp, false);
875 + rtl_runtime_suspend_enable(tp, true);
877 + r8153_queue_wake(tp, false);
878 + rtl_runtime_suspend_enable(tp, false);
879 + r8153_u2p3en(tp, true);
880 + if (tp->udev->speed >= USB_SPEED_SUPER)
881 + r8153b_u1u2en(tp, true);
885 static void r8153_teredo_off(struct r8152 *tp)
888 @@ -3402,14 +3838,19 @@ static void r8153_teredo_off(struct r815
900 /* The bit 0 ~ 7 are relative with teredo settings. They are
901 * W1C (write 1 to clear), so set all 1 to disable it.
903 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
910 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
911 @@ -3444,6 +3885,12 @@ static void rtl_clear_bp(struct r8152 *t
922 if (type == MCU_TYPE_USB) {
923 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
924 @@ -3653,6 +4100,11 @@ static bool rtl8152_is_fw_mac_ok(struct
934 bp_ba_addr = PLA_BP_BA;
935 bp_en_addr = PLA_BP_EN;
936 @@ -3676,6 +4128,11 @@ static bool rtl8152_is_fw_mac_ok(struct
946 bp_ba_addr = USB_BP_BA;
947 bp_en_addr = USB_BP2_EN;
948 @@ -4215,6 +4672,22 @@ static void r8153_eee_en(struct r8152 *t
949 tp->ups_info.eee = enable;
952 +static void r8156_eee_en(struct r8152 *tp, bool enable)
956 + r8153_eee_en(tp, enable);
958 + config = ocp_reg_read(tp, OCP_EEE_ADV2);
961 + config |= MDIO_EEE_2_5GT;
963 + config &= ~MDIO_EEE_2_5GT;
965 + ocp_reg_write(tp, OCP_EEE_ADV2, config);
968 static void rtl_eee_enable(struct r8152 *tp, bool enable)
970 switch (tp->version) {
971 @@ -4236,6 +4709,7 @@ static void rtl_eee_enable(struct r8152
977 r8153_eee_en(tp, true);
978 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
979 @@ -4244,6 +4718,19 @@ static void rtl_eee_enable(struct r8152
980 ocp_reg_write(tp, OCP_EEE_ADV, 0);
989 + r8156_eee_en(tp, true);
990 + ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
992 + r8156_eee_en(tp, false);
993 + ocp_reg_write(tp, OCP_EEE_ADV, 0);
999 @@ -4290,6 +4777,20 @@ static void wait_oob_link_list_ready(str
1003 +static void r8156b_wait_loading_flash(struct r8152 *tp)
1005 + if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
1006 + !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
1009 + for (i = 0; i < 100; i++) {
1010 + if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
1012 + usleep_range(1000, 2000);
1017 static void r8152b_exit_oob(struct r8152 *tp)
1020 @@ -4340,7 +4841,7 @@ static void r8152b_exit_oob(struct r8152
1023 /* TX share fifo free credit full threshold */
1024 - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1025 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
1027 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1028 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
1029 @@ -4517,6 +5018,21 @@ static int r8153b_post_firmware_1(struct
1033 +static int r8153c_post_firmware_1(struct r8152 *tp)
1037 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
1038 + ocp_data |= FLOW_CTRL_PATCH_2;
1039 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
1041 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
1042 + ocp_data |= FC_PATCH_TASK;
1043 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
1048 static void r8153_aldps_en(struct r8152 *tp, bool enable)
1051 @@ -4719,6 +5235,13 @@ static void r8153b_hw_phy_cfg(struct r81
1052 set_bit(PHY_RESET, &tp->flags);
1055 +static void r8153c_hw_phy_cfg(struct r8152 *tp)
1057 + r8153b_hw_phy_cfg(tp);
1059 + tp->ups_info.r_tune = true;
1062 static void rtl8153_change_mtu(struct r8152 *tp)
1064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
1065 @@ -4806,6 +5329,7 @@ static void r8153_enter_oob(struct r8152
1070 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
1071 * type. Set it to zero. bits[7:0] are the W1C bits about
1072 * the events. Set them to all 1 to clear them.
1073 @@ -4842,6 +5366,96 @@ static void rtl8153_disable(struct r8152
1074 r8153_aldps_en(tp, true);
1077 +static int rtl8156_enable(struct r8152 *tp)
1082 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1086 + rtl_set_eee_plus(tp);
1087 + r8153_set_rx_early_timeout(tp);
1088 + r8153_set_rx_early_size(tp);
1090 + speed = rtl8152_get_speed(tp);
1091 + rtl_set_ifg(tp, speed);
1093 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
1094 + if (speed & _2500bps)
1095 + ocp_data &= ~IDLE_SPDWN_EN;
1097 + ocp_data |= IDLE_SPDWN_EN;
1098 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
1100 + if (speed & _1000bps)
1101 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
1102 + else if (speed & _500bps)
1103 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
1105 + if (tp->udev->speed == USB_SPEED_HIGH) {
1106 + /* USB 0xb45e[3:0] l1_nyet_hird */
1107 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
1109 + if (is_flow_control(speed))
1113 + ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
1116 + return rtl_enable(tp);
1119 +static int rtl8156b_enable(struct r8152 *tp)
1124 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1128 + rtl_set_eee_plus(tp);
1130 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
1131 + ocp_data &= ~RX_AGGR_NUM_MASK;
1132 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
1134 + r8153_set_rx_early_timeout(tp);
1135 + r8153_set_rx_early_size(tp);
1137 + speed = rtl8152_get_speed(tp);
1138 + rtl_set_ifg(tp, speed);
1140 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
1141 + if (speed & _2500bps)
1142 + ocp_data &= ~IDLE_SPDWN_EN;
1144 + ocp_data |= IDLE_SPDWN_EN;
1145 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
1147 + if (tp->udev->speed == USB_SPEED_HIGH) {
1148 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
1150 + if (is_flow_control(speed))
1154 + ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
1157 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
1158 + ocp_data &= ~FC_PATCH_TASK;
1159 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
1160 + usleep_range(1000, 2000);
1161 + ocp_data |= FC_PATCH_TASK;
1162 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
1164 + return rtl_enable(tp);
1167 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1170 @@ -4890,58 +5504,73 @@ static int rtl8152_set_speed(struct r815
1172 tp->mii.force_media = 1;
1178 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
1179 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
1181 - if (tp->mii.supports_gmii)
1182 + if (tp->mii.supports_gmii) {
1183 support |= RTL_ADVERTISED_1000_FULL;
1185 + if (tp->support_2500full)
1186 + support |= RTL_ADVERTISED_2500_FULL;
1189 if (!(advertising & support))
1192 - anar = r8152_mdio_read(tp, MII_ADVERTISE);
1193 - tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1194 + orig = r8152_mdio_read(tp, MII_ADVERTISE);
1195 + new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1196 ADVERTISE_100HALF | ADVERTISE_100FULL);
1197 if (advertising & RTL_ADVERTISED_10_HALF) {
1198 - tmp1 |= ADVERTISE_10HALF;
1199 + new1 |= ADVERTISE_10HALF;
1200 tp->ups_info.speed_duplex = NWAY_10M_HALF;
1202 if (advertising & RTL_ADVERTISED_10_FULL) {
1203 - tmp1 |= ADVERTISE_10FULL;
1204 + new1 |= ADVERTISE_10FULL;
1205 tp->ups_info.speed_duplex = NWAY_10M_FULL;
1208 if (advertising & RTL_ADVERTISED_100_HALF) {
1209 - tmp1 |= ADVERTISE_100HALF;
1210 + new1 |= ADVERTISE_100HALF;
1211 tp->ups_info.speed_duplex = NWAY_100M_HALF;
1213 if (advertising & RTL_ADVERTISED_100_FULL) {
1214 - tmp1 |= ADVERTISE_100FULL;
1215 + new1 |= ADVERTISE_100FULL;
1216 tp->ups_info.speed_duplex = NWAY_100M_FULL;
1219 - if (anar != tmp1) {
1220 - r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
1221 - tp->mii.advertising = tmp1;
1222 + if (orig != new1) {
1223 + r8152_mdio_write(tp, MII_ADVERTISE, new1);
1224 + tp->mii.advertising = new1;
1227 if (tp->mii.supports_gmii) {
1230 - gbcr = r8152_mdio_read(tp, MII_CTRL1000);
1231 - tmp1 = gbcr & ~(ADVERTISE_1000FULL |
1232 + orig = r8152_mdio_read(tp, MII_CTRL1000);
1233 + new1 = orig & ~(ADVERTISE_1000FULL |
1234 ADVERTISE_1000HALF);
1236 if (advertising & RTL_ADVERTISED_1000_FULL) {
1237 - tmp1 |= ADVERTISE_1000FULL;
1238 + new1 |= ADVERTISE_1000FULL;
1239 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
1243 - r8152_mdio_write(tp, MII_CTRL1000, tmp1);
1245 + r8152_mdio_write(tp, MII_CTRL1000, new1);
1248 + if (tp->support_2500full) {
1249 + orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
1250 + new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
1252 + if (advertising & RTL_ADVERTISED_2500_FULL) {
1253 + new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
1254 + tp->ups_info.speed_duplex = NWAY_2500M_FULL;
1258 + ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
1261 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1262 @@ -5097,6 +5726,253 @@ static void rtl8153b_down(struct r8152 *
1263 r8153_aldps_en(tp, true);
1266 +static void rtl8153c_change_mtu(struct r8152 *tp)
1268 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
1269 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
1271 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
1273 + /* Adjust the tx fifo free credit full threshold, otherwise
1274 + * the fifo would be too small to send a jumbo frame packet.
1276 + if (tp->netdev->mtu < 8000)
1277 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
1279 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
1282 +static void rtl8153c_up(struct r8152 *tp)
1286 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1289 + r8153b_u1u2en(tp, false);
1290 + r8153_u2p3en(tp, false);
1291 + r8153_aldps_en(tp, false);
1293 + rxdy_gated_en(tp, true);
1294 + r8153_teredo_off(tp);
1296 + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1297 + ocp_data &= ~RCR_ACPT_ALL;
1298 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1300 + rtl8152_nic_reset(tp);
1301 + rtl_reset_bmu(tp);
1303 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1304 + ocp_data &= ~NOW_IS_OOB;
1305 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1307 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1308 + ocp_data &= ~MCU_BORW_EN;
1309 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1311 + wait_oob_link_list_ready(tp);
1313 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1314 + ocp_data |= RE_INIT_LL;
1315 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1317 + wait_oob_link_list_ready(tp);
1319 + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
1321 + rtl8153c_change_mtu(tp);
1323 + rtl8152_nic_reset(tp);
1325 + /* rx share fifo credit full threshold */
1326 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
1327 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
1328 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
1329 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
1331 + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
1333 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1335 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1336 + ocp_data |= BIT(8);
1337 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
1339 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1341 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1342 + ocp_data &= ~PLA_MCU_SPDWN_EN;
1343 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1345 + r8153_aldps_en(tp, true);
1346 + r8153b_u1u2en(tp, true);
1349 +static inline u32 fc_pause_on_auto(struct r8152 *tp)
1351 + return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
1354 +static inline u32 fc_pause_off_auto(struct r8152 *tp)
1356 + return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
1359 +static void r8156_fc_parameter(struct r8152 *tp)
1361 + u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
1362 + u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
1364 + switch (tp->version) {
1367 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
1368 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
1373 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
1374 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
1381 +static void rtl8156_change_mtu(struct r8152 *tp)
1383 + u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
1385 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
1386 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
1387 + r8156_fc_parameter(tp);
1389 + /* TX share fifo free credit full threshold */
1390 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
1391 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
1392 + ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
1395 +static void rtl8156_up(struct r8152 *tp)
1399 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1402 + r8153b_u1u2en(tp, false);
1403 + r8153_u2p3en(tp, false);
1404 + r8153_aldps_en(tp, false);
1406 + rxdy_gated_en(tp, true);
1407 + r8153_teredo_off(tp);
1409 + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1410 + ocp_data &= ~RCR_ACPT_ALL;
1411 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1413 + rtl8152_nic_reset(tp);
1414 + rtl_reset_bmu(tp);
1416 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1417 + ocp_data &= ~NOW_IS_OOB;
1418 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1420 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1421 + ocp_data &= ~MCU_BORW_EN;
1422 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1424 + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
1426 + rtl8156_change_mtu(tp);
1428 + switch (tp->version) {
1432 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
1433 + ocp_data |= ACT_ODMA;
1434 + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
1440 + /* share FIFO settings */
1441 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
1442 + ocp_data &= ~RXFIFO_FULL_MASK;
1444 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
1446 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1447 + ocp_data &= ~PLA_MCU_SPDWN_EN;
1448 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1450 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
1451 + ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
1452 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
1454 + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
1456 + if (tp->saved_wolopts != __rtl_get_wol(tp)) {
1457 + netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
1458 + __rtl_set_wol(tp, tp->saved_wolopts);
1461 + r8153_aldps_en(tp, true);
1462 + r8153_u2p3en(tp, true);
1464 + if (tp->udev->speed >= USB_SPEED_SUPER)
1465 + r8153b_u1u2en(tp, true);
1468 +static void rtl8156_down(struct r8152 *tp)
1472 + if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
1473 + rtl_drop_queued_tx(tp);
1477 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1478 + ocp_data |= PLA_MCU_SPDWN_EN;
1479 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1481 + r8153b_u1u2en(tp, false);
1482 + r8153_u2p3en(tp, false);
1483 + r8153b_power_cut_en(tp, false);
1484 + r8153_aldps_en(tp, false);
1486 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1487 + ocp_data &= ~NOW_IS_OOB;
1488 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1491 + rtl_reset_bmu(tp);
1493 + /* Clear teredo wake event. bit[15:8] is the teredo wakeup
1494 + * type. Set it to zero. bits[7:0] are the W1C bits about
1495 + * the events. Set them to all 1 to clear them.
1497 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
1499 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1500 + ocp_data |= NOW_IS_OOB;
1501 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1503 + rtl_rx_vlan_en(tp, true);
1504 + rxdy_gated_en(tp, false);
1506 + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1507 + ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1508 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1510 + r8153_aldps_en(tp, true);
1513 static bool rtl8152_in_nway(struct r8152 *tp)
1516 @@ -5127,7 +6003,7 @@ static void set_carrier(struct r8152 *tp
1518 struct net_device *netdev = tp->netdev;
1519 struct napi_struct *napi = &tp->napi;
1523 speed = rtl8152_get_speed(tp);
1525 @@ -5140,7 +6016,7 @@ static void set_carrier(struct r8152 *tp
1527 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1528 _rtl8152_set_rx_mode(netdev);
1529 - napi_enable(&tp->napi);
1530 + napi_enable(napi);
1531 netif_wake_queue(netdev);
1532 netif_info(tp, link, netdev, "carrier on\n");
1533 } else if (netif_queue_stopped(netdev) &&
1534 @@ -5502,14 +6378,9 @@ static void r8153_init(struct r8152 *tp)
1536 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1538 - /* MAC clock speed down */
1539 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
1540 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
1541 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
1542 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
1544 r8153_power_cut_en(tp, false);
1545 rtl_runtime_suspend_enable(tp, false);
1546 + r8153_mac_clk_speed_down(tp, false);
1547 r8153_u1u2en(tp, true);
1548 usb_enable_lpm(tp->udev);
1550 @@ -5600,9 +6471,7 @@ static void r8153b_init(struct r8152 *tp
1551 usb_enable_lpm(tp->udev);
1553 /* MAC clock speed down */
1554 - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
1555 - ocp_data |= MAC_CLK_SPDWN_EN;
1556 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
1557 + r8153_mac_clk_speed_down(tp, true);
1559 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1560 ocp_data &= ~PLA_MCU_SPDWN_EN;
1561 @@ -5629,6 +6498,1069 @@ static void r8153b_init(struct r8152 *tp
1562 tp->coalesce = 15000; /* 15 us */
1565 +static void r8153c_init(struct r8152 *tp)
1571 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1574 + r8153b_u1u2en(tp, false);
1576 + /* Disable spi_en */
1577 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1578 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1579 + ocp_data &= ~BIT(3);
1580 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
1581 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
1582 + ocp_data |= BIT(1);
1583 + ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
1585 + for (i = 0; i < 500; i++) {
1586 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
1591 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1595 + data = r8153_phy_status(tp, 0);
1597 + data = r8152_mdio_read(tp, MII_BMCR);
1598 + if (data & BMCR_PDOWN) {
1599 + data &= ~BMCR_PDOWN;
1600 + r8152_mdio_write(tp, MII_BMCR, data);
1603 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
1605 + r8153_u2p3en(tp, false);
1607 + /* MSC timer = 0xfff * 8ms = 32760 ms */
1608 + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
1610 + r8153b_power_cut_en(tp, false);
1611 + r8153c_ups_en(tp, false);
1612 + r8153_queue_wake(tp, false);
1613 + rtl_runtime_suspend_enable(tp, false);
1615 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
1616 + if (rtl8152_get_speed(tp) & LINK_STATUS)
1617 + ocp_data |= CUR_LINK_OK;
1619 + ocp_data &= ~CUR_LINK_OK;
1621 + ocp_data |= POLL_LINK_CHG;
1622 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
1624 + r8153b_u1u2en(tp, true);
1626 + usb_enable_lpm(tp->udev);
1628 + /* MAC clock speed down */
1629 + r8153_mac_clk_speed_down(tp, true);
1631 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
1632 + ocp_data &= ~BIT(7);
1633 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
1635 + set_bit(GREEN_ETHERNET, &tp->flags);
1637 + /* rx aggregation */
1638 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1639 + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1640 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1642 + rtl_tally_reset(tp);
1644 + tp->coalesce = 15000; /* 15 us */
1647 +static void r8156_hw_phy_cfg(struct r8152 *tp)
1652 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1653 + if (ocp_data & PCUT_STATUS) {
1654 + ocp_data &= ~PCUT_STATUS;
1655 + ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
1658 + data = r8153_phy_status(tp, 0);
1660 + case PHY_STAT_EXT_INIT:
1661 + rtl8152_apply_firmware(tp, true);
1663 + data = ocp_reg_read(tp, 0xa468);
1664 + data &= ~(BIT(3) | BIT(1));
1665 + ocp_reg_write(tp, 0xa468, data);
1667 + case PHY_STAT_LAN_ON:
1668 + case PHY_STAT_PWRDN:
1670 + rtl8152_apply_firmware(tp, false);
1674 + /* disable ALDPS before updating the PHY parameters */
1675 + r8153_aldps_en(tp, false);
1677 + /* disable EEE before updating the PHY parameters */
1678 + rtl_eee_enable(tp, false);
1680 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
1681 + WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
1683 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1684 + ocp_data |= PFM_PWM_SWITCH;
1685 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1687 + switch (tp->version) {
1689 + data = ocp_reg_read(tp, 0xad40);
1691 + data |= BIT(7) | BIT(2);
1692 + ocp_reg_write(tp, 0xad40, data);
1694 + data = ocp_reg_read(tp, 0xad4e);
1696 + ocp_reg_write(tp, 0xad4e, data);
1697 + data = ocp_reg_read(tp, 0xad16);
1700 + ocp_reg_write(tp, 0xad16, data);
1701 + data = ocp_reg_read(tp, 0xad32);
1704 + ocp_reg_write(tp, 0xad32, data);
1705 + data = ocp_reg_read(tp, 0xac08);
1706 + data &= ~(BIT(12) | BIT(8));
1707 + ocp_reg_write(tp, 0xac08, data);
1708 + data = ocp_reg_read(tp, 0xac8a);
1709 + data |= BIT(12) | BIT(13) | BIT(14);
1711 + ocp_reg_write(tp, 0xac8a, data);
1712 + data = ocp_reg_read(tp, 0xad18);
1714 + ocp_reg_write(tp, 0xad18, data);
1715 + data = ocp_reg_read(tp, 0xad1a);
1717 + ocp_reg_write(tp, 0xad1a, data);
1718 + data = ocp_reg_read(tp, 0xad1c);
1720 + ocp_reg_write(tp, 0xad1c, data);
1722 + data = sram_read(tp, 0x80ea);
1725 + sram_write(tp, 0x80ea, data);
1726 + data = sram_read(tp, 0x80eb);
1729 + sram_write(tp, 0x80eb, data);
1730 + data = sram_read(tp, 0x80f8);
1733 + sram_write(tp, 0x80f8, data);
1734 + data = sram_read(tp, 0x80f1);
1737 + sram_write(tp, 0x80f1, data);
1739 + data = sram_read(tp, 0x80fe);
1742 + sram_write(tp, 0x80fe, data);
1743 + data = sram_read(tp, 0x8102);
1746 + sram_write(tp, 0x8102, data);
1747 + data = sram_read(tp, 0x8015);
1750 + sram_write(tp, 0x8015, data);
1751 + data = sram_read(tp, 0x8100);
1754 + sram_write(tp, 0x8100, data);
1755 + data = sram_read(tp, 0x8014);
1758 + sram_write(tp, 0x8014, data);
1759 + data = sram_read(tp, 0x8016);
1762 + sram_write(tp, 0x8016, data);
1763 + data = sram_read(tp, 0x80dc);
1766 + sram_write(tp, 0x80dc, data);
1767 + data = sram_read(tp, 0x80df);
1769 + sram_write(tp, 0x80df, data);
1770 + data = sram_read(tp, 0x80e1);
1772 + sram_write(tp, 0x80e1, data);
1774 + data = ocp_reg_read(tp, 0xbf06);
1777 + ocp_reg_write(tp, 0xbf06, data);
1779 + sram_write(tp, 0x819f, 0xddb6);
1781 + ocp_reg_write(tp, 0xbc34, 0x5555);
1782 + data = ocp_reg_read(tp, 0xbf0a);
1785 + ocp_reg_write(tp, 0xbf0a, data);
1787 + data = ocp_reg_read(tp, 0xbd2c);
1789 + ocp_reg_write(tp, 0xbd2c, data);
1792 + data = ocp_reg_read(tp, 0xad16);
1794 + ocp_reg_write(tp, 0xad16, data);
1795 + data = ocp_reg_read(tp, 0xad32);
1798 + ocp_reg_write(tp, 0xad32, data);
1799 + data = ocp_reg_read(tp, 0xac08);
1800 + data &= ~(BIT(12) | BIT(8));
1801 + ocp_reg_write(tp, 0xac08, data);
1802 + data = ocp_reg_read(tp, 0xacc0);
1805 + ocp_reg_write(tp, 0xacc0, data);
1806 + data = ocp_reg_read(tp, 0xad40);
1808 + data |= BIT(6) | BIT(2);
1809 + ocp_reg_write(tp, 0xad40, data);
1810 + data = ocp_reg_read(tp, 0xac14);
1812 + ocp_reg_write(tp, 0xac14, data);
1813 + data = ocp_reg_read(tp, 0xac80);
1814 + data &= ~(BIT(8) | BIT(9));
1815 + ocp_reg_write(tp, 0xac80, data);
1816 + data = ocp_reg_read(tp, 0xac5e);
1819 + ocp_reg_write(tp, 0xac5e, data);
1820 + ocp_reg_write(tp, 0xad4c, 0x00a8);
1821 + ocp_reg_write(tp, 0xac5c, 0x01ff);
1822 + data = ocp_reg_read(tp, 0xac8a);
1824 + data |= BIT(4) | BIT(5);
1825 + ocp_reg_write(tp, 0xac8a, data);
1826 + ocp_reg_write(tp, 0xb87c, 0x8157);
1827 + data = ocp_reg_read(tp, 0xb87e);
1830 + ocp_reg_write(tp, 0xb87e, data);
1831 + ocp_reg_write(tp, 0xb87c, 0x8159);
1832 + data = ocp_reg_read(tp, 0xb87e);
1835 + ocp_reg_write(tp, 0xb87e, data);
1838 + ocp_reg_write(tp, 0xb87c, 0x80a2);
1839 + ocp_reg_write(tp, 0xb87e, 0x0153);
1840 + ocp_reg_write(tp, 0xb87c, 0x809c);
1841 + ocp_reg_write(tp, 0xb87e, 0x0153);
1843 + /* EEE parameter */
1844 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
1846 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
1847 + ocp_data |= EN_XG_LIP | EN_G_LIP;
1848 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
1850 + sram_write(tp, 0x8257, 0x020f); /* XG PLL */
1851 + sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
1853 + if (rtl_phy_patch_request(tp, true, true))
1857 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
1858 + ocp_data |= EEE_SPDWN_EN;
1859 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
1861 + data = ocp_reg_read(tp, OCP_DOWN_SPEED);
1862 + data &= ~(EN_EEE_100 | EN_EEE_1000);
1863 + data |= EN_10M_CLKDIV;
1864 + ocp_reg_write(tp, OCP_DOWN_SPEED, data);
1865 + tp->ups_info._10m_ckdiv = true;
1866 + tp->ups_info.eee_plloff_100 = false;
1867 + tp->ups_info.eee_plloff_giga = false;
1869 + data = ocp_reg_read(tp, OCP_POWER_CFG);
1870 + data &= ~EEE_CLKDIV_EN;
1871 + ocp_reg_write(tp, OCP_POWER_CFG, data);
1872 + tp->ups_info.eee_ckdiv = false;
1874 + ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
1875 + ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
1876 + tp->ups_info._250m_ckdiv = false;
1878 + rtl_phy_patch_request(tp, false, true);
1880 + /* enable ADC Ibias Cal */
1881 + data = ocp_reg_read(tp, 0xd068);
1883 + ocp_reg_write(tp, 0xd068, data);
1885 + /* enable Thermal Sensor */
1886 + data = sram_read(tp, 0x81a2);
1888 + sram_write(tp, 0x81a2, data);
1889 + data = ocp_reg_read(tp, 0xb54c);
1892 + ocp_reg_write(tp, 0xb54c, data);
1894 + /* Nway 2.5G Lite */
1895 + data = ocp_reg_read(tp, 0xa454);
1897 + ocp_reg_write(tp, 0xa454, data);
1899 + /* CS DSP solution */
1900 + data = ocp_reg_read(tp, OCP_10GBT_CTRL);
1901 + data |= RTL_ADV2_5G_F_R;
1902 + ocp_reg_write(tp, OCP_10GBT_CTRL, data);
1903 + data = ocp_reg_read(tp, 0xad4e);
1905 + ocp_reg_write(tp, 0xad4e, data);
1906 + data = ocp_reg_read(tp, 0xa86a);
1908 + ocp_reg_write(tp, 0xa86a, data);
1911 + if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
1912 + (ocp_reg_read(tp, 0xd068) & BIT(1))) {
1913 + u16 swap_a, swap_b;
1915 + data = ocp_reg_read(tp, 0xd068);
1917 + data |= 0x1; /* p0 */
1918 + ocp_reg_write(tp, 0xd068, data);
1919 + swap_a = ocp_reg_read(tp, 0xd06a);
1921 + data |= 0x18; /* p3 */
1922 + ocp_reg_write(tp, 0xd068, data);
1923 + swap_b = ocp_reg_read(tp, 0xd06a);
1924 + data &= ~0x18; /* p0 */
1925 + ocp_reg_write(tp, 0xd068, data);
1926 + ocp_reg_write(tp, 0xd06a,
1927 + (swap_a & ~0x7ff) | (swap_b & 0x7ff));
1928 + data |= 0x18; /* p3 */
1929 + ocp_reg_write(tp, 0xd068, data);
1930 + ocp_reg_write(tp, 0xd06a,
1931 + (swap_b & ~0x7ff) | (swap_a & 0x7ff));
1933 + data |= 0x08; /* p1 */
1934 + ocp_reg_write(tp, 0xd068, data);
1935 + swap_a = ocp_reg_read(tp, 0xd06a);
1937 + data |= 0x10; /* p2 */
1938 + ocp_reg_write(tp, 0xd068, data);
1939 + swap_b = ocp_reg_read(tp, 0xd06a);
1941 + data |= 0x08; /* p1 */
1942 + ocp_reg_write(tp, 0xd068, data);
1943 + ocp_reg_write(tp, 0xd06a,
1944 + (swap_a & ~0x7ff) | (swap_b & 0x7ff));
1946 + data |= 0x10; /* p2 */
1947 + ocp_reg_write(tp, 0xd068, data);
1948 + ocp_reg_write(tp, 0xd06a,
1949 + (swap_b & ~0x7ff) | (swap_a & 0x7ff));
1950 + swap_a = ocp_reg_read(tp, 0xbd5a);
1951 + swap_b = ocp_reg_read(tp, 0xbd5c);
1952 + ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
1953 + ((swap_b & 0x1f) << 8) |
1954 + ((swap_b >> 8) & 0x1f));
1955 + ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
1956 + ((swap_a & 0x1f) << 8) |
1957 + ((swap_a >> 8) & 0x1f));
1958 + swap_a = ocp_reg_read(tp, 0xbc18);
1959 + swap_b = ocp_reg_read(tp, 0xbc1a);
1960 + ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
1961 + ((swap_b & 0x1f) << 8) |
1962 + ((swap_b >> 8) & 0x1f));
1963 + ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
1964 + ((swap_a & 0x1f) << 8) |
1965 + ((swap_a >> 8) & 0x1f));
1972 + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
1974 + data = ocp_reg_read(tp, 0xa428);
1976 + ocp_reg_write(tp, 0xa428, data);
1977 + data = ocp_reg_read(tp, 0xa5ea);
1979 + ocp_reg_write(tp, 0xa5ea, data);
1980 + tp->ups_info.lite_mode = 0;
1983 + rtl_eee_enable(tp, true);
1985 + r8153_aldps_en(tp, true);
1986 + r8152b_enable_fc(tp);
1987 + r8153_u2p3en(tp, true);
1989 + set_bit(PHY_RESET, &tp->flags);
1992 +static void r8156b_hw_phy_cfg(struct r8152 *tp)
1997 + switch (tp->version) {
1999 + ocp_reg_write(tp, 0xbf86, 0x9000);
2000 + data = ocp_reg_read(tp, 0xc402);
2002 + ocp_reg_write(tp, 0xc402, data);
2004 + ocp_reg_write(tp, 0xc402, data);
2005 + ocp_reg_write(tp, 0xbd86, 0x1010);
2006 + ocp_reg_write(tp, 0xbd88, 0x1010);
2007 + data = ocp_reg_read(tp, 0xbd4e);
2008 + data &= ~(BIT(10) | BIT(11));
2010 + ocp_reg_write(tp, 0xbd4e, data);
2011 + data = ocp_reg_read(tp, 0xbf46);
2014 + ocp_reg_write(tp, 0xbf46, data);
2018 + r8156b_wait_loading_flash(tp);
2024 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2025 + if (ocp_data & PCUT_STATUS) {
2026 + ocp_data &= ~PCUT_STATUS;
2027 + ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2030 + data = r8153_phy_status(tp, 0);
2032 + case PHY_STAT_EXT_INIT:
2033 + rtl8152_apply_firmware(tp, true);
2035 + data = ocp_reg_read(tp, 0xa466);
2037 + ocp_reg_write(tp, 0xa466, data);
2039 + data = ocp_reg_read(tp, 0xa468);
2040 + data &= ~(BIT(3) | BIT(1));
2041 + ocp_reg_write(tp, 0xa468, data);
2043 + case PHY_STAT_LAN_ON:
2044 + case PHY_STAT_PWRDN:
2046 + rtl8152_apply_firmware(tp, false);
2050 + data = r8152_mdio_read(tp, MII_BMCR);
2051 + if (data & BMCR_PDOWN) {
2052 + data &= ~BMCR_PDOWN;
2053 + r8152_mdio_write(tp, MII_BMCR, data);
2056 + /* disable ALDPS before updating the PHY parameters */
2057 + r8153_aldps_en(tp, false);
2059 + /* disable EEE before updating the PHY parameters */
2060 + rtl_eee_enable(tp, false);
2062 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2063 + WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
2065 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2066 + ocp_data |= PFM_PWM_SWITCH;
2067 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2069 + switch (tp->version) {
2071 + data = ocp_reg_read(tp, 0xbc08);
2072 + data |= BIT(3) | BIT(2);
2073 + ocp_reg_write(tp, 0xbc08, data);
2075 + data = sram_read(tp, 0x8fff);
2078 + sram_write(tp, 0x8fff, data);
2080 + data = ocp_reg_read(tp, 0xacda);
2082 + ocp_reg_write(tp, 0xacda, data);
2083 + data = ocp_reg_read(tp, 0xacde);
2085 + ocp_reg_write(tp, 0xacde, data);
2086 + ocp_reg_write(tp, 0xac8c, 0x0ffc);
2087 + ocp_reg_write(tp, 0xac46, 0xb7b4);
2088 + ocp_reg_write(tp, 0xac50, 0x0fbc);
2089 + ocp_reg_write(tp, 0xac3c, 0x9240);
2090 + ocp_reg_write(tp, 0xac4e, 0x0db4);
2091 + ocp_reg_write(tp, 0xacc6, 0x0707);
2092 + ocp_reg_write(tp, 0xacc8, 0xa0d3);
2093 + ocp_reg_write(tp, 0xad08, 0x0007);
2095 + ocp_reg_write(tp, 0xb87c, 0x8560);
2096 + ocp_reg_write(tp, 0xb87e, 0x19cc);
2097 + ocp_reg_write(tp, 0xb87c, 0x8562);
2098 + ocp_reg_write(tp, 0xb87e, 0x19cc);
2099 + ocp_reg_write(tp, 0xb87c, 0x8564);
2100 + ocp_reg_write(tp, 0xb87e, 0x19cc);
2101 + ocp_reg_write(tp, 0xb87c, 0x8566);
2102 + ocp_reg_write(tp, 0xb87e, 0x147d);
2103 + ocp_reg_write(tp, 0xb87c, 0x8568);
2104 + ocp_reg_write(tp, 0xb87e, 0x147d);
2105 + ocp_reg_write(tp, 0xb87c, 0x856a);
2106 + ocp_reg_write(tp, 0xb87e, 0x147d);
2107 + ocp_reg_write(tp, 0xb87c, 0x8ffe);
2108 + ocp_reg_write(tp, 0xb87e, 0x0907);
2109 + ocp_reg_write(tp, 0xb87c, 0x80d6);
2110 + ocp_reg_write(tp, 0xb87e, 0x2801);
2111 + ocp_reg_write(tp, 0xb87c, 0x80f2);
2112 + ocp_reg_write(tp, 0xb87e, 0x2801);
2113 + ocp_reg_write(tp, 0xb87c, 0x80f4);
2114 + ocp_reg_write(tp, 0xb87e, 0x6077);
2115 + ocp_reg_write(tp, 0xb506, 0x01e7);
2117 + ocp_reg_write(tp, 0xb87c, 0x8013);
2118 + ocp_reg_write(tp, 0xb87e, 0x0700);
2119 + ocp_reg_write(tp, 0xb87c, 0x8fb9);
2120 + ocp_reg_write(tp, 0xb87e, 0x2801);
2121 + ocp_reg_write(tp, 0xb87c, 0x8fba);
2122 + ocp_reg_write(tp, 0xb87e, 0x0100);
2123 + ocp_reg_write(tp, 0xb87c, 0x8fbc);
2124 + ocp_reg_write(tp, 0xb87e, 0x1900);
2125 + ocp_reg_write(tp, 0xb87c, 0x8fbe);
2126 + ocp_reg_write(tp, 0xb87e, 0xe100);
2127 + ocp_reg_write(tp, 0xb87c, 0x8fc0);
2128 + ocp_reg_write(tp, 0xb87e, 0x0800);
2129 + ocp_reg_write(tp, 0xb87c, 0x8fc2);
2130 + ocp_reg_write(tp, 0xb87e, 0xe500);
2131 + ocp_reg_write(tp, 0xb87c, 0x8fc4);
2132 + ocp_reg_write(tp, 0xb87e, 0x0f00);
2133 + ocp_reg_write(tp, 0xb87c, 0x8fc6);
2134 + ocp_reg_write(tp, 0xb87e, 0xf100);
2135 + ocp_reg_write(tp, 0xb87c, 0x8fc8);
2136 + ocp_reg_write(tp, 0xb87e, 0x0400);
2137 + ocp_reg_write(tp, 0xb87c, 0x8fca);
2138 + ocp_reg_write(tp, 0xb87e, 0xf300);
2139 + ocp_reg_write(tp, 0xb87c, 0x8fcc);
2140 + ocp_reg_write(tp, 0xb87e, 0xfd00);
2141 + ocp_reg_write(tp, 0xb87c, 0x8fce);
2142 + ocp_reg_write(tp, 0xb87e, 0xff00);
2143 + ocp_reg_write(tp, 0xb87c, 0x8fd0);
2144 + ocp_reg_write(tp, 0xb87e, 0xfb00);
2145 + ocp_reg_write(tp, 0xb87c, 0x8fd2);
2146 + ocp_reg_write(tp, 0xb87e, 0x0100);
2147 + ocp_reg_write(tp, 0xb87c, 0x8fd4);
2148 + ocp_reg_write(tp, 0xb87e, 0xf400);
2149 + ocp_reg_write(tp, 0xb87c, 0x8fd6);
2150 + ocp_reg_write(tp, 0xb87e, 0xff00);
2151 + ocp_reg_write(tp, 0xb87c, 0x8fd8);
2152 + ocp_reg_write(tp, 0xb87e, 0xf600);
2154 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
2155 + ocp_data |= EN_XG_LIP | EN_G_LIP;
2156 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
2157 + ocp_reg_write(tp, 0xb87c, 0x813d);
2158 + ocp_reg_write(tp, 0xb87e, 0x390e);
2159 + ocp_reg_write(tp, 0xb87c, 0x814f);
2160 + ocp_reg_write(tp, 0xb87e, 0x790e);
2161 + ocp_reg_write(tp, 0xb87c, 0x80b0);
2162 + ocp_reg_write(tp, 0xb87e, 0x0f31);
2163 + data = ocp_reg_read(tp, 0xbf4c);
2165 + ocp_reg_write(tp, 0xbf4c, data);
2166 + data = ocp_reg_read(tp, 0xbcca);
2167 + data |= BIT(9) | BIT(8);
2168 + ocp_reg_write(tp, 0xbcca, data);
2169 + ocp_reg_write(tp, 0xb87c, 0x8141);
2170 + ocp_reg_write(tp, 0xb87e, 0x320e);
2171 + ocp_reg_write(tp, 0xb87c, 0x8153);
2172 + ocp_reg_write(tp, 0xb87e, 0x720e);
2173 + ocp_reg_write(tp, 0xb87c, 0x8529);
2174 + ocp_reg_write(tp, 0xb87e, 0x050e);
2175 + data = ocp_reg_read(tp, OCP_EEE_CFG);
2176 + data &= ~CTAP_SHORT_EN;
2177 + ocp_reg_write(tp, OCP_EEE_CFG, data);
2179 + sram_write(tp, 0x816c, 0xc4a0);
2180 + sram_write(tp, 0x8170, 0xc4a0);
2181 + sram_write(tp, 0x8174, 0x04a0);
2182 + sram_write(tp, 0x8178, 0x04a0);
2183 + sram_write(tp, 0x817c, 0x0719);
2184 + sram_write(tp, 0x8ff4, 0x0400);
2185 + sram_write(tp, 0x8ff1, 0x0404);
2187 + ocp_reg_write(tp, 0xbf4a, 0x001b);
2188 + ocp_reg_write(tp, 0xb87c, 0x8033);
2189 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2190 + ocp_reg_write(tp, 0xb87c, 0x8037);
2191 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2192 + ocp_reg_write(tp, 0xb87c, 0x803b);
2193 + ocp_reg_write(tp, 0xb87e, 0xfc32);
2194 + ocp_reg_write(tp, 0xb87c, 0x803f);
2195 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2196 + ocp_reg_write(tp, 0xb87c, 0x8043);
2197 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2198 + ocp_reg_write(tp, 0xb87c, 0x8047);
2199 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2201 + ocp_reg_write(tp, 0xb87c, 0x8145);
2202 + ocp_reg_write(tp, 0xb87e, 0x370e);
2203 + ocp_reg_write(tp, 0xb87c, 0x8157);
2204 + ocp_reg_write(tp, 0xb87e, 0x770e);
2205 + ocp_reg_write(tp, 0xb87c, 0x8169);
2206 + ocp_reg_write(tp, 0xb87e, 0x0d0a);
2207 + ocp_reg_write(tp, 0xb87c, 0x817b);
2208 + ocp_reg_write(tp, 0xb87e, 0x1d0a);
2210 + data = sram_read(tp, 0x8217);
2213 + sram_write(tp, 0x8217, data);
2214 + data = sram_read(tp, 0x821a);
2217 + sram_write(tp, 0x821a, data);
2218 + sram_write(tp, 0x80da, 0x0403);
2219 + data = sram_read(tp, 0x80dc);
2222 + sram_write(tp, 0x80dc, data);
2223 + sram_write(tp, 0x80b3, 0x0384);
2224 + sram_write(tp, 0x80b7, 0x2007);
2225 + data = sram_read(tp, 0x80ba);
2228 + sram_write(tp, 0x80ba, data);
2229 + sram_write(tp, 0x80b5, 0xf009);
2230 + data = sram_read(tp, 0x80bd);
2233 + sram_write(tp, 0x80bd, data);
2234 + sram_write(tp, 0x80c7, 0xf083);
2235 + sram_write(tp, 0x80dd, 0x03f0);
2236 + data = sram_read(tp, 0x80df);
2239 + sram_write(tp, 0x80df, data);
2240 + sram_write(tp, 0x80cb, 0x2007);
2241 + data = sram_read(tp, 0x80ce);
2244 + sram_write(tp, 0x80ce, data);
2245 + sram_write(tp, 0x80c9, 0x8009);
2246 + data = sram_read(tp, 0x80d1);
2249 + sram_write(tp, 0x80d1, data);
2250 + sram_write(tp, 0x80a3, 0x200a);
2251 + sram_write(tp, 0x80a5, 0xf0ad);
2252 + sram_write(tp, 0x809f, 0x6073);
2253 + sram_write(tp, 0x80a1, 0x000b);
2254 + data = sram_read(tp, 0x80a9);
2257 + sram_write(tp, 0x80a9, data);
2259 + if (rtl_phy_patch_request(tp, true, true))
2262 + data = ocp_reg_read(tp, 0xb896);
2264 + ocp_reg_write(tp, 0xb896, data);
2265 + data = ocp_reg_read(tp, 0xb892);
2267 + ocp_reg_write(tp, 0xb892, data);
2268 + ocp_reg_write(tp, 0xb88e, 0xc23e);
2269 + ocp_reg_write(tp, 0xb890, 0x0000);
2270 + ocp_reg_write(tp, 0xb88e, 0xc240);
2271 + ocp_reg_write(tp, 0xb890, 0x0103);
2272 + ocp_reg_write(tp, 0xb88e, 0xc242);
2273 + ocp_reg_write(tp, 0xb890, 0x0507);
2274 + ocp_reg_write(tp, 0xb88e, 0xc244);
2275 + ocp_reg_write(tp, 0xb890, 0x090b);
2276 + ocp_reg_write(tp, 0xb88e, 0xc246);
2277 + ocp_reg_write(tp, 0xb890, 0x0c0e);
2278 + ocp_reg_write(tp, 0xb88e, 0xc248);
2279 + ocp_reg_write(tp, 0xb890, 0x1012);
2280 + ocp_reg_write(tp, 0xb88e, 0xc24a);
2281 + ocp_reg_write(tp, 0xb890, 0x1416);
2282 + data = ocp_reg_read(tp, 0xb896);
2284 + ocp_reg_write(tp, 0xb896, data);
2286 + rtl_phy_patch_request(tp, false, true);
2288 + data = ocp_reg_read(tp, 0xa86a);
2290 + ocp_reg_write(tp, 0xa86a, data);
2291 + data = ocp_reg_read(tp, 0xa6f0);
2293 + ocp_reg_write(tp, 0xa6f0, data);
2295 + ocp_reg_write(tp, 0xbfa0, 0xd70d);
2296 + ocp_reg_write(tp, 0xbfa2, 0x4100);
2297 + ocp_reg_write(tp, 0xbfa4, 0xe868);
2298 + ocp_reg_write(tp, 0xbfa6, 0xdc59);
2299 + ocp_reg_write(tp, 0xb54c, 0x3c18);
2300 + data = ocp_reg_read(tp, 0xbfa4);
2302 + ocp_reg_write(tp, 0xbfa4, data);
2303 + data = sram_read(tp, 0x817d);
2305 + sram_write(tp, 0x817d, data);
2309 + data = ocp_reg_read(tp, 0xac46);
2312 + ocp_reg_write(tp, 0xac46, data);
2313 + data = ocp_reg_read(tp, 0xad30);
2316 + ocp_reg_write(tp, 0xad30, data);
2319 + /* EEE parameter */
2320 + ocp_reg_write(tp, 0xb87c, 0x80f5);
2321 + ocp_reg_write(tp, 0xb87e, 0x760e);
2322 + ocp_reg_write(tp, 0xb87c, 0x8107);
2323 + ocp_reg_write(tp, 0xb87e, 0x360e);
2324 + ocp_reg_write(tp, 0xb87c, 0x8551);
2325 + data = ocp_reg_read(tp, 0xb87e);
2328 + ocp_reg_write(tp, 0xb87e, data);
2330 + /* ADC_PGA parameter */
2331 + data = ocp_reg_read(tp, 0xbf00);
2334 + ocp_reg_write(tp, 0xbf00, data);
2335 + data = ocp_reg_read(tp, 0xbf46);
2338 + ocp_reg_write(tp, 0xbf46, data);
2340 + /* Green Table-PGA, 1G full viterbi */
2341 + sram_write(tp, 0x8044, 0x2417);
2342 + sram_write(tp, 0x804a, 0x2417);
2343 + sram_write(tp, 0x8050, 0x2417);
2344 + sram_write(tp, 0x8056, 0x2417);
2345 + sram_write(tp, 0x805c, 0x2417);
2346 + sram_write(tp, 0x8062, 0x2417);
2347 + sram_write(tp, 0x8068, 0x2417);
2348 + sram_write(tp, 0x806e, 0x2417);
2349 + sram_write(tp, 0x8074, 0x2417);
2350 + sram_write(tp, 0x807a, 0x2417);
2353 + data = ocp_reg_read(tp, 0xbf84);
2356 + ocp_reg_write(tp, 0xbf84, data);
2362 + if (rtl_phy_patch_request(tp, true, true))
2365 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2366 + ocp_data |= EEE_SPDWN_EN;
2367 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2369 + data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2370 + data &= ~(EN_EEE_100 | EN_EEE_1000);
2371 + data |= EN_10M_CLKDIV;
2372 + ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2373 + tp->ups_info._10m_ckdiv = true;
2374 + tp->ups_info.eee_plloff_100 = false;
2375 + tp->ups_info.eee_plloff_giga = false;
2377 + data = ocp_reg_read(tp, OCP_POWER_CFG);
2378 + data &= ~EEE_CLKDIV_EN;
2379 + ocp_reg_write(tp, OCP_POWER_CFG, data);
2380 + tp->ups_info.eee_ckdiv = false;
2382 + rtl_phy_patch_request(tp, false, true);
2384 + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
2386 + data = ocp_reg_read(tp, 0xa428);
2388 + ocp_reg_write(tp, 0xa428, data);
2389 + data = ocp_reg_read(tp, 0xa5ea);
2391 + ocp_reg_write(tp, 0xa5ea, data);
2392 + tp->ups_info.lite_mode = 0;
2395 + rtl_eee_enable(tp, true);
2397 + r8153_aldps_en(tp, true);
2398 + r8152b_enable_fc(tp);
2399 + r8153_u2p3en(tp, true);
2401 + set_bit(PHY_RESET, &tp->flags);
2404 +static void r8156_init(struct r8152 *tp)
2410 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2413 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
2414 + ocp_data &= ~EN_ALL_SPEED;
2415 + ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
2417 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
2419 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
2420 + ocp_data |= BYPASS_MAC_RESET;
2421 + ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
2423 + r8153b_u1u2en(tp, false);
2425 + for (i = 0; i < 500; i++) {
2426 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2431 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2435 + data = r8153_phy_status(tp, 0);
2436 + if (data == PHY_STAT_EXT_INIT) {
2437 + data = ocp_reg_read(tp, 0xa468);
2438 + data &= ~(BIT(3) | BIT(1));
2439 + ocp_reg_write(tp, 0xa468, data);
2442 + data = r8152_mdio_read(tp, MII_BMCR);
2443 + if (data & BMCR_PDOWN) {
2444 + data &= ~BMCR_PDOWN;
2445 + r8152_mdio_write(tp, MII_BMCR, data);
2448 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2449 + WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
2451 + r8153_u2p3en(tp, false);
2453 + /* MSC timer = 0xfff * 8ms = 32760 ms */
2454 + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
2456 + /* U1/U2/L1 idle timer. 500 us */
2457 + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
2459 + r8153b_power_cut_en(tp, false);
2460 + r8156_ups_en(tp, false);
2461 + r8153_queue_wake(tp, false);
2462 + rtl_runtime_suspend_enable(tp, false);
2464 + if (tp->udev->speed >= USB_SPEED_SUPER)
2465 + r8153b_u1u2en(tp, true);
2467 + usb_enable_lpm(tp->udev);
2469 + r8156_mac_clk_spd(tp, true);
2471 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
2472 + ocp_data &= ~PLA_MCU_SPDWN_EN;
2473 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
2475 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
2476 + if (rtl8152_get_speed(tp) & LINK_STATUS)
2477 + ocp_data |= CUR_LINK_OK;
2479 + ocp_data &= ~CUR_LINK_OK;
2480 + ocp_data |= POLL_LINK_CHG;
2481 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
2483 + set_bit(GREEN_ETHERNET, &tp->flags);
2485 + /* rx aggregation */
2486 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2487 + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2488 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2490 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
2491 + ocp_data |= ACT_ODMA;
2492 + ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
2494 + rtl_tally_reset(tp);
2496 + tp->coalesce = 15000; /* 15 us */
2499 +static void r8156b_init(struct r8152 *tp)
2505 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2508 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
2509 + ocp_data &= ~EN_ALL_SPEED;
2510 + ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
2512 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
2514 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
2515 + ocp_data |= BYPASS_MAC_RESET;
2516 + ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
2518 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2519 + ocp_data |= RX_DETECT8;
2520 + ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2522 + r8153b_u1u2en(tp, false);
2524 + switch (tp->version) {
2527 + r8156b_wait_loading_flash(tp);
2533 + for (i = 0; i < 500; i++) {
2534 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2539 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2543 + data = r8153_phy_status(tp, 0);
2544 + if (data == PHY_STAT_EXT_INIT) {
2545 + data = ocp_reg_read(tp, 0xa468);
2546 + data &= ~(BIT(3) | BIT(1));
2547 + ocp_reg_write(tp, 0xa468, data);
2549 + data = ocp_reg_read(tp, 0xa466);
2551 + ocp_reg_write(tp, 0xa466, data);
2554 + data = r8152_mdio_read(tp, MII_BMCR);
2555 + if (data & BMCR_PDOWN) {
2556 + data &= ~BMCR_PDOWN;
2557 + r8152_mdio_write(tp, MII_BMCR, data);
2560 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2562 + r8153_u2p3en(tp, false);
2564 + /* MSC timer = 0xfff * 8ms = 32760 ms */
2565 + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
2567 + /* U1/U2/L1 idle timer. 500 us */
2568 + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
2570 + r8153b_power_cut_en(tp, false);
2571 + r8156_ups_en(tp, false);
2572 + r8153_queue_wake(tp, false);
2573 + rtl_runtime_suspend_enable(tp, false);
2575 + if (tp->udev->speed >= USB_SPEED_SUPER)
2576 + r8153b_u1u2en(tp, true);
2578 + usb_enable_lpm(tp->udev);
2580 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
2581 + ocp_data &= ~SLOT_EN;
2582 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2584 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2585 + ocp_data |= FLOW_CTRL_EN;
2586 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2588 + /* enable fc timer and set timer to 600 ms. */
2589 + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
2590 + CTRL_TIMER_EN | (600 / 8));
2592 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
2593 + if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
2594 + ocp_data |= FLOW_CTRL_PATCH_2;
2595 + ocp_data &= ~AUTO_SPEEDUP;
2596 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
2598 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2599 + ocp_data |= FC_PATCH_TASK;
2600 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2602 + r8156_mac_clk_spd(tp, true);
2604 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
2605 + ocp_data &= ~PLA_MCU_SPDWN_EN;
2606 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
2608 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
2609 + if (rtl8152_get_speed(tp) & LINK_STATUS)
2610 + ocp_data |= CUR_LINK_OK;
2612 + ocp_data &= ~CUR_LINK_OK;
2613 + ocp_data |= POLL_LINK_CHG;
2614 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
2616 + set_bit(GREEN_ETHERNET, &tp->flags);
2618 + /* rx aggregation */
2619 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2620 + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2621 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2623 + rtl_tally_reset(tp);
2625 + tp->coalesce = 15000; /* 15 us */
2628 static int rtl8152_pre_reset(struct usb_interface *intf)
2630 struct r8152 *tp = usb_get_intfdata(intf);
2631 @@ -5992,6 +7924,22 @@ int rtl8152_get_link_ksettings(struct ne
2633 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2635 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2636 + cmd->link_modes.supported, tp->support_2500full);
2638 + if (tp->support_2500full) {
2639 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2640 + cmd->link_modes.advertising,
2641 + ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
2643 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2644 + cmd->link_modes.lp_advertising,
2645 + ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
2647 + if (is_speed_2500(rtl8152_get_speed(tp)))
2648 + cmd->base.speed = SPEED_2500;
2651 mutex_unlock(&tp->control);
2653 usb_autopm_put_interface(tp->intf);
2654 @@ -6035,6 +7983,10 @@ static int rtl8152_set_link_ksettings(st
2655 cmd->link_modes.advertising))
2656 advertising |= RTL_ADVERTISED_1000_FULL;
2658 + if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2659 + cmd->link_modes.advertising))
2660 + advertising |= RTL_ADVERTISED_2500_FULL;
2662 mutex_lock(&tp->control);
2664 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
2665 @@ -6624,6 +8576,67 @@ static int rtl_ops_init(struct r8152 *tp
2666 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2670 + tp->eee_en = true;
2671 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2674 + ops->init = r8156_init;
2675 + ops->enable = rtl8156_enable;
2676 + ops->disable = rtl8153_disable;
2677 + ops->up = rtl8156_up;
2678 + ops->down = rtl8156_down;
2679 + ops->unload = rtl8153_unload;
2680 + ops->eee_get = r8153_get_eee;
2681 + ops->eee_set = r8152_set_eee;
2682 + ops->in_nway = rtl8153_in_nway;
2683 + ops->hw_phy_cfg = r8156_hw_phy_cfg;
2684 + ops->autosuspend_en = rtl8156_runtime_enable;
2685 + ops->change_mtu = rtl8156_change_mtu;
2686 + tp->rx_buf_sz = 48 * 1024;
2687 + tp->support_2500full = 1;
2692 + tp->support_2500full = 1;
2695 + tp->eee_en = true;
2696 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2697 + ops->init = r8156b_init;
2698 + ops->enable = rtl8156b_enable;
2699 + ops->disable = rtl8153_disable;
2700 + ops->up = rtl8156_up;
2701 + ops->down = rtl8156_down;
2702 + ops->unload = rtl8153_unload;
2703 + ops->eee_get = r8153_get_eee;
2704 + ops->eee_set = r8152_set_eee;
2705 + ops->in_nway = rtl8153_in_nway;
2706 + ops->hw_phy_cfg = r8156b_hw_phy_cfg;
2707 + ops->autosuspend_en = rtl8156_runtime_enable;
2708 + ops->change_mtu = rtl8156_change_mtu;
2709 + tp->rx_buf_sz = 48 * 1024;
2713 + ops->init = r8153c_init;
2714 + ops->enable = rtl8153_enable;
2715 + ops->disable = rtl8153_disable;
2716 + ops->up = rtl8153c_up;
2717 + ops->down = rtl8153b_down;
2718 + ops->unload = rtl8153_unload;
2719 + ops->eee_get = r8153_get_eee;
2720 + ops->eee_set = r8152_set_eee;
2721 + ops->in_nway = rtl8153_in_nway;
2722 + ops->hw_phy_cfg = r8153c_hw_phy_cfg;
2723 + ops->autosuspend_en = rtl8153c_runtime_enable;
2724 + ops->change_mtu = rtl8153c_change_mtu;
2725 + tp->rx_buf_sz = 32 * 1024;
2726 + tp->eee_en = true;
2727 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2732 dev_err(&tp->intf->dev, "Unknown Device\n");
2733 @@ -6637,11 +8650,13 @@ static int rtl_ops_init(struct r8152 *tp
2734 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
2735 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
2736 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
2737 +#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
2739 MODULE_FIRMWARE(FIRMWARE_8153A_2);
2740 MODULE_FIRMWARE(FIRMWARE_8153A_3);
2741 MODULE_FIRMWARE(FIRMWARE_8153A_4);
2742 MODULE_FIRMWARE(FIRMWARE_8153B_2);
2743 +MODULE_FIRMWARE(FIRMWARE_8153C_1);
2745 static int rtl_fw_init(struct r8152 *tp)
2747 @@ -6667,6 +8682,11 @@ static int rtl_fw_init(struct r8152 *tp)
2748 rtl_fw->pre_fw = r8153b_pre_firmware_1;
2749 rtl_fw->post_fw = r8153b_post_firmware_1;
2752 + rtl_fw->fw_name = FIRMWARE_8153C_1;
2753 + rtl_fw->pre_fw = r8153b_pre_firmware_1;
2754 + rtl_fw->post_fw = r8153c_post_firmware_1;
2759 @@ -6722,6 +8742,27 @@ u8 rtl8152_get_version(struct usb_interf
2761 version = RTL_VER_09;
2764 + version = RTL_TEST_01;
2767 + version = RTL_VER_10;
2770 + version = RTL_VER_11;
2773 + version = RTL_VER_12;
2776 + version = RTL_VER_13;
2779 + version = RTL_VER_14;
2782 + version = RTL_VER_15;
2785 version = RTL_VER_UNKNOWN;
2786 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
2787 @@ -6834,12 +8875,29 @@ static int rtl8152_probe(struct usb_inte
2788 /* MTU range: 68 - 1500 or 9194 */
2789 netdev->min_mtu = ETH_MIN_MTU;
2790 switch (tp->version) {
2798 + netdev->max_mtu = size_to_mtu(9 * 1024);
2802 + netdev->max_mtu = size_to_mtu(15 * 1024);
2807 + netdev->max_mtu = size_to_mtu(16 * 1024);
2811 - netdev->max_mtu = ETH_DATA_LEN;
2815 - netdev->max_mtu = size_to_mtu(9 * 1024);
2816 + netdev->max_mtu = ETH_DATA_LEN;
2820 @@ -6855,7 +8913,13 @@ static int rtl8152_probe(struct usb_inte
2821 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
2822 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
2823 if (tp->mii.supports_gmii) {
2824 - tp->speed = SPEED_1000;
2825 + if (tp->support_2500full &&
2826 + tp->udev->speed >= USB_SPEED_SUPER) {
2827 + tp->speed = SPEED_2500;
2828 + tp->advertising |= RTL_ADVERTISED_2500_FULL;
2830 + tp->speed = SPEED_1000;
2832 tp->advertising |= RTL_ADVERTISED_1000_FULL;
2834 tp->duplex = DUPLEX_FULL;
2835 @@ -6879,7 +8943,11 @@ static int rtl8152_probe(struct usb_inte
2836 set_ethernet_addr(tp);
2838 usb_set_intfdata(intf, tp);
2839 - netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
2841 + if (tp->support_2500full)
2842 + netif_napi_add(netdev, &tp->napi, r8152_poll, 256);
2844 + netif_napi_add(netdev, &tp->napi, r8152_poll, 64);
2846 ret = register_netdev(netdev);
2848 @@ -6915,7 +8983,8 @@ static void rtl8152_disconnect(struct us
2849 unregister_netdev(tp->netdev);
2850 tasklet_kill(&tp->tx_tl);
2851 cancel_delayed_work_sync(&tp->hw_phy_work);
2852 - tp->rtl_ops.unload(tp);
2853 + if (tp->rtl_ops.unload)
2854 + tp->rtl_ops.unload(tp);
2855 rtl8152_release_firmware(tp);
2856 free_netdev(tp->netdev);
2858 @@ -6935,13 +9004,28 @@ static void rtl8152_disconnect(struct us
2859 .idProduct = (prod), \
2860 .bInterfaceClass = USB_CLASS_COMM, \
2861 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
2862 + .bInterfaceProtocol = USB_CDC_PROTO_NONE \
2865 + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
2866 + USB_DEVICE_ID_MATCH_DEVICE, \
2867 + .idVendor = (vend), \
2868 + .idProduct = (prod), \
2869 + .bInterfaceClass = USB_CLASS_COMM, \
2870 + .bInterfaceSubClass = USB_CDC_SUBCLASS_NCM, \
2871 .bInterfaceProtocol = USB_CDC_PROTO_NONE
2873 /* table of devices that work with this driver */
2874 static const struct usb_device_id rtl8152_table[] = {
2876 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
2877 + {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053)},
2878 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
2879 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
2880 + {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155)},
2881 + {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156)},
2884 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
2885 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
2886 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},