1 From: Russell King <rmk+kernel@armlinux.org.uk>
2 Bcc: linux@mail.armlinux.org.uk
3 Cc: linux-i2c@vger.kernel.org
4 Subject: [PATCH 05/17] i2c: pxa: re-arrange register field definitions
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10 Arrange the register field definitions to be grouped together, rather
11 than the Armada-3700 definitions being separated from the rest of the
14 Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
16 drivers/i2c/busses/i2c-pxa.c | 113 ++++++++++++++++-------------------
17 1 file changed, 53 insertions(+), 60 deletions(-)
19 --- a/drivers/i2c/busses/i2c-pxa.c
20 +++ b/drivers/i2c/busses/i2c-pxa.c
22 #include <linux/platform_data/i2c-pxa.h>
23 #include <linux/slab.h>
25 +/* I2C register field definitions */
26 +#define ICR_START (1 << 0) /* start bit */
27 +#define ICR_STOP (1 << 1) /* stop bit */
28 +#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
29 +#define ICR_TB (1 << 3) /* transfer byte bit */
30 +#define ICR_MA (1 << 4) /* master abort */
31 +#define ICR_SCLE (1 << 5) /* master clock enable */
32 +#define ICR_IUE (1 << 6) /* unit enable */
33 +#define ICR_GCD (1 << 7) /* general call disable */
34 +#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
35 +#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
36 +#define ICR_BEIE (1 << 10) /* enable bus error ints */
37 +#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
38 +#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
39 +#define ICR_SADIE (1 << 13) /* slave address detected int enable */
40 +#define ICR_UR (1 << 14) /* unit reset */
41 +#define ICR_FM (1 << 15) /* fast mode */
42 +#define ICR_HS (1 << 16) /* High Speed mode */
43 +#define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
44 +#define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
45 +#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
47 +#define ISR_RWM (1 << 0) /* read/write mode */
48 +#define ISR_ACKNAK (1 << 1) /* ack/nak status */
49 +#define ISR_UB (1 << 2) /* unit busy */
50 +#define ISR_IBB (1 << 3) /* bus busy */
51 +#define ISR_SSD (1 << 4) /* slave stop detected */
52 +#define ISR_ALD (1 << 5) /* arbitration loss detected */
53 +#define ISR_ITE (1 << 6) /* tx buffer empty */
54 +#define ISR_IRF (1 << 7) /* rx buffer full */
55 +#define ISR_GCAD (1 << 8) /* general call address detected */
56 +#define ISR_SAD (1 << 9) /* slave address detected */
57 +#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
59 +#define ILCR_SLV_SHIFT 0
60 +#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
61 +#define ILCR_FLV_SHIFT 9
62 +#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
63 +#define ILCR_HLVL_SHIFT 18
64 +#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
65 +#define ILCR_HLVH_SHIFT 27
66 +#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
68 +#define IWCR_CNT_SHIFT 0
69 +#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
70 +#define IWCR_HS_CNT1_SHIFT 5
71 +#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
72 +#define IWCR_HS_CNT2_SHIFT 10
73 +#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
75 struct pxa_reg_layout {
78 @@ -53,12 +103,7 @@ enum pxa_i2c_types {
82 -#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
83 -#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
86 - * I2C registers definitions
88 +/* I2C register layout definitions */
89 static struct pxa_reg_layout pxa_reg_layout[] = {
92 @@ -96,8 +141,8 @@ static struct pxa_reg_layout pxa_reg_lay
96 - .fm = ICR_BUSMODE_FM,
97 - .hs = ICR_BUSMODE_HS,
103 @@ -111,58 +156,6 @@ static const struct platform_device_id i
105 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
108 - * I2C bit definitions
111 -#define ICR_START (1 << 0) /* start bit */
112 -#define ICR_STOP (1 << 1) /* stop bit */
113 -#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
114 -#define ICR_TB (1 << 3) /* transfer byte bit */
115 -#define ICR_MA (1 << 4) /* master abort */
116 -#define ICR_SCLE (1 << 5) /* master clock enable */
117 -#define ICR_IUE (1 << 6) /* unit enable */
118 -#define ICR_GCD (1 << 7) /* general call disable */
119 -#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
120 -#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
121 -#define ICR_BEIE (1 << 10) /* enable bus error ints */
122 -#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
123 -#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
124 -#define ICR_SADIE (1 << 13) /* slave address detected int enable */
125 -#define ICR_UR (1 << 14) /* unit reset */
126 -#define ICR_FM (1 << 15) /* fast mode */
127 -#define ICR_HS (1 << 16) /* High Speed mode */
128 -#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
130 -#define ISR_RWM (1 << 0) /* read/write mode */
131 -#define ISR_ACKNAK (1 << 1) /* ack/nak status */
132 -#define ISR_UB (1 << 2) /* unit busy */
133 -#define ISR_IBB (1 << 3) /* bus busy */
134 -#define ISR_SSD (1 << 4) /* slave stop detected */
135 -#define ISR_ALD (1 << 5) /* arbitration loss detected */
136 -#define ISR_ITE (1 << 6) /* tx buffer empty */
137 -#define ISR_IRF (1 << 7) /* rx buffer full */
138 -#define ISR_GCAD (1 << 8) /* general call address detected */
139 -#define ISR_SAD (1 << 9) /* slave address detected */
140 -#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
142 -/* bit field shift & mask */
143 -#define ILCR_SLV_SHIFT 0
144 -#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
145 -#define ILCR_FLV_SHIFT 9
146 -#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
147 -#define ILCR_HLVL_SHIFT 18
148 -#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
149 -#define ILCR_HLVH_SHIFT 27
150 -#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
152 -#define IWCR_CNT_SHIFT 0
153 -#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
154 -#define IWCR_HS_CNT1_SHIFT 5
155 -#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
156 -#define IWCR_HS_CNT2_SHIFT 10
157 -#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
161 wait_queue_head_t wait;