1 From d2213db3f49bce8e7a87c8de05b9a091f78f654e Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Tue, 14 Nov 2023 15:08:41 +0100
4 Subject: [PATCH 1/3] net: phy: aquantia: move to separate directory
6 Move aquantia PHY driver to separate driectory in preparation for
7 firmware loading support to keep things tidy.
9 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
13 drivers/net/phy/Kconfig | 5 +----
14 drivers/net/phy/Makefile | 6 +-----
15 drivers/net/phy/aquantia/Kconfig | 5 +++++
16 drivers/net/phy/aquantia/Makefile | 6 ++++++
17 drivers/net/phy/{ => aquantia}/aquantia.h | 0
18 drivers/net/phy/{ => aquantia}/aquantia_hwmon.c | 0
19 drivers/net/phy/{ => aquantia}/aquantia_main.c | 0
20 7 files changed, 13 insertions(+), 9 deletions(-)
21 create mode 100644 drivers/net/phy/aquantia/Kconfig
22 create mode 100644 drivers/net/phy/aquantia/Makefile
23 rename drivers/net/phy/{ => aquantia}/aquantia.h (100%)
24 rename drivers/net/phy/{ => aquantia}/aquantia_hwmon.c (100%)
25 rename drivers/net/phy/{ => aquantia}/aquantia_main.c (100%)
27 --- a/drivers/net/phy/Kconfig
28 +++ b/drivers/net/phy/Kconfig
29 @@ -90,10 +90,7 @@ config ADIN1100_PHY
30 Currently supports the:
31 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
34 - tristate "Aquantia PHYs"
36 - Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
37 +source "drivers/net/phy/aquantia/Kconfig"
41 --- a/drivers/net/phy/Makefile
42 +++ b/drivers/net/phy/Makefile
43 @@ -33,11 +33,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
44 obj-$(CONFIG_ADIN_PHY) += adin.o
45 obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
46 obj-$(CONFIG_AMD_PHY) += amd.o
47 -aquantia-objs += aquantia_main.o
49 -aquantia-objs += aquantia_hwmon.o
51 -obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
52 +obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
53 obj-$(CONFIG_AT803X_PHY) += at803x.o
54 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
55 obj-$(CONFIG_BCM54140_PHY) += bcm54140.o
57 +++ b/drivers/net/phy/aquantia/Kconfig
59 +# SPDX-License-Identifier: GPL-2.0-only
61 + tristate "Aquantia PHYs"
63 + Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
65 +++ b/drivers/net/phy/aquantia/Makefile
67 +# SPDX-License-Identifier: GPL-2.0
68 +aquantia-objs += aquantia_main.o
70 +aquantia-objs += aquantia_hwmon.o
72 +obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
73 --- a/drivers/net/phy/aquantia.h
76 -/* SPDX-License-Identifier: GPL-2.0 */
77 -/* HWMON driver for Aquantia PHY
79 - * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
80 - * Author: Andrew Lunn <andrew@lunn.ch>
81 - * Author: Heiner Kallweit <hkallweit1@gmail.com>
84 -#include <linux/device.h>
85 -#include <linux/phy.h>
87 -#if IS_REACHABLE(CONFIG_HWMON)
88 -int aqr_hwmon_probe(struct phy_device *phydev);
90 -static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
93 +++ b/drivers/net/phy/aquantia/aquantia.h
95 +/* SPDX-License-Identifier: GPL-2.0 */
96 +/* HWMON driver for Aquantia PHY
98 + * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
99 + * Author: Andrew Lunn <andrew@lunn.ch>
100 + * Author: Heiner Kallweit <hkallweit1@gmail.com>
103 +#include <linux/device.h>
104 +#include <linux/phy.h>
106 +#if IS_REACHABLE(CONFIG_HWMON)
107 +int aqr_hwmon_probe(struct phy_device *phydev);
109 +static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
112 +++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
114 +// SPDX-License-Identifier: GPL-2.0
115 +/* HWMON driver for Aquantia PHY
117 + * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
118 + * Author: Andrew Lunn <andrew@lunn.ch>
119 + * Author: Heiner Kallweit <hkallweit1@gmail.com>
122 +#include <linux/phy.h>
123 +#include <linux/device.h>
124 +#include <linux/ctype.h>
125 +#include <linux/hwmon.h>
127 +#include "aquantia.h"
129 +/* Vendor specific 1, MDIO_MMD_VEND2 */
130 +#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
131 +#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
132 +#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
133 +#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
134 +#define VEND1_THERMAL_STAT1 0xc820
135 +#define VEND1_THERMAL_STAT2 0xc821
136 +#define VEND1_THERMAL_STAT2_VALID BIT(0)
137 +#define VEND1_GENERAL_STAT1 0xc830
138 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
139 +#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
140 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
141 +#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
143 +#if IS_REACHABLE(CONFIG_HWMON)
145 +static umode_t aqr_hwmon_is_visible(const void *data,
146 + enum hwmon_sensor_types type,
147 + u32 attr, int channel)
149 + if (type != hwmon_temp)
153 + case hwmon_temp_input:
154 + case hwmon_temp_min_alarm:
155 + case hwmon_temp_max_alarm:
156 + case hwmon_temp_lcrit_alarm:
157 + case hwmon_temp_crit_alarm:
159 + case hwmon_temp_min:
160 + case hwmon_temp_max:
161 + case hwmon_temp_lcrit:
162 + case hwmon_temp_crit:
169 +static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
171 + int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
176 + /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
177 + *value = (s16)temp * 1000 / 256;
182 +static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
186 + if (value >= 128000 || value < -128000)
189 + temp = value * 256 / 1000;
191 + /* temp is in s16 range and we're interested in lower 16 bits only */
192 + return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
195 +static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
197 + int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
202 + return !!(val & bit);
205 +static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
207 + int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
217 +static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
218 + u32 attr, int channel, long *value)
220 + struct phy_device *phydev = dev_get_drvdata(dev);
223 + if (type != hwmon_temp)
224 + return -EOPNOTSUPP;
227 + case hwmon_temp_input:
228 + reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
229 + VEND1_THERMAL_STAT2_VALID);
235 + return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
237 + case hwmon_temp_lcrit:
238 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
240 + case hwmon_temp_min:
241 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
243 + case hwmon_temp_max:
244 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
246 + case hwmon_temp_crit:
247 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
249 + case hwmon_temp_lcrit_alarm:
250 + return aqr_hwmon_status1(phydev,
251 + VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
253 + case hwmon_temp_min_alarm:
254 + return aqr_hwmon_status1(phydev,
255 + VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
257 + case hwmon_temp_max_alarm:
258 + return aqr_hwmon_status1(phydev,
259 + VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
261 + case hwmon_temp_crit_alarm:
262 + return aqr_hwmon_status1(phydev,
263 + VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
266 + return -EOPNOTSUPP;
270 +static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
271 + u32 attr, int channel, long value)
273 + struct phy_device *phydev = dev_get_drvdata(dev);
275 + if (type != hwmon_temp)
276 + return -EOPNOTSUPP;
279 + case hwmon_temp_lcrit:
280 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
282 + case hwmon_temp_min:
283 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
285 + case hwmon_temp_max:
286 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
288 + case hwmon_temp_crit:
289 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
292 + return -EOPNOTSUPP;
296 +static const struct hwmon_ops aqr_hwmon_ops = {
297 + .is_visible = aqr_hwmon_is_visible,
298 + .read = aqr_hwmon_read,
299 + .write = aqr_hwmon_write,
302 +static u32 aqr_hwmon_chip_config[] = {
303 + HWMON_C_REGISTER_TZ,
307 +static const struct hwmon_channel_info aqr_hwmon_chip = {
308 + .type = hwmon_chip,
309 + .config = aqr_hwmon_chip_config,
312 +static u32 aqr_hwmon_temp_config[] = {
314 + HWMON_T_MAX | HWMON_T_MIN |
315 + HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
316 + HWMON_T_CRIT | HWMON_T_LCRIT |
317 + HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
321 +static const struct hwmon_channel_info aqr_hwmon_temp = {
322 + .type = hwmon_temp,
323 + .config = aqr_hwmon_temp_config,
326 +static const struct hwmon_channel_info *aqr_hwmon_info[] = {
332 +static const struct hwmon_chip_info aqr_hwmon_chip_info = {
333 + .ops = &aqr_hwmon_ops,
334 + .info = aqr_hwmon_info,
337 +int aqr_hwmon_probe(struct phy_device *phydev)
339 + struct device *dev = &phydev->mdio.dev;
340 + struct device *hwmon_dev;
344 + hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
348 + for (i = j = 0; hwmon_name[i]; i++) {
349 + if (isalnum(hwmon_name[i])) {
351 + hwmon_name[j] = hwmon_name[i];
355 + hwmon_name[j] = '\0';
357 + hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
358 + phydev, &aqr_hwmon_chip_info, NULL);
360 + return PTR_ERR_OR_ZERO(hwmon_dev);
365 +++ b/drivers/net/phy/aquantia/aquantia_main.c
367 +// SPDX-License-Identifier: GPL-2.0
369 + * Driver for Aquantia PHY
371 + * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
373 + * Copyright 2015 Freescale Semiconductor, Inc.
376 +#include <linux/kernel.h>
377 +#include <linux/module.h>
378 +#include <linux/delay.h>
379 +#include <linux/bitfield.h>
380 +#include <linux/phy.h>
382 +#include "aquantia.h"
384 +#define PHY_ID_AQ1202 0x03a1b445
385 +#define PHY_ID_AQ2104 0x03a1b460
386 +#define PHY_ID_AQR105 0x03a1b4a2
387 +#define PHY_ID_AQR106 0x03a1b4d0
388 +#define PHY_ID_AQR107 0x03a1b4e0
389 +#define PHY_ID_AQCS109 0x03a1b5c2
390 +#define PHY_ID_AQR405 0x03a1b4b0
391 +#define PHY_ID_AQR113C 0x31c31c12
393 +#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
394 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
395 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
396 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
397 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
398 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
399 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
400 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
401 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
402 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
404 +#define MDIO_AN_VEND_PROV 0xc400
405 +#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
406 +#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
407 +#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
408 +#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
409 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
410 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
411 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
413 +#define MDIO_AN_TX_VEND_STATUS1 0xc800
414 +#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
415 +#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
416 +#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
417 +#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
418 +#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
419 +#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
420 +#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
421 +#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
423 +#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
424 +#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
426 +#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
427 +#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
429 +#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
430 +#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
432 +#define MDIO_AN_RX_LP_STAT1 0xe820
433 +#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
434 +#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
435 +#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
436 +#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
437 +#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
439 +#define MDIO_AN_RX_LP_STAT4 0xe823
440 +#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
441 +#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
443 +#define MDIO_AN_RX_VEND_STAT3 0xe832
444 +#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
446 +/* MDIO_MMD_C22EXT */
447 +#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
448 +#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
449 +#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
450 +#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
451 +#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
452 +#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
453 +#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
454 +#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
455 +#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
456 +#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
458 +/* Vendor specific 1, MDIO_MMD_VEND1 */
459 +#define VEND1_GLOBAL_FW_ID 0x0020
460 +#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
461 +#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
463 +#define VEND1_GLOBAL_GEN_STAT2 0xc831
464 +#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
466 +/* The following registers all have similar layouts; first the registers... */
467 +#define VEND1_GLOBAL_CFG_10M 0x0310
468 +#define VEND1_GLOBAL_CFG_100M 0x031b
469 +#define VEND1_GLOBAL_CFG_1G 0x031c
470 +#define VEND1_GLOBAL_CFG_2_5G 0x031d
471 +#define VEND1_GLOBAL_CFG_5G 0x031e
472 +#define VEND1_GLOBAL_CFG_10G 0x031f
473 +/* ...and now the fields */
474 +#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
475 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
476 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
477 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
479 +#define VEND1_GLOBAL_RSVD_STAT1 0xc885
480 +#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
481 +#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
483 +#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
484 +#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
485 +#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
487 +#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
488 +#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
490 +#define VEND1_GLOBAL_INT_STD_MASK 0xff00
491 +#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
492 +#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
493 +#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
494 +#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
495 +#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
496 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
497 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
498 +#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
499 +#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
500 +#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
501 +#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
503 +#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
504 +#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
505 +#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
506 +#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
507 +#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
508 +#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
509 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
510 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
511 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
513 +/* Sleep and timeout for checking if the Processor-Intensive
514 + * MDIO operation is finished
516 +#define AQR107_OP_IN_PROG_SLEEP 1000
517 +#define AQR107_OP_IN_PROG_TIMEOUT 100000
519 +struct aqr107_hw_stat {
525 +#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
526 +static const struct aqr107_hw_stat aqr107_hw_stats[] = {
527 + SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
528 + SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
529 + SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
530 + SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
531 + SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
532 + SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
533 + SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
534 + SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
535 + SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
536 + SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
538 +#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
540 +struct aqr107_priv {
541 + u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
544 +static int aqr107_get_sset_count(struct phy_device *phydev)
546 + return AQR107_SGMII_STAT_SZ;
549 +static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
553 + for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
554 + strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
558 +static u64 aqr107_get_stat(struct phy_device *phydev, int index)
560 + const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
561 + int len_l = min(stat->size, 16);
562 + int len_h = stat->size - len_l;
566 + val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
570 + ret = val & GENMASK(len_l - 1, 0);
572 + val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
576 + ret += (val & GENMASK(len_h - 1, 0)) << 16;
582 +static void aqr107_get_stats(struct phy_device *phydev,
583 + struct ethtool_stats *stats, u64 *data)
585 + struct aqr107_priv *priv = phydev->priv;
589 + for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
590 + val = aqr107_get_stat(phydev, i);
591 + if (val == U64_MAX)
592 + phydev_err(phydev, "Reading HW Statistics failed for %s\n",
593 + aqr107_hw_stats[i].name);
595 + priv->sgmii_stats[i] += val;
597 + data[i] = priv->sgmii_stats[i];
601 +static int aqr_config_aneg(struct phy_device *phydev)
603 + bool changed = false;
607 + if (phydev->autoneg == AUTONEG_DISABLE)
608 + return genphy_c45_pma_setup_forced(phydev);
610 + ret = genphy_c45_an_config_aneg(phydev);
616 + /* Clause 45 has no standardized support for 1000BaseT, therefore
617 + * use vendor registers for this mode.
620 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
621 + phydev->advertising))
622 + reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
624 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
625 + phydev->advertising))
626 + reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
628 + /* Handle the case when the 2.5G and 5G speeds are not advertised */
629 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
630 + phydev->advertising))
631 + reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
633 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
634 + phydev->advertising))
635 + reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
637 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
638 + MDIO_AN_VEND_PROV_1000BASET_HALF |
639 + MDIO_AN_VEND_PROV_1000BASET_FULL |
640 + MDIO_AN_VEND_PROV_2500BASET_FULL |
641 + MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
647 + return genphy_c45_check_and_restart_aneg(phydev, changed);
650 +static int aqr_config_intr(struct phy_device *phydev)
652 + bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
656 + /* Clear any pending interrupts before enabling them */
657 + err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
662 + err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
663 + en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
667 + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
668 + en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
672 + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
673 + en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
674 + VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
679 + /* Clear any pending interrupts after we have disabled them */
680 + err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
688 +static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
692 + irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
693 + MDIO_AN_TX_VEND_INT_STATUS2);
694 + if (irq_status < 0) {
699 + if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
702 + phy_trigger_machine(phydev);
704 + return IRQ_HANDLED;
707 +static int aqr_read_status(struct phy_device *phydev)
711 + if (phydev->autoneg == AUTONEG_ENABLE) {
712 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
716 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
717 + phydev->lp_advertising,
718 + val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
719 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
720 + phydev->lp_advertising,
721 + val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
724 + return genphy_c45_read_status(phydev);
727 +static int aqr107_read_rate(struct phy_device *phydev)
732 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
736 + if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
737 + phydev->duplex = DUPLEX_FULL;
739 + phydev->duplex = DUPLEX_HALF;
741 + switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
742 + case MDIO_AN_TX_VEND_STATUS1_10BASET:
743 + phydev->speed = SPEED_10;
744 + config_reg = VEND1_GLOBAL_CFG_10M;
746 + case MDIO_AN_TX_VEND_STATUS1_100BASETX:
747 + phydev->speed = SPEED_100;
748 + config_reg = VEND1_GLOBAL_CFG_100M;
750 + case MDIO_AN_TX_VEND_STATUS1_1000BASET:
751 + phydev->speed = SPEED_1000;
752 + config_reg = VEND1_GLOBAL_CFG_1G;
754 + case MDIO_AN_TX_VEND_STATUS1_2500BASET:
755 + phydev->speed = SPEED_2500;
756 + config_reg = VEND1_GLOBAL_CFG_2_5G;
758 + case MDIO_AN_TX_VEND_STATUS1_5000BASET:
759 + phydev->speed = SPEED_5000;
760 + config_reg = VEND1_GLOBAL_CFG_5G;
762 + case MDIO_AN_TX_VEND_STATUS1_10GBASET:
763 + phydev->speed = SPEED_10000;
764 + config_reg = VEND1_GLOBAL_CFG_10G;
767 + phydev->speed = SPEED_UNKNOWN;
771 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
775 + if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
776 + VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
777 + phydev->rate_matching = RATE_MATCH_PAUSE;
779 + phydev->rate_matching = RATE_MATCH_NONE;
784 +static int aqr107_read_status(struct phy_device *phydev)
788 + ret = aqr_read_status(phydev);
792 + if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
795 + val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
799 + switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
800 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
801 + phydev->interface = PHY_INTERFACE_MODE_10GKR;
803 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
804 + phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
806 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
807 + phydev->interface = PHY_INTERFACE_MODE_10GBASER;
809 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
810 + phydev->interface = PHY_INTERFACE_MODE_USXGMII;
812 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
813 + phydev->interface = PHY_INTERFACE_MODE_XAUI;
815 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
816 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
818 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
819 + phydev->interface = PHY_INTERFACE_MODE_RXAUI;
821 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
822 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
825 + phydev->interface = PHY_INTERFACE_MODE_NA;
829 + /* Read possibly downshifted rate from vendor register */
830 + return aqr107_read_rate(phydev);
833 +static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
835 + int val, cnt, enable;
837 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
841 + enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
842 + cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
844 + *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
849 +static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
853 + if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
856 + if (cnt != DOWNSHIFT_DEV_DISABLE) {
857 + val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
858 + val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
861 + return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
862 + MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
863 + MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
866 +static int aqr107_get_tunable(struct phy_device *phydev,
867 + struct ethtool_tunable *tuna, void *data)
869 + switch (tuna->id) {
870 + case ETHTOOL_PHY_DOWNSHIFT:
871 + return aqr107_get_downshift(phydev, data);
873 + return -EOPNOTSUPP;
877 +static int aqr107_set_tunable(struct phy_device *phydev,
878 + struct ethtool_tunable *tuna, const void *data)
880 + switch (tuna->id) {
881 + case ETHTOOL_PHY_DOWNSHIFT:
882 + return aqr107_set_downshift(phydev, *(const u8 *)data);
884 + return -EOPNOTSUPP;
888 +/* If we configure settings whilst firmware is still initializing the chip,
889 + * then these settings may be overwritten. Therefore make sure chip
890 + * initialization has completed. Use presence of the firmware ID as
891 + * indicator for initialization having completed.
892 + * The chip also provides a "reset completed" bit, but it's cleared after
893 + * read. Therefore function would time out if called again.
895 +static int aqr107_wait_reset_complete(struct phy_device *phydev)
899 + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
900 + VEND1_GLOBAL_FW_ID, val, val != 0,
901 + 20000, 2000000, false);
904 +static void aqr107_chip_info(struct phy_device *phydev)
906 + u8 fw_major, fw_minor, build_id, prov_id;
909 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
913 + fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
914 + fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
916 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
920 + build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
921 + prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
923 + phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
924 + fw_major, fw_minor, build_id, prov_id);
927 +static int aqr107_config_init(struct phy_device *phydev)
931 + /* Check that the PHY interface type is compatible */
932 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
933 + phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
934 + phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
935 + phydev->interface != PHY_INTERFACE_MODE_XGMII &&
936 + phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
937 + phydev->interface != PHY_INTERFACE_MODE_10GKR &&
938 + phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
939 + phydev->interface != PHY_INTERFACE_MODE_XAUI &&
940 + phydev->interface != PHY_INTERFACE_MODE_RXAUI)
943 + WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
944 + "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
946 + ret = aqr107_wait_reset_complete(phydev);
948 + aqr107_chip_info(phydev);
950 + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
953 +static int aqcs109_config_init(struct phy_device *phydev)
957 + /* Check that the PHY interface type is compatible */
958 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
959 + phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
962 + ret = aqr107_wait_reset_complete(phydev);
964 + aqr107_chip_info(phydev);
966 + /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
967 + * PMA speed ability bits are the same for all members of the family,
968 + * AQCS109 however supports speeds up to 2.5G only.
970 + phy_set_max_speed(phydev, SPEED_2500);
972 + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
975 +static void aqr107_link_change_notify(struct phy_device *phydev)
977 + u8 fw_major, fw_minor;
978 + bool downshift, short_reach, afr;
981 + if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
984 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
985 + /* call failed or link partner is no Aquantia PHY */
986 + if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
989 + short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
990 + downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
992 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
996 + fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
997 + fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
999 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
1003 + afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
1005 + phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
1006 + fw_major, fw_minor,
1007 + short_reach ? ", short reach mode" : "",
1008 + downshift ? ", fast-retrain downshift advertised" : "",
1009 + afr ? ", fast reframe advertised" : "");
1011 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
1015 + mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
1016 + if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
1017 + phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
1020 +static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
1024 + /* The datasheet notes to wait at least 1ms after issuing a
1025 + * processor intensive operation before checking.
1026 + * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
1027 + * because that just determines the maximum time slept, not the minimum.
1029 + usleep_range(1000, 5000);
1031 + err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1032 + VEND1_GLOBAL_GEN_STAT2, val,
1033 + !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
1034 + AQR107_OP_IN_PROG_SLEEP,
1035 + AQR107_OP_IN_PROG_TIMEOUT, false);
1037 + phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
1044 +static int aqr107_get_rate_matching(struct phy_device *phydev,
1045 + phy_interface_t iface)
1047 + if (iface == PHY_INTERFACE_MODE_10GBASER ||
1048 + iface == PHY_INTERFACE_MODE_2500BASEX ||
1049 + iface == PHY_INTERFACE_MODE_NA)
1050 + return RATE_MATCH_PAUSE;
1051 + return RATE_MATCH_NONE;
1054 +static int aqr107_suspend(struct phy_device *phydev)
1058 + err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1059 + MDIO_CTRL1_LPOWER);
1063 + return aqr107_wait_processor_intensive_op(phydev);
1066 +static int aqr107_resume(struct phy_device *phydev)
1070 + err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1071 + MDIO_CTRL1_LPOWER);
1075 + return aqr107_wait_processor_intensive_op(phydev);
1078 +static int aqr107_probe(struct phy_device *phydev)
1080 + phydev->priv = devm_kzalloc(&phydev->mdio.dev,
1081 + sizeof(struct aqr107_priv), GFP_KERNEL);
1082 + if (!phydev->priv)
1085 + return aqr_hwmon_probe(phydev);
1088 +static struct phy_driver aqr_driver[] = {
1090 + PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
1091 + .name = "Aquantia AQ1202",
1092 + .config_aneg = aqr_config_aneg,
1093 + .config_intr = aqr_config_intr,
1094 + .handle_interrupt = aqr_handle_interrupt,
1095 + .read_status = aqr_read_status,
1098 + PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
1099 + .name = "Aquantia AQ2104",
1100 + .config_aneg = aqr_config_aneg,
1101 + .config_intr = aqr_config_intr,
1102 + .handle_interrupt = aqr_handle_interrupt,
1103 + .read_status = aqr_read_status,
1106 + PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
1107 + .name = "Aquantia AQR105",
1108 + .config_aneg = aqr_config_aneg,
1109 + .config_intr = aqr_config_intr,
1110 + .handle_interrupt = aqr_handle_interrupt,
1111 + .read_status = aqr_read_status,
1112 + .suspend = aqr107_suspend,
1113 + .resume = aqr107_resume,
1116 + PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
1117 + .name = "Aquantia AQR106",
1118 + .config_aneg = aqr_config_aneg,
1119 + .config_intr = aqr_config_intr,
1120 + .handle_interrupt = aqr_handle_interrupt,
1121 + .read_status = aqr_read_status,
1124 + PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
1125 + .name = "Aquantia AQR107",
1126 + .probe = aqr107_probe,
1127 + .get_rate_matching = aqr107_get_rate_matching,
1128 + .config_init = aqr107_config_init,
1129 + .config_aneg = aqr_config_aneg,
1130 + .config_intr = aqr_config_intr,
1131 + .handle_interrupt = aqr_handle_interrupt,
1132 + .read_status = aqr107_read_status,
1133 + .get_tunable = aqr107_get_tunable,
1134 + .set_tunable = aqr107_set_tunable,
1135 + .suspend = aqr107_suspend,
1136 + .resume = aqr107_resume,
1137 + .get_sset_count = aqr107_get_sset_count,
1138 + .get_strings = aqr107_get_strings,
1139 + .get_stats = aqr107_get_stats,
1140 + .link_change_notify = aqr107_link_change_notify,
1143 + PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
1144 + .name = "Aquantia AQCS109",
1145 + .probe = aqr107_probe,
1146 + .get_rate_matching = aqr107_get_rate_matching,
1147 + .config_init = aqcs109_config_init,
1148 + .config_aneg = aqr_config_aneg,
1149 + .config_intr = aqr_config_intr,
1150 + .handle_interrupt = aqr_handle_interrupt,
1151 + .read_status = aqr107_read_status,
1152 + .get_tunable = aqr107_get_tunable,
1153 + .set_tunable = aqr107_set_tunable,
1154 + .suspend = aqr107_suspend,
1155 + .resume = aqr107_resume,
1156 + .get_sset_count = aqr107_get_sset_count,
1157 + .get_strings = aqr107_get_strings,
1158 + .get_stats = aqr107_get_stats,
1159 + .link_change_notify = aqr107_link_change_notify,
1162 + PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
1163 + .name = "Aquantia AQR405",
1164 + .config_aneg = aqr_config_aneg,
1165 + .config_intr = aqr_config_intr,
1166 + .handle_interrupt = aqr_handle_interrupt,
1167 + .read_status = aqr_read_status,
1170 + PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
1171 + .name = "Aquantia AQR113C",
1172 + .probe = aqr107_probe,
1173 + .get_rate_matching = aqr107_get_rate_matching,
1174 + .config_init = aqr107_config_init,
1175 + .config_aneg = aqr_config_aneg,
1176 + .config_intr = aqr_config_intr,
1177 + .handle_interrupt = aqr_handle_interrupt,
1178 + .read_status = aqr107_read_status,
1179 + .get_tunable = aqr107_get_tunable,
1180 + .set_tunable = aqr107_set_tunable,
1181 + .suspend = aqr107_suspend,
1182 + .resume = aqr107_resume,
1183 + .get_sset_count = aqr107_get_sset_count,
1184 + .get_strings = aqr107_get_strings,
1185 + .get_stats = aqr107_get_stats,
1186 + .link_change_notify = aqr107_link_change_notify,
1190 +module_phy_driver(aqr_driver);
1192 +static struct mdio_device_id __maybe_unused aqr_tbl[] = {
1193 + { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
1194 + { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
1195 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
1196 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
1197 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
1198 + { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
1199 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
1200 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
1204 +MODULE_DEVICE_TABLE(mdio, aqr_tbl);
1206 +MODULE_DESCRIPTION("Aquantia PHY driver");
1207 +MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
1208 +MODULE_LICENSE("GPL v2");
1209 --- a/drivers/net/phy/aquantia_hwmon.c
1212 -// SPDX-License-Identifier: GPL-2.0
1213 -/* HWMON driver for Aquantia PHY
1215 - * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
1216 - * Author: Andrew Lunn <andrew@lunn.ch>
1217 - * Author: Heiner Kallweit <hkallweit1@gmail.com>
1220 -#include <linux/phy.h>
1221 -#include <linux/device.h>
1222 -#include <linux/ctype.h>
1223 -#include <linux/hwmon.h>
1225 -#include "aquantia.h"
1227 -/* Vendor specific 1, MDIO_MMD_VEND2 */
1228 -#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
1229 -#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
1230 -#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
1231 -#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
1232 -#define VEND1_THERMAL_STAT1 0xc820
1233 -#define VEND1_THERMAL_STAT2 0xc821
1234 -#define VEND1_THERMAL_STAT2_VALID BIT(0)
1235 -#define VEND1_GENERAL_STAT1 0xc830
1236 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
1237 -#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
1238 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
1239 -#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
1241 -#if IS_REACHABLE(CONFIG_HWMON)
1243 -static umode_t aqr_hwmon_is_visible(const void *data,
1244 - enum hwmon_sensor_types type,
1245 - u32 attr, int channel)
1247 - if (type != hwmon_temp)
1251 - case hwmon_temp_input:
1252 - case hwmon_temp_min_alarm:
1253 - case hwmon_temp_max_alarm:
1254 - case hwmon_temp_lcrit_alarm:
1255 - case hwmon_temp_crit_alarm:
1257 - case hwmon_temp_min:
1258 - case hwmon_temp_max:
1259 - case hwmon_temp_lcrit:
1260 - case hwmon_temp_crit:
1267 -static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
1269 - int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
1274 - /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
1275 - *value = (s16)temp * 1000 / 256;
1280 -static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
1284 - if (value >= 128000 || value < -128000)
1287 - temp = value * 256 / 1000;
1289 - /* temp is in s16 range and we're interested in lower 16 bits only */
1290 - return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
1293 -static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
1295 - int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
1300 - return !!(val & bit);
1303 -static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
1305 - int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
1315 -static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
1316 - u32 attr, int channel, long *value)
1318 - struct phy_device *phydev = dev_get_drvdata(dev);
1321 - if (type != hwmon_temp)
1322 - return -EOPNOTSUPP;
1325 - case hwmon_temp_input:
1326 - reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
1327 - VEND1_THERMAL_STAT2_VALID);
1333 - return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
1335 - case hwmon_temp_lcrit:
1336 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
1338 - case hwmon_temp_min:
1339 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
1341 - case hwmon_temp_max:
1342 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
1344 - case hwmon_temp_crit:
1345 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
1347 - case hwmon_temp_lcrit_alarm:
1348 - return aqr_hwmon_status1(phydev,
1349 - VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
1351 - case hwmon_temp_min_alarm:
1352 - return aqr_hwmon_status1(phydev,
1353 - VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
1355 - case hwmon_temp_max_alarm:
1356 - return aqr_hwmon_status1(phydev,
1357 - VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
1359 - case hwmon_temp_crit_alarm:
1360 - return aqr_hwmon_status1(phydev,
1361 - VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
1364 - return -EOPNOTSUPP;
1368 -static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
1369 - u32 attr, int channel, long value)
1371 - struct phy_device *phydev = dev_get_drvdata(dev);
1373 - if (type != hwmon_temp)
1374 - return -EOPNOTSUPP;
1377 - case hwmon_temp_lcrit:
1378 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
1380 - case hwmon_temp_min:
1381 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
1383 - case hwmon_temp_max:
1384 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
1386 - case hwmon_temp_crit:
1387 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
1390 - return -EOPNOTSUPP;
1394 -static const struct hwmon_ops aqr_hwmon_ops = {
1395 - .is_visible = aqr_hwmon_is_visible,
1396 - .read = aqr_hwmon_read,
1397 - .write = aqr_hwmon_write,
1400 -static u32 aqr_hwmon_chip_config[] = {
1401 - HWMON_C_REGISTER_TZ,
1405 -static const struct hwmon_channel_info aqr_hwmon_chip = {
1406 - .type = hwmon_chip,
1407 - .config = aqr_hwmon_chip_config,
1410 -static u32 aqr_hwmon_temp_config[] = {
1412 - HWMON_T_MAX | HWMON_T_MIN |
1413 - HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
1414 - HWMON_T_CRIT | HWMON_T_LCRIT |
1415 - HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
1419 -static const struct hwmon_channel_info aqr_hwmon_temp = {
1420 - .type = hwmon_temp,
1421 - .config = aqr_hwmon_temp_config,
1424 -static const struct hwmon_channel_info *aqr_hwmon_info[] = {
1430 -static const struct hwmon_chip_info aqr_hwmon_chip_info = {
1431 - .ops = &aqr_hwmon_ops,
1432 - .info = aqr_hwmon_info,
1435 -int aqr_hwmon_probe(struct phy_device *phydev)
1437 - struct device *dev = &phydev->mdio.dev;
1438 - struct device *hwmon_dev;
1442 - hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
1446 - for (i = j = 0; hwmon_name[i]; i++) {
1447 - if (isalnum(hwmon_name[i])) {
1449 - hwmon_name[j] = hwmon_name[i];
1453 - hwmon_name[j] = '\0';
1455 - hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
1456 - phydev, &aqr_hwmon_chip_info, NULL);
1458 - return PTR_ERR_OR_ZERO(hwmon_dev);
1462 --- a/drivers/net/phy/aquantia_main.c
1465 -// SPDX-License-Identifier: GPL-2.0
1467 - * Driver for Aquantia PHY
1469 - * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
1471 - * Copyright 2015 Freescale Semiconductor, Inc.
1474 -#include <linux/kernel.h>
1475 -#include <linux/module.h>
1476 -#include <linux/delay.h>
1477 -#include <linux/bitfield.h>
1478 -#include <linux/phy.h>
1480 -#include "aquantia.h"
1482 -#define PHY_ID_AQ1202 0x03a1b445
1483 -#define PHY_ID_AQ2104 0x03a1b460
1484 -#define PHY_ID_AQR105 0x03a1b4a2
1485 -#define PHY_ID_AQR106 0x03a1b4d0
1486 -#define PHY_ID_AQR107 0x03a1b4e0
1487 -#define PHY_ID_AQCS109 0x03a1b5c2
1488 -#define PHY_ID_AQR405 0x03a1b4b0
1489 -#define PHY_ID_AQR113C 0x31c31c12
1491 -#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
1492 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
1493 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
1494 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
1495 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
1496 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
1497 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
1498 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
1499 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
1500 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
1502 -#define MDIO_AN_VEND_PROV 0xc400
1503 -#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
1504 -#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
1505 -#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
1506 -#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
1507 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
1508 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
1509 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
1511 -#define MDIO_AN_TX_VEND_STATUS1 0xc800
1512 -#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
1513 -#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
1514 -#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
1515 -#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
1516 -#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
1517 -#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
1518 -#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
1519 -#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
1521 -#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
1522 -#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
1524 -#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
1525 -#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
1527 -#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
1528 -#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
1530 -#define MDIO_AN_RX_LP_STAT1 0xe820
1531 -#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
1532 -#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
1533 -#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
1534 -#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
1535 -#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
1537 -#define MDIO_AN_RX_LP_STAT4 0xe823
1538 -#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
1539 -#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
1541 -#define MDIO_AN_RX_VEND_STAT3 0xe832
1542 -#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
1544 -/* MDIO_MMD_C22EXT */
1545 -#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
1546 -#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
1547 -#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
1548 -#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
1549 -#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
1550 -#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
1551 -#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
1552 -#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
1553 -#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
1554 -#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
1556 -/* Vendor specific 1, MDIO_MMD_VEND1 */
1557 -#define VEND1_GLOBAL_FW_ID 0x0020
1558 -#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
1559 -#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
1561 -#define VEND1_GLOBAL_GEN_STAT2 0xc831
1562 -#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
1564 -/* The following registers all have similar layouts; first the registers... */
1565 -#define VEND1_GLOBAL_CFG_10M 0x0310
1566 -#define VEND1_GLOBAL_CFG_100M 0x031b
1567 -#define VEND1_GLOBAL_CFG_1G 0x031c
1568 -#define VEND1_GLOBAL_CFG_2_5G 0x031d
1569 -#define VEND1_GLOBAL_CFG_5G 0x031e
1570 -#define VEND1_GLOBAL_CFG_10G 0x031f
1571 -/* ...and now the fields */
1572 -#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
1573 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
1574 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
1575 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
1577 -#define VEND1_GLOBAL_RSVD_STAT1 0xc885
1578 -#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
1579 -#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
1581 -#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
1582 -#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
1583 -#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
1585 -#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
1586 -#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
1588 -#define VEND1_GLOBAL_INT_STD_MASK 0xff00
1589 -#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
1590 -#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
1591 -#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
1592 -#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
1593 -#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
1594 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
1595 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
1596 -#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
1597 -#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
1598 -#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
1599 -#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
1601 -#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
1602 -#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
1603 -#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
1604 -#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
1605 -#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
1606 -#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
1607 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
1608 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
1609 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
1611 -/* Sleep and timeout for checking if the Processor-Intensive
1612 - * MDIO operation is finished
1614 -#define AQR107_OP_IN_PROG_SLEEP 1000
1615 -#define AQR107_OP_IN_PROG_TIMEOUT 100000
1617 -struct aqr107_hw_stat {
1623 -#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
1624 -static const struct aqr107_hw_stat aqr107_hw_stats[] = {
1625 - SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
1626 - SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
1627 - SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
1628 - SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
1629 - SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
1630 - SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
1631 - SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
1632 - SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
1633 - SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
1634 - SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
1636 -#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
1638 -struct aqr107_priv {
1639 - u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
1642 -static int aqr107_get_sset_count(struct phy_device *phydev)
1644 - return AQR107_SGMII_STAT_SZ;
1647 -static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
1651 - for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
1652 - strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
1656 -static u64 aqr107_get_stat(struct phy_device *phydev, int index)
1658 - const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
1659 - int len_l = min(stat->size, 16);
1660 - int len_h = stat->size - len_l;
1664 - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
1668 - ret = val & GENMASK(len_l - 1, 0);
1670 - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
1674 - ret += (val & GENMASK(len_h - 1, 0)) << 16;
1680 -static void aqr107_get_stats(struct phy_device *phydev,
1681 - struct ethtool_stats *stats, u64 *data)
1683 - struct aqr107_priv *priv = phydev->priv;
1687 - for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
1688 - val = aqr107_get_stat(phydev, i);
1689 - if (val == U64_MAX)
1690 - phydev_err(phydev, "Reading HW Statistics failed for %s\n",
1691 - aqr107_hw_stats[i].name);
1693 - priv->sgmii_stats[i] += val;
1695 - data[i] = priv->sgmii_stats[i];
1699 -static int aqr_config_aneg(struct phy_device *phydev)
1701 - bool changed = false;
1705 - if (phydev->autoneg == AUTONEG_DISABLE)
1706 - return genphy_c45_pma_setup_forced(phydev);
1708 - ret = genphy_c45_an_config_aneg(phydev);
1714 - /* Clause 45 has no standardized support for 1000BaseT, therefore
1715 - * use vendor registers for this mode.
1718 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1719 - phydev->advertising))
1720 - reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
1722 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1723 - phydev->advertising))
1724 - reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
1726 - /* Handle the case when the 2.5G and 5G speeds are not advertised */
1727 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1728 - phydev->advertising))
1729 - reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
1731 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1732 - phydev->advertising))
1733 - reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
1735 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
1736 - MDIO_AN_VEND_PROV_1000BASET_HALF |
1737 - MDIO_AN_VEND_PROV_1000BASET_FULL |
1738 - MDIO_AN_VEND_PROV_2500BASET_FULL |
1739 - MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
1745 - return genphy_c45_check_and_restart_aneg(phydev, changed);
1748 -static int aqr_config_intr(struct phy_device *phydev)
1750 - bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
1754 - /* Clear any pending interrupts before enabling them */
1755 - err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
1760 - err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
1761 - en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
1765 - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
1766 - en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
1770 - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
1771 - en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
1772 - VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
1777 - /* Clear any pending interrupts after we have disabled them */
1778 - err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
1786 -static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
1790 - irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
1791 - MDIO_AN_TX_VEND_INT_STATUS2);
1792 - if (irq_status < 0) {
1793 - phy_error(phydev);
1797 - if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
1800 - phy_trigger_machine(phydev);
1802 - return IRQ_HANDLED;
1805 -static int aqr_read_status(struct phy_device *phydev)
1809 - if (phydev->autoneg == AUTONEG_ENABLE) {
1810 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
1814 - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1815 - phydev->lp_advertising,
1816 - val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
1817 - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1818 - phydev->lp_advertising,
1819 - val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
1822 - return genphy_c45_read_status(phydev);
1825 -static int aqr107_read_rate(struct phy_device *phydev)
1830 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
1834 - if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
1835 - phydev->duplex = DUPLEX_FULL;
1837 - phydev->duplex = DUPLEX_HALF;
1839 - switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
1840 - case MDIO_AN_TX_VEND_STATUS1_10BASET:
1841 - phydev->speed = SPEED_10;
1842 - config_reg = VEND1_GLOBAL_CFG_10M;
1844 - case MDIO_AN_TX_VEND_STATUS1_100BASETX:
1845 - phydev->speed = SPEED_100;
1846 - config_reg = VEND1_GLOBAL_CFG_100M;
1848 - case MDIO_AN_TX_VEND_STATUS1_1000BASET:
1849 - phydev->speed = SPEED_1000;
1850 - config_reg = VEND1_GLOBAL_CFG_1G;
1852 - case MDIO_AN_TX_VEND_STATUS1_2500BASET:
1853 - phydev->speed = SPEED_2500;
1854 - config_reg = VEND1_GLOBAL_CFG_2_5G;
1856 - case MDIO_AN_TX_VEND_STATUS1_5000BASET:
1857 - phydev->speed = SPEED_5000;
1858 - config_reg = VEND1_GLOBAL_CFG_5G;
1860 - case MDIO_AN_TX_VEND_STATUS1_10GBASET:
1861 - phydev->speed = SPEED_10000;
1862 - config_reg = VEND1_GLOBAL_CFG_10G;
1865 - phydev->speed = SPEED_UNKNOWN;
1869 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
1873 - if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
1874 - VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
1875 - phydev->rate_matching = RATE_MATCH_PAUSE;
1877 - phydev->rate_matching = RATE_MATCH_NONE;
1882 -static int aqr107_read_status(struct phy_device *phydev)
1886 - ret = aqr_read_status(phydev);
1890 - if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
1893 - val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
1897 - switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
1898 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
1899 - phydev->interface = PHY_INTERFACE_MODE_10GKR;
1901 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
1902 - phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
1904 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
1905 - phydev->interface = PHY_INTERFACE_MODE_10GBASER;
1907 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
1908 - phydev->interface = PHY_INTERFACE_MODE_USXGMII;
1910 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
1911 - phydev->interface = PHY_INTERFACE_MODE_XAUI;
1913 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
1914 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
1916 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
1917 - phydev->interface = PHY_INTERFACE_MODE_RXAUI;
1919 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
1920 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1923 - phydev->interface = PHY_INTERFACE_MODE_NA;
1927 - /* Read possibly downshifted rate from vendor register */
1928 - return aqr107_read_rate(phydev);
1931 -static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
1933 - int val, cnt, enable;
1935 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
1939 - enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
1940 - cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
1942 - *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
1947 -static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
1951 - if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
1954 - if (cnt != DOWNSHIFT_DEV_DISABLE) {
1955 - val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
1956 - val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
1959 - return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
1960 - MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
1961 - MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
1964 -static int aqr107_get_tunable(struct phy_device *phydev,
1965 - struct ethtool_tunable *tuna, void *data)
1967 - switch (tuna->id) {
1968 - case ETHTOOL_PHY_DOWNSHIFT:
1969 - return aqr107_get_downshift(phydev, data);
1971 - return -EOPNOTSUPP;
1975 -static int aqr107_set_tunable(struct phy_device *phydev,
1976 - struct ethtool_tunable *tuna, const void *data)
1978 - switch (tuna->id) {
1979 - case ETHTOOL_PHY_DOWNSHIFT:
1980 - return aqr107_set_downshift(phydev, *(const u8 *)data);
1982 - return -EOPNOTSUPP;
1986 -/* If we configure settings whilst firmware is still initializing the chip,
1987 - * then these settings may be overwritten. Therefore make sure chip
1988 - * initialization has completed. Use presence of the firmware ID as
1989 - * indicator for initialization having completed.
1990 - * The chip also provides a "reset completed" bit, but it's cleared after
1991 - * read. Therefore function would time out if called again.
1993 -static int aqr107_wait_reset_complete(struct phy_device *phydev)
1997 - return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1998 - VEND1_GLOBAL_FW_ID, val, val != 0,
1999 - 20000, 2000000, false);
2002 -static void aqr107_chip_info(struct phy_device *phydev)
2004 - u8 fw_major, fw_minor, build_id, prov_id;
2007 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
2011 - fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
2012 - fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
2014 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
2018 - build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
2019 - prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
2021 - phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
2022 - fw_major, fw_minor, build_id, prov_id);
2025 -static int aqr107_config_init(struct phy_device *phydev)
2029 - /* Check that the PHY interface type is compatible */
2030 - if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
2031 - phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
2032 - phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
2033 - phydev->interface != PHY_INTERFACE_MODE_XGMII &&
2034 - phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
2035 - phydev->interface != PHY_INTERFACE_MODE_10GKR &&
2036 - phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
2037 - phydev->interface != PHY_INTERFACE_MODE_XAUI &&
2038 - phydev->interface != PHY_INTERFACE_MODE_RXAUI)
2041 - WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
2042 - "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
2044 - ret = aqr107_wait_reset_complete(phydev);
2046 - aqr107_chip_info(phydev);
2048 - return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
2051 -static int aqcs109_config_init(struct phy_device *phydev)
2055 - /* Check that the PHY interface type is compatible */
2056 - if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
2057 - phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
2060 - ret = aqr107_wait_reset_complete(phydev);
2062 - aqr107_chip_info(phydev);
2064 - /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
2065 - * PMA speed ability bits are the same for all members of the family,
2066 - * AQCS109 however supports speeds up to 2.5G only.
2068 - phy_set_max_speed(phydev, SPEED_2500);
2070 - return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
2073 -static void aqr107_link_change_notify(struct phy_device *phydev)
2075 - u8 fw_major, fw_minor;
2076 - bool downshift, short_reach, afr;
2079 - if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
2082 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
2083 - /* call failed or link partner is no Aquantia PHY */
2084 - if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
2087 - short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
2088 - downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
2090 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
2094 - fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
2095 - fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
2097 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
2101 - afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
2103 - phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
2104 - fw_major, fw_minor,
2105 - short_reach ? ", short reach mode" : "",
2106 - downshift ? ", fast-retrain downshift advertised" : "",
2107 - afr ? ", fast reframe advertised" : "");
2109 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
2113 - mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
2114 - if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
2115 - phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
2118 -static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
2122 - /* The datasheet notes to wait at least 1ms after issuing a
2123 - * processor intensive operation before checking.
2124 - * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
2125 - * because that just determines the maximum time slept, not the minimum.
2127 - usleep_range(1000, 5000);
2129 - err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2130 - VEND1_GLOBAL_GEN_STAT2, val,
2131 - !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
2132 - AQR107_OP_IN_PROG_SLEEP,
2133 - AQR107_OP_IN_PROG_TIMEOUT, false);
2135 - phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
2142 -static int aqr107_get_rate_matching(struct phy_device *phydev,
2143 - phy_interface_t iface)
2145 - if (iface == PHY_INTERFACE_MODE_10GBASER ||
2146 - iface == PHY_INTERFACE_MODE_2500BASEX ||
2147 - iface == PHY_INTERFACE_MODE_NA)
2148 - return RATE_MATCH_PAUSE;
2149 - return RATE_MATCH_NONE;
2152 -static int aqr107_suspend(struct phy_device *phydev)
2156 - err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
2157 - MDIO_CTRL1_LPOWER);
2161 - return aqr107_wait_processor_intensive_op(phydev);
2164 -static int aqr107_resume(struct phy_device *phydev)
2168 - err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
2169 - MDIO_CTRL1_LPOWER);
2173 - return aqr107_wait_processor_intensive_op(phydev);
2176 -static int aqr107_probe(struct phy_device *phydev)
2178 - phydev->priv = devm_kzalloc(&phydev->mdio.dev,
2179 - sizeof(struct aqr107_priv), GFP_KERNEL);
2180 - if (!phydev->priv)
2183 - return aqr_hwmon_probe(phydev);
2186 -static struct phy_driver aqr_driver[] = {
2188 - PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
2189 - .name = "Aquantia AQ1202",
2190 - .config_aneg = aqr_config_aneg,
2191 - .config_intr = aqr_config_intr,
2192 - .handle_interrupt = aqr_handle_interrupt,
2193 - .read_status = aqr_read_status,
2196 - PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
2197 - .name = "Aquantia AQ2104",
2198 - .config_aneg = aqr_config_aneg,
2199 - .config_intr = aqr_config_intr,
2200 - .handle_interrupt = aqr_handle_interrupt,
2201 - .read_status = aqr_read_status,
2204 - PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
2205 - .name = "Aquantia AQR105",
2206 - .config_aneg = aqr_config_aneg,
2207 - .config_intr = aqr_config_intr,
2208 - .handle_interrupt = aqr_handle_interrupt,
2209 - .read_status = aqr_read_status,
2210 - .suspend = aqr107_suspend,
2211 - .resume = aqr107_resume,
2214 - PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
2215 - .name = "Aquantia AQR106",
2216 - .config_aneg = aqr_config_aneg,
2217 - .config_intr = aqr_config_intr,
2218 - .handle_interrupt = aqr_handle_interrupt,
2219 - .read_status = aqr_read_status,
2222 - PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
2223 - .name = "Aquantia AQR107",
2224 - .probe = aqr107_probe,
2225 - .get_rate_matching = aqr107_get_rate_matching,
2226 - .config_init = aqr107_config_init,
2227 - .config_aneg = aqr_config_aneg,
2228 - .config_intr = aqr_config_intr,
2229 - .handle_interrupt = aqr_handle_interrupt,
2230 - .read_status = aqr107_read_status,
2231 - .get_tunable = aqr107_get_tunable,
2232 - .set_tunable = aqr107_set_tunable,
2233 - .suspend = aqr107_suspend,
2234 - .resume = aqr107_resume,
2235 - .get_sset_count = aqr107_get_sset_count,
2236 - .get_strings = aqr107_get_strings,
2237 - .get_stats = aqr107_get_stats,
2238 - .link_change_notify = aqr107_link_change_notify,
2241 - PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
2242 - .name = "Aquantia AQCS109",
2243 - .probe = aqr107_probe,
2244 - .get_rate_matching = aqr107_get_rate_matching,
2245 - .config_init = aqcs109_config_init,
2246 - .config_aneg = aqr_config_aneg,
2247 - .config_intr = aqr_config_intr,
2248 - .handle_interrupt = aqr_handle_interrupt,
2249 - .read_status = aqr107_read_status,
2250 - .get_tunable = aqr107_get_tunable,
2251 - .set_tunable = aqr107_set_tunable,
2252 - .suspend = aqr107_suspend,
2253 - .resume = aqr107_resume,
2254 - .get_sset_count = aqr107_get_sset_count,
2255 - .get_strings = aqr107_get_strings,
2256 - .get_stats = aqr107_get_stats,
2257 - .link_change_notify = aqr107_link_change_notify,
2260 - PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
2261 - .name = "Aquantia AQR405",
2262 - .config_aneg = aqr_config_aneg,
2263 - .config_intr = aqr_config_intr,
2264 - .handle_interrupt = aqr_handle_interrupt,
2265 - .read_status = aqr_read_status,
2268 - PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
2269 - .name = "Aquantia AQR113C",
2270 - .probe = aqr107_probe,
2271 - .get_rate_matching = aqr107_get_rate_matching,
2272 - .config_init = aqr107_config_init,
2273 - .config_aneg = aqr_config_aneg,
2274 - .config_intr = aqr_config_intr,
2275 - .handle_interrupt = aqr_handle_interrupt,
2276 - .read_status = aqr107_read_status,
2277 - .get_tunable = aqr107_get_tunable,
2278 - .set_tunable = aqr107_set_tunable,
2279 - .suspend = aqr107_suspend,
2280 - .resume = aqr107_resume,
2281 - .get_sset_count = aqr107_get_sset_count,
2282 - .get_strings = aqr107_get_strings,
2283 - .get_stats = aqr107_get_stats,
2284 - .link_change_notify = aqr107_link_change_notify,
2288 -module_phy_driver(aqr_driver);
2290 -static struct mdio_device_id __maybe_unused aqr_tbl[] = {
2291 - { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
2292 - { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
2293 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
2294 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
2295 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
2296 - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
2297 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
2298 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
2302 -MODULE_DEVICE_TABLE(mdio, aqr_tbl);
2304 -MODULE_DESCRIPTION("Aquantia PHY driver");
2305 -MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
2306 -MODULE_LICENSE("GPL v2");