1 From 831a3d26bea0d14f8563eecf96def660a74a3000 Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Tue, 5 Oct 2021 21:47:02 +0200
4 Subject: [PATCH 08/11] net: dsa: rtl8366rb: Support disabling learning
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 The RTL8366RB hardware supports disabling learning per-port
10 so let's make use of this feature. Rename some unfortunately
11 named registers in the process.
13 Suggested-by: Vladimir Oltean <olteanv@gmail.com>
14 Cc: Alvin Šipraga <alsi@bang-olufsen.dk>
15 Cc: Mauri Sandberg <sandberg@mailfence.com>
16 Cc: Florian Fainelli <f.fainelli@gmail.com>
17 Cc: DENG Qingfang <dqfext@gmail.com>
18 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
19 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
20 Signed-off-by: David S. Miller <davem@davemloft.net>
22 drivers/net/dsa/rtl8366rb.c | 50 ++++++++++++++++++++++++++++++++-----
23 1 file changed, 44 insertions(+), 6 deletions(-)
25 --- a/drivers/net/dsa/rtl8366rb.c
26 +++ b/drivers/net/dsa/rtl8366rb.c
29 #include <linux/bitops.h>
30 #include <linux/etherdevice.h>
31 +#include <linux/if_bridge.h>
32 #include <linux/interrupt.h>
33 #include <linux/irqdomain.h>
34 #include <linux/irqchip/chained_irq.h>
36 /* Port Enable Control register */
37 #define RTL8366RB_PECR 0x0001
39 -/* Switch Security Control registers */
40 -#define RTL8366RB_SSCR0 0x0002
41 -#define RTL8366RB_SSCR1 0x0003
42 +/* Switch per-port learning disablement register */
43 +#define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002
45 +/* Security control, actually aging register */
46 +#define RTL8366RB_SECURITY_CTRL 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
51 @@ -927,13 +931,14 @@ static int rtl8366rb_setup(struct dsa_sw
52 /* layer 2 size, see rtl8366rb_change_mtu() */
53 rb->max_mtu[i] = 1532;
55 - /* Enable learning for all ports */
56 - ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0);
57 + /* Disable learning for all ports */
58 + ret = regmap_write(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL,
59 + RTL8366RB_PORT_ALL);
63 /* Enable auto ageing for all ports */
64 - ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0);
65 + ret = regmap_write(smi->map, RTL8366RB_SECURITY_CTRL, 0);
69 @@ -1272,6 +1277,37 @@ static int rtl8366rb_vlan_filtering(stru
74 +rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
75 + struct switchdev_brport_flags flags,
76 + struct netlink_ext_ack *extack)
78 + /* We support enabling/disabling learning */
79 + if (flags.mask & ~(BR_LEARNING))
86 +rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
87 + struct switchdev_brport_flags flags,
88 + struct netlink_ext_ack *extack)
90 + struct realtek_smi *smi = ds->priv;
93 + if (flags.mask & BR_LEARNING) {
94 + ret = regmap_update_bits(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL,
96 + (flags.val & BR_LEARNING) ? 0 : BIT(port));
104 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
106 struct realtek_smi *smi = ds->priv;
107 @@ -1682,6 +1718,8 @@ static const struct dsa_switch_ops rtl83
108 .port_vlan_del = rtl8366_vlan_del,
109 .port_enable = rtl8366rb_port_enable,
110 .port_disable = rtl8366rb_port_disable,
111 + .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
112 + .port_bridge_flags = rtl8366rb_port_bridge_flags,
113 .port_change_mtu = rtl8366rb_change_mtu,
114 .port_max_mtu = rtl8366rb_max_mtu,