1 From c766e077d927e1775902c18827205ea2ade3a35d Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Wed, 25 Jan 2023 21:35:17 +0100
4 Subject: [PATCH] net: dsa: qca8k: convert to regmap read/write API
6 Convert qca8k to regmap read/write bulk API. The mgmt eth can write up
7 to 32 bytes of data at times. Currently we use a custom function to do
8 it but regmap now supports declaration of read/write bulk even without a
11 Drop the custom function and rework the regmap function to this new
14 Rework the qca8k_fdb_read/write function to use the new
15 regmap_bulk_read/write as the old qca8k_bulk_read/write are now dropped.
17 Cc: Mark Brown <broonie@kernel.org>
18 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
19 Signed-off-by: David S. Miller <davem@davemloft.net>
21 drivers/net/dsa/qca/qca8k-8xxx.c | 92 ++++++++++++++++++++++++------
22 drivers/net/dsa/qca/qca8k-common.c | 47 ++-------------
23 drivers/net/dsa/qca/qca8k.h | 3 -
24 3 files changed, 77 insertions(+), 65 deletions(-)
26 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
27 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
28 @@ -425,16 +425,12 @@ qca8k_regmap_update_bits_eth(struct qca8
32 -qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
33 +qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)
35 - struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
36 struct mii_bus *bus = priv->bus;
40 - if (!qca8k_read_eth(priv, reg, val, sizeof(*val)))
43 qca8k_split_addr(reg, &r1, &r2, &page);
45 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
46 @@ -451,16 +447,12 @@ exit:
50 -qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
51 +qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val)
53 - struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
54 struct mii_bus *bus = priv->bus;
58 - if (!qca8k_write_eth(priv, reg, &val, sizeof(val)))
61 qca8k_split_addr(reg, &r1, &r2, &page);
63 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
64 @@ -477,17 +469,14 @@ exit:
68 -qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
69 +qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg,
70 + uint32_t mask, uint32_t write_val)
72 - struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
73 struct mii_bus *bus = priv->bus;
78 - if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
81 qca8k_split_addr(reg, &r1, &r2, &page);
83 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
84 @@ -510,17 +499,84 @@ exit:
89 +qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,
90 + void *val_buf, size_t val_len)
92 + int i, count = val_len / sizeof(u32), ret;
93 + u32 reg = *(u32 *)reg_buf & U16_MAX;
94 + struct qca8k_priv *priv = ctx;
96 + if (priv->mgmt_master &&
97 + !qca8k_read_eth(priv, reg, val_buf, val_len))
100 + /* loop count times and increment reg of 4 */
101 + for (i = 0; i < count; i++, reg += sizeof(u32)) {
102 + ret = qca8k_read_mii(priv, reg, val_buf + i);
111 +qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len,
112 + const void *val_buf, size_t val_len)
114 + int i, count = val_len / sizeof(u32), ret;
115 + u32 reg = *(u32 *)reg_buf & U16_MAX;
116 + struct qca8k_priv *priv = ctx;
117 + u32 *val = (u32 *)val_buf;
119 + if (priv->mgmt_master &&
120 + !qca8k_write_eth(priv, reg, val, val_len))
123 + /* loop count times, increment reg of 4 and increment val ptr to
126 + for (i = 0; i < count; i++, reg += sizeof(u32), val++) {
127 + ret = qca8k_write_mii(priv, reg, *val);
136 +qca8k_bulk_write(void *ctx, const void *data, size_t bytes)
138 + return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16),
139 + bytes - sizeof(u16));
143 +qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
145 + struct qca8k_priv *priv = ctx;
147 + if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
150 + return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val);
153 static struct regmap_config qca8k_regmap_config = {
157 .max_register = 0x16ac, /* end MIB - Port6 range */
158 - .reg_read = qca8k_regmap_read,
159 - .reg_write = qca8k_regmap_write,
160 + .read = qca8k_bulk_read,
161 + .write = qca8k_bulk_write,
162 .reg_update_bits = qca8k_regmap_update_bits,
163 .rd_table = &qca8k_readable_table,
164 .disable_locking = true, /* Locking is handled by qca8k read/write */
165 .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
166 + .max_raw_read = 32, /* mgmt eth can read/write up to 8 registers at time */
167 + .max_raw_write = 32,
171 @@ -2091,8 +2147,6 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
173 static const struct qca8k_info_ops qca8xxx_ops = {
174 .autocast_mib = qca8k_get_ethtool_stats_eth,
175 - .read_eth = qca8k_read_eth,
176 - .write_eth = qca8k_write_eth,
179 static const struct qca8k_match_data qca8327 = {
180 --- a/drivers/net/dsa/qca/qca8k-common.c
181 +++ b/drivers/net/dsa/qca/qca8k-common.c
182 @@ -101,45 +101,6 @@ const struct regmap_access_table qca8k_r
183 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
186 -/* TODO: remove these extra ops when we can support regmap bulk read/write */
187 -static int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
189 - int i, count = len / sizeof(u32), ret;
191 - if (priv->mgmt_master && priv->info->ops->read_eth &&
192 - !priv->info->ops->read_eth(priv, reg, val, len))
195 - for (i = 0; i < count; i++) {
196 - ret = regmap_read(priv->regmap, reg + (i * 4), val + i);
204 -/* TODO: remove these extra ops when we can support regmap bulk read/write */
205 -static int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
207 - int i, count = len / sizeof(u32), ret;
210 - if (priv->mgmt_master && priv->info->ops->write_eth &&
211 - !priv->info->ops->write_eth(priv, reg, val, len))
214 - for (i = 0; i < count; i++) {
217 - ret = regmap_write(priv->regmap, reg + (i * 4), tmp);
225 static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
228 @@ -154,8 +115,8 @@ static int qca8k_fdb_read(struct qca8k_p
231 /* load the ARL table into an array */
232 - ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg,
233 - QCA8K_ATU_TABLE_SIZE * sizeof(u32));
234 + ret = regmap_bulk_read(priv->regmap, QCA8K_REG_ATU_DATA0, reg,
235 + QCA8K_ATU_TABLE_SIZE);
239 @@ -196,8 +157,8 @@ static void qca8k_fdb_write(struct qca8k
240 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
242 /* load the array into the ARL table */
243 - qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg,
244 - QCA8K_ATU_TABLE_SIZE * sizeof(u32));
245 + regmap_bulk_write(priv->regmap, QCA8K_REG_ATU_DATA0, reg,
246 + QCA8K_ATU_TABLE_SIZE);
249 static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd,
250 --- a/drivers/net/dsa/qca/qca8k.h
251 +++ b/drivers/net/dsa/qca/qca8k.h
252 @@ -330,9 +330,6 @@ struct qca8k_priv;
254 struct qca8k_info_ops {
255 int (*autocast_mib)(struct dsa_switch *ds, int port, u64 *data);
256 - /* TODO: remove these extra ops when we can support regmap bulk read/write */
257 - int (*read_eth)(struct qca8k_priv *priv, u32 reg, u32 *val, int len);
258 - int (*write_eth)(struct qca8k_priv *priv, u32 reg, u32 *val, int len);
261 struct qca8k_match_data {