1 From fe60e7154d3a35af975c5e6570d6ec31aab9a731 Mon Sep 17 00:00:00 2001
2 From: Sean Anderson <sean.anderson@seco.com>
3 Date: Mon, 17 Oct 2022 16:22:37 -0400
4 Subject: [PATCH 02/21] net: fman: memac: Use lynx pcs driver
6 Although not stated in the datasheet, as far as I can tell PCS for mEMACs
7 is a "Lynx." By reusing the existing driver, we can remove the PCS
8 management code from the memac driver. This requires calling some PCS
9 functions manually which phylink would usually do for us, but we will let
12 One problem is that we don't actually have a PCS for QSGMII. We pretend
13 that each mEMAC's MDIO bus has four QSGMII PCSs, but this is not the case.
14 Only the "base" mEMAC's MDIO bus has the four QSGMII PCSs. This is not an
15 issue yet, because we never get the PCS state. However, it will be once the
16 conversion to phylink is complete, since the links will appear to never
17 come up. To get around this, we allow specifying multiple PCSs in pcsphy.
18 This breaks backwards compatibility with old device trees, but only for
19 QSGMII. IMO this is the only reasonable way to figure out what the actual
22 Additionally, we now also support a separate XFI PCS. This can allow the
23 SerDes driver to set different addresses for the SGMII and XFI PCSs so they
24 can be accessed at the same time.
26 Signed-off-by: Sean Anderson <sean.anderson@seco.com>
27 Signed-off-by: David S. Miller <davem@davemloft.net>
29 drivers/net/ethernet/freescale/fman/Kconfig | 3 +
30 .../net/ethernet/freescale/fman/fman_memac.c | 258 +++++++-----------
31 2 files changed, 105 insertions(+), 156 deletions(-)
33 --- a/drivers/net/ethernet/freescale/fman/Kconfig
34 +++ b/drivers/net/ethernet/freescale/fman/Kconfig
35 @@ -4,6 +4,9 @@ config FSL_FMAN
36 depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
37 select GENERIC_ALLOCATOR
45 --- a/drivers/net/ethernet/freescale/fman/fman_memac.c
46 +++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
49 #include <linux/slab.h>
51 +#include <linux/pcs-lynx.h>
52 #include <linux/phy.h>
53 #include <linux/phy_fixed.h>
54 #include <linux/phy/phy.h>
55 #include <linux/of_mdio.h>
58 -#define MDIO_SGMII_CR 0x00
59 -#define MDIO_SGMII_DEV_ABIL_SGMII 0x04
60 -#define MDIO_SGMII_LINK_TMR_L 0x12
61 -#define MDIO_SGMII_LINK_TMR_H 0x13
62 -#define MDIO_SGMII_IF_MODE 0x14
64 -/* SGMII Control defines */
65 -#define SGMII_CR_AN_EN 0x1000
66 -#define SGMII_CR_RESTART_AN 0x0200
67 -#define SGMII_CR_FD 0x0100
68 -#define SGMII_CR_SPEED_SEL1_1G 0x0040
69 -#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \
70 - SGMII_CR_SPEED_SEL1_1G)
72 -/* SGMII Device Ability for SGMII defines */
73 -#define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001
74 -#define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0
76 -/* Link timer define */
77 -#define LINK_TMR_L 0xa120
78 -#define LINK_TMR_H 0x0007
79 -#define LINK_TMR_L_BASEX 0xaf08
80 -#define LINK_TMR_H_BASEX 0x002f
82 -/* SGMII IF Mode defines */
83 -#define IF_MODE_USE_SGMII_AN 0x0002
84 -#define IF_MODE_SGMII_EN 0x0001
85 -#define IF_MODE_SGMII_SPEED_100M 0x0004
86 -#define IF_MODE_SGMII_SPEED_1G 0x0008
87 -#define IF_MODE_SGMII_DUPLEX_HALF 0x0010
89 /* Num of additional exact match MAC adr regs */
90 #define MEMAC_NUM_OF_PADDRS 7
92 @@ -326,7 +295,9 @@ struct fman_mac {
93 struct fman_rev_info fm_rev_info;
96 - struct phy_device *pcsphy;
97 + struct phylink_pcs *sgmii_pcs;
98 + struct phylink_pcs *qsgmii_pcs;
99 + struct phylink_pcs *xfi_pcs;
100 bool allmulti_enabled;
103 @@ -487,91 +458,22 @@ static u32 get_mac_addr_hash_code(u64 et
107 -static void setup_sgmii_internal_phy(struct fman_mac *memac,
108 - struct fixed_phy_status *fixed_link)
112 - if (WARN_ON(!memac->pcsphy))
116 - tmp_reg16 = IF_MODE_SGMII_EN;
119 - tmp_reg16 |= IF_MODE_USE_SGMII_AN;
121 - switch (fixed_link->speed) {
123 - /* For 10M: IF_MODE[SPEED_10M] = 0 */
126 - tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
130 - tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
133 - if (!fixed_link->duplex)
134 - tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
136 - phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
138 - /* Device ability according to SGMII specification */
139 - tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
140 - phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
142 - /* Adjust link timer for SGMII -
143 - * According to Cisco SGMII specification the timer should be 1.6 ms.
144 - * The link_timer register is configured in units of the clock.
145 - * - When running as 1G SGMII, Serdes clock is 125 MHz, so
146 - * unit = 1 / (125*10^6 Hz) = 8 ns.
147 - * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
148 - * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
149 - * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
150 - * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
151 - * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
152 - * we always set up here a value of 2.5 SGMII.
154 - phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
155 - phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
159 - tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
160 +static void setup_sgmii_internal(struct fman_mac *memac,
161 + struct phylink_pcs *pcs,
162 + struct fixed_phy_status *fixed_link)
164 + __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
165 + phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
166 + PHY_INTERFACE_MODE_SGMII;
167 + unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
169 + linkmode_set_pause(advertising, true, true);
170 + pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
172 + pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
173 + fixed_link->duplex);
176 - tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
177 - phy_write(memac->pcsphy, 0x0, tmp_reg16);
180 -static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
184 - /* AN Device capability */
185 - tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
186 - phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
188 - /* Adjust link timer for SGMII -
189 - * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
190 - * The link_timer register is configured in units of the clock.
191 - * - When running as 1G SGMII, Serdes clock is 125 MHz, so
192 - * unit = 1 / (125*10^6 Hz) = 8 ns.
193 - * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
194 - * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
195 - * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
196 - * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
197 - * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
198 - * we always set up here a value of 2.5 SGMII.
200 - phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
201 - phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
204 - tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
205 - phy_write(memac->pcsphy, 0x0, tmp_reg16);
206 + pcs->ops->pcs_an_restart(pcs);
209 static int check_init_parameters(struct fman_mac *memac)
210 @@ -983,7 +885,6 @@ static int memac_set_exception(struct fm
211 static int memac_init(struct fman_mac *memac)
213 struct memac_cfg *memac_drv_param;
215 enet_addr_t eth_addr;
216 bool slow_10g_if = false;
217 struct fixed_phy_status *fixed_link = NULL;
218 @@ -1036,32 +937,10 @@ static int memac_init(struct fman_mac *m
219 iowrite32be(reg32, &memac->regs->command_config);
222 - if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
223 - /* Configure internal SGMII PHY */
224 - if (memac->basex_if)
225 - setup_sgmii_internal_phy_base_x(memac);
227 - setup_sgmii_internal_phy(memac, fixed_link);
228 - } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
229 - /* Configure 4 internal SGMII PHYs */
230 - for (i = 0; i < 4; i++) {
231 - u8 qsmgii_phy_addr, phy_addr;
232 - /* QSGMII PHY address occupies 3 upper bits of 5-bit
233 - * phy_address; the lower 2 bits are used to extend
234 - * register address space and access each one of 4
235 - * ports inside QSGMII.
237 - phy_addr = memac->pcsphy->mdio.addr;
238 - qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
239 - memac->pcsphy->mdio.addr = qsmgii_phy_addr;
240 - if (memac->basex_if)
241 - setup_sgmii_internal_phy_base_x(memac);
243 - setup_sgmii_internal_phy(memac, fixed_link);
245 - memac->pcsphy->mdio.addr = phy_addr;
248 + if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
249 + setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
250 + else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
251 + setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
253 /* Max Frame Length */
254 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
255 @@ -1097,12 +976,25 @@ static int memac_init(struct fman_mac *m
259 +static void pcs_put(struct phylink_pcs *pcs)
261 + struct mdio_device *mdiodev;
263 + if (IS_ERR_OR_NULL(pcs))
266 + mdiodev = lynx_get_mdio_device(pcs);
267 + lynx_pcs_destroy(pcs);
268 + mdio_device_free(mdiodev);
271 static int memac_free(struct fman_mac *memac)
273 free_init_resources(memac);
276 - put_device(&memac->pcsphy->mdio.dev);
277 + pcs_put(memac->sgmii_pcs);
278 + pcs_put(memac->qsgmii_pcs);
279 + pcs_put(memac->xfi_pcs);
281 kfree(memac->memac_drv_param);
283 @@ -1153,12 +1045,31 @@ static struct fman_mac *memac_config(str
287 +static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
290 + struct device_node *node;
291 + struct mdio_device *mdiodev = NULL;
292 + struct phylink_pcs *pcs;
294 + node = of_parse_phandle(mac_node, "pcsphy-handle", index);
295 + if (node && of_device_is_available(node))
296 + mdiodev = of_mdio_find_device(node);
300 + return ERR_PTR(-EPROBE_DEFER);
302 + pcs = lynx_pcs_create(mdiodev);
306 int memac_initialization(struct mac_device *mac_dev,
307 struct device_node *mac_node,
308 struct fman_mac_params *params)
311 - struct device_node *phy_node;
312 + struct phylink_pcs *pcs;
313 struct fixed_phy_status *fixed_link;
314 struct fman_mac *memac;
316 @@ -1188,23 +1099,58 @@ int memac_initialization(struct mac_devi
317 memac = mac_dev->fman_mac;
318 memac->memac_drv_param->max_frame_length = fman_get_max_frm();
319 memac->memac_drv_param->reset_on_init = true;
320 - if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
321 - memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
322 - phy_node = of_parse_phandle(mac_node, "pcsphy-handle", 0);
324 - pr_err("PCS PHY node is not available\n");
327 + err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
329 + memac->xfi_pcs = memac_pcs_create(mac_node, err);
330 + if (IS_ERR(memac->xfi_pcs)) {
331 + err = PTR_ERR(memac->xfi_pcs);
332 + dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
333 goto _return_fm_mac_free;
335 + } else if (err != -EINVAL && err != -ENODATA) {
336 + goto _return_fm_mac_free;
339 - memac->pcsphy = of_phy_find_device(phy_node);
340 - if (!memac->pcsphy) {
341 - pr_err("of_phy_find_device (PCS PHY) failed\n");
343 + err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
345 + memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
346 + if (IS_ERR(memac->qsgmii_pcs)) {
347 + err = PTR_ERR(memac->qsgmii_pcs);
348 + dev_err_probe(mac_dev->dev, err,
349 + "missing qsgmii pcs\n");
350 goto _return_fm_mac_free;
352 + } else if (err != -EINVAL && err != -ENODATA) {
353 + goto _return_fm_mac_free;
356 + /* For compatibility, if pcs-handle-names is missing, we assume this
357 + * phy is the first one in pcsphy-handle
359 + err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
360 + if (err == -EINVAL || err == -ENODATA)
361 + pcs = memac_pcs_create(mac_node, 0);
363 + goto _return_fm_mac_free;
365 + pcs = memac_pcs_create(mac_node, err);
368 + dev_err(mac_dev->dev, "missing pcs\n");
370 + goto _return_fm_mac_free;
373 + /* If err is set here, it means that pcs-handle-names was missing above
374 + * (and therefore that xfi_pcs cannot be set). If we are defaulting to
375 + * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
377 + if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
378 + memac->xfi_pcs = pcs;
380 + memac->sgmii_pcs = pcs;
382 memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
383 err = PTR_ERR(memac->serdes);
384 if (err == -ENODEV || err == -ENOSYS) {