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12 ********************************************************************************
13 Marvell Commercial License Option
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39 are permitted provided that the following conditions are met:
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42 this list of conditions and the following disclaimer.
44 * Redistributions in binary form must reproduce the above copyright
45 notice, this list of conditions and the following disclaimer in the
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61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
66 #include "cpu/mvCpu.h"
67 #include "ctrlEnv/mvCtrlEnvLib.h"
68 #include "ctrlEnv/mvCtrlEnvRegs.h"
69 #include "ctrlEnv/sys/mvCpuIfRegs.h"
80 /*******************************************************************************
81 * mvCpuPclkGet - Get the CPU pClk (pipe clock)
84 * This routine extract the CPU core clock.
93 * 32bit clock cycles in MHertz.
95 *******************************************************************************/
96 /* 6180 have different clk reset sampling */
98 static MV_U32
mvCpu6180PclkGet(MV_VOID
)
100 MV_U32 tmpPClkRate
=0;
101 MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK
[] = MV_CPU6180_DDR_L2_CLCK_TBL
;
103 tmpPClkRate
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
104 tmpPClkRate
= tmpPClkRate
& MSAR_CPUCLCK_MASK_6180
;
105 tmpPClkRate
= tmpPClkRate
>> MSAR_CPUCLCK_OFFS_6180
;
107 tmpPClkRate
= cpu6180_ddr_l2_CLK
[tmpPClkRate
].cpuClk
;
113 MV_U32
mvCpuPclkGet(MV_VOID
)
115 #if defined(PCLCK_AUTO_DETECT)
116 MV_U32 tmpPClkRate
=0;
117 MV_U32 cpuCLK
[] = MV_CPU_CLCK_TBL
;
119 if(mvCtrlModelGet() == MV_6180_DEV_ID
)
120 return mvCpu6180PclkGet();
122 tmpPClkRate
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
123 tmpPClkRate
= MSAR_CPUCLCK_EXTRACT(tmpPClkRate
);
124 tmpPClkRate
= cpuCLK
[tmpPClkRate
];
128 return MV_DEFAULT_PCLK
132 /*******************************************************************************
133 * mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock)
136 * This routine extract the CPU L2 clock.
139 * 32bit clock cycles in Hertz.
141 *******************************************************************************/
142 static MV_U32
mvCpu6180L2ClkGet(MV_VOID
)
145 MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK
[] = MV_CPU6180_DDR_L2_CLCK_TBL
;
147 L2ClkRate
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
148 L2ClkRate
= L2ClkRate
& MSAR_CPUCLCK_MASK_6180
;
149 L2ClkRate
= L2ClkRate
>> MSAR_CPUCLCK_OFFS_6180
;
151 L2ClkRate
= _cpu6180_ddr_l2_CLK
[L2ClkRate
].l2Clk
;
157 MV_U32
mvCpuL2ClkGet(MV_VOID
)
159 #ifdef L2CLK_AUTO_DETECT
160 MV_U32 L2ClkRate
, tmp
, pClkRate
, indexL2Rtio
;
161 MV_U32 L2Rtio
[][2] = MV_L2_CLCK_RTIO_TBL
;
163 if(mvCtrlModelGet() == MV_6180_DEV_ID
)
164 return mvCpu6180L2ClkGet();
166 pClkRate
= mvCpuPclkGet();
168 tmp
= MV_REG_READ(MPP_SAMPLE_AT_RESET
);
169 indexL2Rtio
= MSAR_L2CLCK_EXTRACT(tmp
);
171 L2ClkRate
= ((pClkRate
* L2Rtio
[indexL2Rtio
][1]) / L2Rtio
[indexL2Rtio
][0]);
175 return MV_BOARD_DEFAULT_L2CLK
;
180 /*******************************************************************************
181 * mvCpuNameGet - Get CPU name
184 * This function returns a string describing the CPU model and revision.
190 * pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
194 *******************************************************************************/
195 MV_VOID
mvCpuNameGet(char *pNameBuff
)
199 cpuModel
= mvOsCpuPartGet();
201 /* The CPU module is indicated in the Processor Version Register (PVR) */
204 case CPU_PART_MRVL131
:
205 mvOsSPrintf(pNameBuff
, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet());
207 case CPU_PART_ARM926
:
208 mvOsSPrintf(pNameBuff
, "%s (Rev %d)", "ARM926",mvOsCpuRevGet());
210 case CPU_PART_ARM946
:
211 mvOsSPrintf(pNameBuff
, "%s (Rev %d)", "ARM946",mvOsCpuRevGet());
214 mvOsSPrintf(pNameBuff
,"??? (0x%04x) (Rev %d)",cpuModel
,mvOsCpuRevGet());
222 #define MV_PROC_STR_SIZE 50
224 static void mvCpuIfGetL2EccMode(MV_8
*buf
)
226 MV_U32 regVal
= MV_REG_READ(CPU_L2_CONFIG_REG
);
228 mvOsSPrintf(buf
, "L2 ECC Enabled");
230 mvOsSPrintf(buf
, "L2 ECC Disabled");
233 static void mvCpuIfGetL2Mode(MV_8
*buf
)
236 __asm
volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal
)); /* Read Marvell extra features register */
238 mvOsSPrintf(buf
, "L2 Enabled");
240 mvOsSPrintf(buf
, "L2 Disabled");
243 static void mvCpuIfGetL2PrefetchMode(MV_8
*buf
)
246 __asm
volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal
)); /* Read Marvell extra features register */
248 mvOsSPrintf(buf
, "L2 Prefetch Disabled");
250 mvOsSPrintf(buf
, "L2 Prefetch Enabled");
253 static void mvCpuIfGetWriteAllocMode(MV_8
*buf
)
256 __asm
volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal
)); /* Read Marvell extra features register */
258 mvOsSPrintf(buf
, "Write Allocate Enabled");
260 mvOsSPrintf(buf
, "Write Allocate Disabled");
263 static void mvCpuIfGetCpuStreamMode(MV_8
*buf
)
266 __asm
volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal
)); /* Read Marvell extra features register */
268 mvOsSPrintf(buf
, "CPU Streaming Enabled");
270 mvOsSPrintf(buf
, "CPU Streaming Disabled");
273 static void mvCpuIfPrintCpuRegs(void)
277 __asm
volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal
)); /* Read Marvell extra features register */
278 mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal
);
280 __asm
volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal
)); /* Read Control register */
281 mvOsPrintf("Control Reg = 0x%x\n",regVal
);
283 __asm
volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal
)); /* Read ID Code register */
284 mvOsPrintf("ID Code Reg = 0x%x\n",regVal
);
286 __asm
volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal
)); /* Read Cache Type register */
287 mvOsPrintf("Cache Type Reg = 0x%x\n",regVal
);
291 MV_U32
mvCpuIfPrintSystemConfig(MV_8
*buffer
, MV_U32 index
)
295 MV_8 L2_ECC_str
[MV_PROC_STR_SIZE
];
296 MV_8 L2_En_str
[MV_PROC_STR_SIZE
];
297 MV_8 L2_Prefetch_str
[MV_PROC_STR_SIZE
];
298 MV_8 Write_Alloc_str
[MV_PROC_STR_SIZE
];
299 MV_8 Cpu_Stream_str
[MV_PROC_STR_SIZE
];
301 mvCpuIfGetL2Mode(L2_En_str
);
302 mvCpuIfGetL2EccMode(L2_ECC_str
);
303 mvCpuIfGetL2PrefetchMode(L2_Prefetch_str
);
304 mvCpuIfGetWriteAllocMode(Write_Alloc_str
);
305 mvCpuIfGetCpuStreamMode(Cpu_Stream_str
);
306 mvCpuIfPrintCpuRegs();
308 count
+= mvOsSPrintf(buffer
+ count
+ index
, "%s\n", L2_En_str
);
309 count
+= mvOsSPrintf(buffer
+ count
+ index
, "%s\n", L2_ECC_str
);
310 count
+= mvOsSPrintf(buffer
+ count
+ index
, "%s\n", L2_Prefetch_str
);
311 count
+= mvOsSPrintf(buffer
+ count
+ index
, "%s\n", Write_Alloc_str
);
312 count
+= mvOsSPrintf(buffer
+ count
+ index
, "%s\n", Cpu_Stream_str
);
316 MV_U32
whoAmI(MV_VOID
)