1 /*******************************************************************************
2 Copyright (C) Marvell International Ltd. and its affiliates
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10 Marvell copyright notice above.
12 ********************************************************************************
13 Marvell Commercial License Option
15 If you received this File from Marvell and you have entered into a commercial
16 license agreement (a "Commercial License") with Marvell, the File is licensed
17 to you under the terms of the applicable Commercial License.
19 ********************************************************************************
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23 modify this File in accordance with the terms and conditions of the General
24 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
25 available along with the File in the license.txt file or by writing to the Free
26 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
27 on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
29 THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
30 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
31 DISCLAIMED. The GPL License provides additional details about this warranty
33 ********************************************************************************
34 Marvell BSD License Option
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37 modify this File under the following licensing terms.
38 Redistribution and use in source and binary forms, with or without modification,
39 are permitted provided that the following conditions are met:
41 * Redistributions of source code must retain the above copyright notice,
42 this list of conditions and the following disclaimer.
44 * Redistributions in binary form must reproduce the above copyright
45 notice, this list of conditions and the following disclaimer in the
46 documentation and/or other materials provided with the distribution.
48 * Neither the name of Marvell nor the names of its contributors may be
49 used to endorse or promote products derived from this software without
50 specific prior written permission.
52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
65 #define MV_ASMLANGUAGE
66 #include "mvSysHwConfig.h"
68 #include "mvBoardEnvSpec.h"
69 #include "mvCpuIfRegs.h"
70 #include "mvDramIfConfig.h"
71 #include "mvDramIfRegs.h"
72 #include "pex/mvPexRegs.h"
73 #include "pci/mvPciRegs.h"
74 #include "mvCtrlEnvSpec.h"
75 #include "mvCtrlEnvAsm.h"
76 #include "cpu/mvCpuArm.h"
81 #if !defined(MV_INC_BOARD_DDIM)
86 /******************************************************************************
91 *******************************************************************************/
92 #if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG)
94 /* PEX_PCI and PRPMC boards 256 MB*/
95 #define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
96 #define STATIC_SDRAM_CONFIG 0x03248400
97 #define STATIC_SDRAM_MODE 0x62
98 #define STATIC_DUNIT_CTRL_LOW 0x4041000
99 #define STATIC_SDRAM_ADDR_CTRL 0x00000020
100 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
101 #define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F
102 #define STATIC_SDRAM_ODT_CTRL_LOW 0x0
103 #define STATIC_SDRAM_ODT_CTRL_HI 0x0
104 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
105 #define STATIC_SDRAM_EXT_MODE 0x0
107 #elif defined(DB_FPGA)
109 /* FPGA DC boards 256 MB*/
110 #define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
111 #define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */
112 #define STATIC_SDRAM_MODE 0x22
113 #define STATIC_DUNIT_CTRL_LOW 0x03041000
114 #define STATIC_SDRAM_ADDR_CTRL 0x00000020
115 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220
116 #define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D
117 #define STATIC_SDRAM_ODT_CTRL_LOW 0x0
118 #define STATIC_SDRAM_ODT_CTRL_HI 0x0
119 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
120 #define STATIC_SDRAM_EXT_MODE 0x1
122 #elif defined(RD_88F6183GP) || defined(DB_CUSTOMER)
124 /* Customer 1 DDR2 2 devices 512Mbit by 16 bit */
125 #define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
126 #define STATIC_SDRAM_CONFIG 0x03158400
127 #define STATIC_SDRAM_MODE 0x452
128 #define STATIC_DUNIT_CTRL_LOW 0x06041000
129 #define STATIC_SDRAM_ADDR_CTRL 0x00000020
130 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
131 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
132 #define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
133 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
134 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
135 #define STATIC_SDRAM_EXT_MODE 0x00000440
138 #elif defined(RD_88F6183AP)
140 /* DDR2 1 devices 512Mbit by 16 bit */
141 #define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
142 #define STATIC_SDRAM_CONFIG 0x1f154400
143 #define STATIC_SDRAM_MODE 0x432
144 #define STATIC_DUNIT_CTRL_LOW 0x04041000
145 #define STATIC_SDRAM_ADDR_CTRL 0x00000020
146 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
147 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
148 #define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
149 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
150 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
151 #define STATIC_SDRAM_EXT_MODE 0x00000440
153 /* 6082L MARVELL DIMM */
154 #elif defined(DB_88F6082LBP)
155 #define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
156 #define STATIC_SDRAM_CONFIG 0x7f158400
157 #define STATIC_SDRAM_MODE 0x432
158 #define STATIC_DUNIT_CTRL_LOW 0x04041040
159 #define STATIC_SDRAM_ADDR_CTRL 0x00000020
160 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220
161 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000501
162 #define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
163 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
164 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01
165 #define STATIC_SDRAM_EXT_MODE 0x00000440
167 #elif defined(RD_88W8660_AP82S)
171 #if defined(MV_DRAM_32M)
172 #define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001
173 #define STATIC_SDRAM_ADDR_CTRL 0x00000010
174 #elif defined(MV_DRAM_16M)
176 #define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001
177 #define STATIC_SDRAM_ADDR_CTRL 0x00000000
180 #error "NO DDR size selected"
183 #define STATIC_SDRAM_CONFIG 0x03144400
184 #define STATIC_SDRAM_MODE 0x62
185 #define STATIC_DUNIT_CTRL_LOW 0x4041000
187 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
188 #define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
189 #define STATIC_SDRAM_ODT_CTRL_LOW 0x0
190 #define STATIC_SDRAM_ODT_CTRL_HI 0x0
191 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
192 #define STATIC_SDRAM_EXT_MODE 0x0
194 #elif defined(RD_88W8660)
197 #define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
198 #define STATIC_SDRAM_CONFIG 0x03144400
199 #define STATIC_SDRAM_MODE 0x62
200 #define STATIC_DUNIT_CTRL_LOW 0x4041000
201 #define STATIC_SDRAM_ADDR_CTRL 0x00000010
202 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
203 #define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
204 #define STATIC_SDRAM_ODT_CTRL_LOW 0x0
205 #define STATIC_SDRAM_ODT_CTRL_HI 0x0
206 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
207 #define STATIC_SDRAM_EXT_MODE 0x0
212 #if defined(RD_88F5182)
214 #if defined(MV_88F5082)
215 #define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
216 #define STATIC_SDRAM_ADDR_CTRL 0x20
218 #define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
219 #define STATIC_SDRAM_ADDR_CTRL 0x20
222 #elif defined(RD_88F5182_3)
224 #if defined(MV_88F5082)
225 #define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
226 #define STATIC_SDRAM_ADDR_CTRL 0x20
228 #define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
229 #define STATIC_SDRAM_ADDR_CTRL 0x20
234 #define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001
235 #define STATIC_SDRAM_ADDR_CTRL 0x0
239 #if defined(MV_88F5082)
240 #define STATIC_SDRAM_CONFIG 0x3144400
242 #define STATIC_SDRAM_CONFIG 0x3148400
244 #define STATIC_SDRAM_MODE 0x62
245 #define STATIC_DUNIT_CTRL_LOW 0x4041000
246 #define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
247 #define STATIC_SDRAM_TIME_CTRL_HI 0x40c
248 #define STATIC_SDRAM_ODT_CTRL_LOW 0x0
249 #define STATIC_SDRAM_ODT_CTRL_HI 0x0
250 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
251 #define STATIC_SDRAM_EXT_MODE 0x0
255 .globl _mvDramIfStaticInit
258 mov r11, LR /* Save link register */
261 /* If we boot from NAND jump to DRAM sddress */
265 str r5, [r6] /* We started executing from DRAM */
272 /* set all dram windows to 0 */
274 MV_REG_WRITE_ASM(r6, r5, 0x1504)
275 MV_REG_WRITE_ASM(r6, r5, 0x150c)
276 MV_REG_WRITE_ASM(r6, r5, 0x1514)
277 MV_REG_WRITE_ASM(r6, r5, 0x151c)
279 /* set all dram configuration in temp registers */
280 ldr r6, = STATIC_SDRAM0_BANK0_SIZE
281 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
282 ldr r6, = STATIC_SDRAM_CONFIG
283 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
284 ldr r6, = STATIC_SDRAM_MODE
285 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
286 ldr r6, = STATIC_DUNIT_CTRL_LOW
287 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
288 ldr r6, = STATIC_SDRAM_ADDR_CTRL
289 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
290 ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
291 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
292 ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
293 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
294 ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
295 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
296 ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
297 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
298 ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
299 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
300 ldr r6, = STATIC_SDRAM_EXT_MODE
301 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
307 mov PC, r11 /* r11 is saved link register */
309 #else /* #if !defined(MV_INC_BOARD_DDIM) */
315 /*******************************************************************************
316 * mvDramIfBasicInit - Basic initialization of DRAM interface
319 * The function will initialize the DRAM for basic usage. The function
320 * will use the TWSI assembly API to extract DIMM parameters according
321 * to which DRAM interface will be initialized.
322 * The function referes to the following DRAM parameters:
323 * 1) DIMM is registered or not.
324 * 2) DIMM width detection.
328 * r3 - required size for initial DRAM.
337 * r4 holds I2C EEPROM address
338 * r5 holds SDRAM register base address
339 * r7 holds returned values
340 * r8 holds SDRAM various configuration registers value.
341 * r11 holds return function address.
342 *******************************************************************************/
343 /* Setting the offsets of the I2C registers */
344 #define NUM_OF_ROWS_OFFSET 3
345 #define NUM_OF_COLS_OFFSET 4
346 #define NUM_OF_RANKS 5
347 #define SDRAM_WIDTH_OFFSET 13
348 #define NUM_OF_BANKS_OFFSET 17
349 #define SUPPORTED_CL_OFFSET 18
350 #define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
351 #define SDRAM_MODULES_ATTR_OFFSET 21
353 #define DRAM_DEV_DENSITY_128M 0x080
354 #define DRAM_DEV_DENSITY_256M 0x100
355 #define DRAM_DEV_DENSITY_512M 0x200
356 .globl _mvDramIfBasicInit
361 mov r11, LR /* Save link register */
365 str r5, [r8] /* We started executing from DRAM */
367 /* If we boot from NAND jump to DRAM sddress */
374 bl _i2cInit /* Initialize TWSI master */
376 /* Get default SDRAM Config values */
377 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
378 bic r8, r8, #SDRAM_DCFG_MASK
382 MV_CTRL_MODEL_GET_ASM(r4, r5);
384 /* Return if OrionN */
385 ldr r5, =MV_5180_DEV_ID
389 /* Return if Orion1 */
390 ldr r5, =MV_5181_DEV_ID
395 ldr r5, =MV_5182_DEV_ID
399 /* Return if Shark */
400 ldr r5, =MV_8660_DEV_ID
404 /* goto calcConfigReg if bigger than Orion2*/
405 ldr r5, =MV_5281_DEV_ID
410 /* set cat through - for better performance - in orion2 b0 and higher*/
411 orr r8, r8, #SDRAM_CATTHR_EN
416 /* Get registered/non registered info from DIMM */
421 orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
424 /* Get SDRAM width */
427 orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */
431 orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */
435 /* This is an error. return */
440 ldr r6, =SDRAM_CONFIG_DV
441 orr r8, r8, r6 /* Add default settings */
442 mov r6, r8 /* Do not swap r8 content */
443 MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG)
445 /* Set maximum CL supported by DIMM */
448 /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
450 rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
452 /* Check the DDR version */
453 tst r8, #SDRAM_DTYPE_DDR2
457 ldr r7, =3 /* stBurstDel field value */
458 ldr r8, =0x52 /* Assuming MAX CL = 1.5 */
459 cmp r6, #1 /* If CL = 1.5 break */
462 ldr r7, =3 /* stBurstDel field value */
463 ldr r8, =0x22 /* Assuming MAX CL = 2 */
464 cmp r6, #2 /* If CL = 2 break */
467 ldr r7, =4 /* stBurstDel field value */
468 ldr r8, =0x62 /* Assuming MAX CL = 2.5 */
469 cmp r6, #3 /* If CL = 2.5 break */
472 ldr r7, =4 /* stBurstDel field value */
473 ldr r8, =0x32 /* Assuming MAX CL = 3 */
474 cmp r6, #4 /* If CL = 3 break */
477 ldr r7, =5 /* stBurstDel field value */
478 ldr r8, =0x42 /* Assuming MAX CL = 4 */
479 cmp r6, #6 /* If CL = 4 break */
482 b exit_ddrAutoConfig /* This is an error !! */
485 ldr r7, =4 /* stBurstDel field value */
486 ldr r8, =0x32 /* Assuming MAX CL = 3 */
487 cmp r6, #3 /* If CL = 3 break */
490 ldr r7, =5 /* stBurstDel field value */
491 ldr r8, =0x42 /* Assuming MAX CL = 4 */
492 cmp r6, #4 /* If CL = 4 break */
495 /* CL 5 currently unsupported. We use CL 4 instead */
496 ldr r7, =5 /* stBurstDel field value */
497 ldr r8, =0x42 /* Assuming MAX CL = 5 */
498 cmp r6, #5 /* If CL = 5 break */
501 b exit_ddrAutoConfig /* This is an error !! */
503 /* Write recovery for auto-precharge relevant only in DDR2 */
504 orr r8, r8, #0x400 /* Default value */
507 /* The CPU must not attempt to change the SDRAM Mode register setting */
508 /* prior to DRAM controller completion of the DRAM initialization */
509 /* sequence. To guarantee this restriction, it is recommended that */
510 /* the CPU sets the SDRAM Operation register to NOP command, performs */
511 /* read polling until the register is back in Normal operation value, */
512 /* and then sets SDRAM Mode register to it's new value. */
514 /* write 'nop' to SDRAM operation */
515 mov r6, #0x5 /* 'NOP' command */
516 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
518 /* poll SDRAM operation. Make sure its back to normal operation */
521 cmp r6, #0 /* '0' = Normal SDRAM Mode */
524 /* Now its safe to write new value to SDRAM Mode register */
525 MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG)
527 /* Make the Dunit write the DRAM its new mode */
528 mov r6, #0x3 /* Mode Register Set command */
529 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
531 /* poll SDRAM operation. Make sure its back to normal operation */
534 cmp r6, #0 /* '0' = Normal SDRAM Mode */
537 /* Set Dunit control register according to max CL detected */
538 /* If we use registered DIMM, add 1 to stBurstDel */
539 MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG)
540 tst r6, #SDRAM_REGISTERED
545 ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV
546 orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS
547 MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
550 /* DIMM density configuration*/
551 /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
555 mov r8, r8, LSR #20 /* Move density 20 bits to the right */
556 /* For example 0x10000000 --> 0x1000 */
559 cmp r8, #DRAM_DEV_DENSITY_128M
563 cmp r8, #DRAM_DEV_DENSITY_256M
567 cmp r8, #DRAM_DEV_DENSITY_512M
570 /* This is an error. return */
574 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG)
576 /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
577 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
578 tst r8, #SDRAM_DTYPE_DDR2
582 /* Set DDR Extended Mode register for working with CS[0] */
583 /* write 'nop' to SDRAM operation */
584 mov r6, #0x5 /* 'NOP' command */
585 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
587 /* poll SDRAM operation. Make sure its back to normal operation */
590 cmp r6, #0 /* '0' = Normal SDRAM Mode */
593 /* Now its safe to write new value to SDRAM Extended Mode register */
594 ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV
595 MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG)
597 /* Make the Dunit write the DRAM its new extended mode */
598 mov r6, #0x4 /* Extended Mode Register Set command */
599 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
601 /* poll SDRAM operation. Make sure its back to normal operation */
604 cmp r6, #0 /* '0' = Normal SDRAM Mode */
607 /* ODT configuration is done for single bank CS[0] only */
608 /* Config DDR2 On Die Termination (ODT) registers */
609 ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV
610 MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG)
612 ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV
613 MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
615 ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV
616 MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG)
619 /* we will check what device we are running and perform
620 Initialization according to device value */
624 /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
625 /* Does Not Work for Address/Control and Data Pads. */
626 /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
629 MV_CTRL_MODEL_GET_ASM(r6, r5);
630 /* Read device revision */
631 MV_CTRL_REV_GET_ASM(r8, r5);
633 /* Continue if OrionN */
634 ldr r5, =MV_5180_DEV_ID
640 /* Continue if Orion1 and device revision B1 */
641 ldr r5, =MV_5181_DEV_ID
645 cmp r8, #MV_5181_B1_REV
651 ldr r5, =MV_5182_DEV_ID
656 ldr r5, =MV_8660_DEV_ID
664 /* DDR SDRAM Address/Control Pads Calibration */
665 MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
667 /* Set Bit [31] to make the register writable */
668 orr r8, r6, #SDRAM_WR_EN
670 MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
672 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
673 bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
674 bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
675 bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
677 /* Get the final N locked value of driving strength [22:17] */
680 mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */
681 orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */
683 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
686 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
689 /* DDR SDRAM Data Pads Calibration */
690 MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
692 /* Set Bit [31] to make the register writable */
693 orr r8, r6, #SDRAM_WR_EN
695 MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG)
697 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
698 bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
699 bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
700 bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
702 /* Get the final N locked value of driving strength [22:17] */
706 orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */
708 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
711 MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
714 /* Implement Guideline (GL# MEM-3) Drive Strength Value */
715 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
717 /* Get SDRAM Config value */
718 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
721 tst r8, #SDRAM_DTYPE_DDR2
725 ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
726 ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
729 ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
730 ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
733 /* DDR SDRAM Address/Control Pads Calibration */
734 MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
736 orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
738 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
741 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
742 bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
743 orr r6, r4, r6 /* Set default value for DDR */
745 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
748 /* DDR SDRAM Data Pads Calibration */
749 MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
751 orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
753 MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
756 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
757 bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
758 orr r6, r8, r6 /* Set default value for DDR */
760 MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
763 /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
764 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
765 /* Get the "sample on reset" register for the DDR frequancy */
767 #if defined(MV_RUN_FROM_FLASH)
768 /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
769 ldr r7, = _cpuARMDDRCLK
773 ldr r4, = Lrom_start_of_data
777 /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
778 ldr r7, = _cpuARMDDRCLK
781 add r7, r7, #CFG_MONITOR_BASE
783 /* Get the "sample on reset" register for the DDR frequancy */
784 MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
785 ldr r5, =MSAR_ARMDDRCLCK_MASK
787 #if 0 /* YOTAM TO BE FIX */
788 mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS
792 MV_CTRL_MODEL_GET_ASM(r6, r8);
794 /* Continue if TC90 */
795 ldr r8, =MV_1281_DEV_ID
799 /* Continue if Orion2 */
800 ldr r8, =MV_5281_DEV_ID
802 #if 0 /* YOTAM TO BE FIX */
807 #if 0 /* YOTAM TO BE FIX */
808 tst r4, #MSAR_ARMDDRCLCK_H_MASK
812 ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
815 add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
819 /* Get SDRAM Config value */
820 MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG)
823 tst r8, #SDRAM_DTYPE_DDR2
827 ldr r4, =FTDLL_DDR2_250MHZ
831 ldr r4, =FTDLL_DDR2_200MHZ
835 ldr r4, =FTDLL_DDR2_166MHZ
839 ldr r4, =FTDLL_DDR2_133MHZ
843 ldr r4, =FTDLL_DDR1_200MHZ
847 ldr r4, =FTDLL_DDR1_166MHZ
851 ldr r4, =FTDLL_DDR1_133MHZ
859 #if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
860 MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
862 MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
864 MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
865 #endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/
869 /* Set default Timing parameters */
870 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
871 tst r8, #SDRAM_DTYPE_DDR2
875 ldr r6, =DDR1_TIMING_LOW_DV
876 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
877 ldr r6, =DDR1_TIMING_HIGH_DV
878 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
882 ldr r6, =DDR2_TIMING_LOW_DV
883 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
884 ldr r6, =DDR2_TIMING_HIGH_DV
885 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
888 /* Open CS[0] window to requested size and enable it. Disable other */
890 ldr r6, =SCBAR_BASE_MASK
893 orr r3, r3, #1 /* Enable bank */
894 MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0))
896 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1))
897 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2))
898 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3))
901 mov PC, r11 /* r11 is saved link register */
904 /***************************************************************************************/
905 /* r4 holds I2C EEPROM address
906 * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
907 * r8 holds SDRAM various configuration registers value.
908 * r13 holds Link register
910 /**************************/
912 mov r13, LR /* Save link register */
914 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
915 mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
917 mov r8, r7 /* r8 save number of rows */
919 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
920 mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
922 add r8, r8, r7 /* r8 = number of rows + number of col */
925 mov r8, r7, LSL r8 /* r8 = (1 << r8) */
927 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
928 mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
932 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
933 mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
939 /**************************/
941 mov r13, LR /* Save link register */
943 /* Get SDRAM width (SPD offset 13) */
944 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
945 mov r7, #SDRAM_WIDTH_OFFSET
946 bl _i2cRead /* result in r7 */
950 /**************************/
952 mov r13, LR /* Save link register */
954 /* Set maximum CL supported by DIMM */
955 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
956 mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
961 /**************************/
962 /* R8 - sdram configuration register.
963 * Return value in flag if no-registered then Z-flag is set
966 mov r13, LR /* Save link register */
968 /* Get registered/non registered info from DIMM */
969 tst r8, #SDRAM_DTYPE_DDR2
973 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
974 mov r7, #SDRAM_MODULES_ATTR_OFFSET
975 bl _i2cRead /* result in r7 */
979 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
980 mov r7, #DIMM_TYPE_INFO_OFFSET
981 bl _i2cRead /* result in r7 */
982 tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
983 /* or Mini-RDIMM (0x10) */